Digital fractional-n phase locked loop
By introducing a spurious compensation unit into the digital fractional-N PLL to process the unfiltered and filtered control signals, the problem of low fractional spurious suppression efficiency in the prior art is solved, and the effects of high spectral purity and fast frequency establishment are achieved.
Patent Information
- Application Number
- CN202480047692.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-05-31
- Filing Date
- 2024-05-03
- Publication Date
- 2026-02-13
AI Technical Summary
In the existing technology, digital fractional-N phase-locked loops (PLLs) have problems such as low efficiency, large computational workload and potential impact on loop stability and frequency settling time in suppressing fractional spurious signals. Existing solutions have failed to effectively solve these problems.
The forward path includes a phase detector, a digital loop filter, and a numerically controlled oscillator. Combined with a digital time converter and a spurious compensation unit in the feedback path, the spurious compensation unit processes the unfiltered and filtered control signals to compensate for fractional phase errors and reduce fractional spurious signals.
It provides an output signal with low amplitude fractional spurious signals, improves spectral purity and frequency resolution, shortens frequency settling time, and maintains loop stability and flexible calibration capabilities.
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Figure CN121532948A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a digital fractional-N phase-locked loop (PLL). In particular, it enables the PLL to output an AC signal with high spectral purity. Background Technology
[0002] Frequency synthesis is an engineering field involving the generation of different signal frequencies from a single reference or time base. Typically, voltage-controlled crystal oscillators (VCXOs), digitally controlled crystal oscillators (DCXOs), or even temperature-compensated crystal oscillators (TCXOs) are used as time bases to provide a stable and low-phase-noise reference frequency for synthesizer circuits. One of the most widely used techniques in frequency synthesis is the phase-locked loop (PLL) circuit, which utilizes negative feedback to perform frequency multiplication and generates the output frequency based on the reference frequency and output frequency division or timing generation. In the following text, the term PLL circuit or PLL refers to a digital PLL circuit or an all-digital PLL circuit.
[0003] The PLL circuit uses an oscillator at the reference frequency as described above to tune the digitally controlled oscillator (DCO) and achieve a "locked-in state" where the output frequency equals the desired frequency multiplied by an integer N (integer-N PLL). Changing the value of N allows tuning the DCO across the band of interest, where the minimum frequency resolution or channel spacing equals the reference frequency. Fractional-N PLLs further develop this concept, enabling the frequency resolution to be a fraction of the reference frequency. This is achieved by dynamically changing the divider value in the feedback loop, resulting in an "average" division that becomes a fraction. While there is no direct means of dividing by a fraction, the principle of fractionality is achieved through averaging. Recent advances in this field have considered integrating the frequency-locked loop into the loop circuit, eliminating the need for a divider in the feedback loop.
[0004] Compared to integer-N PLLs, fractional-N PLLs offer better frequency resolution, greater loop bandwidth, and potentially lower phase noise, making them ideal for high-performance applications across a variety of technical fields.
[0005] Dynamically changing the divider value in the feedback loop creates unwanted spurious signals in the output spectrum. These signals are often called "fractional spurs" because their frequencies are multiples of the frequency defined by the desired fractional portion of the reference frequency used in the PLL. Generally, fractional spurs only exist when the fractional numerator is non-zero. These fractional spurs are most severe when they fall within the loop filter bandwidth, as they are not attenuated by the latter in this case. Various factors can contribute to the emergence of such spurs. The primary cause is fractional noise, which can be mitigated by the divider switching sequence generated by the Δ-Σ modulator, which reduces in-band quantization noise, and by using a loop filter to suppress out-of-band quantization noise. However, crosstalk on the DCO is not addressed by the loop filter.
[0006] One of the main methods for reducing fractional spurious signals is the use of a digital time converter (DTC). This converter can be located in the feedback loop, directly after the frequency divider, or between the inputs of the reference oscillator and the phase detector. Essentially, a DTC is a circuit capable of generating a programmable time delay that can be adjusted using digital codes. This effectively eliminates the periodic signal associated with the fractional numerator. Real-world DTC implementations exhibit several drawbacks. These often include limited resolution, random noise generation, range mismatch, and nonlinear behavior, especially in response to temperature fluctuations or voltage supply variations. These shortcomings can limit the suppression of fractional spurious signals during operation.
[0007] Several solutions have been suggested in the literature to address the drawbacks caused by defects in DTC. P. Chen et al., in May 2015... 2015 IEEE International Symposium on Circuits and Systems (ISCAS) One proposed solution of this kind, “Fractional Spur Suppression in All-Digital Phase-Locked Loops,” involves calibrating the DTC gain to compensate for associated quantization errors. However, calibrating the DTC gain only adjusts the DTC range to match the period corresponding to the desired output frequency, but it does not compensate for the nonlinearity in the DTC transfer function (which requires more refined processing).
[0008] Furthermore, fractional spurious suppression is not entirely effective, and reducing spurious levels to an acceptable level requires a relatively high computational workload. Other solutions known from the prior art offer enhanced spurious noise reduction, but these solutions may degrade key PLL performance characteristics such as loop stability or frequency settling time. Summary of the Invention
[0009] One object of the present invention is to provide a digital fraction-N PLL designed to overcome the shortcomings and limitations of the prior art.
[0010] Another objective is to provide a digital fractional-N PLL configured to provide an output AC signal containing low-amplitude fractional spurious signals.
[0011] The auxiliary purpose is to provide a digital fraction-N PLL that is configured to allow flexible calibration for compensating for fractional spuriousness.
[0012] Another auxiliary objective is to provide a digital fractional-N PLL with flexible calibration for fractional spurious compensation, which can be run in the background (online) during the operation of the main PLL.
[0013] Another auxiliary purpose is to provide an AC signal output with high spectral purity, fast frequency settling time, and the ability to be equipped with a digital fractional-N PLL with high frequency resolution.
[0014] According to a key aspect of the invention, a numerical fraction-N PLL relating to the features described in claim 1 is disclosed. Further features and embodiments of the numerical fraction-N PLL of the invention are described in the dependent claims.
[0015] This invention relates to a numerical fraction-N PLL, comprising: - Includes the forward path of the phase detector, digital loop filter, and numerically controlled oscillator; - A feedback path including feedback elements, wherein the phase detector output of the phase detector is connected to the loop filter input of the digital loop filter to provide an unfiltered control signal, and the loop filter output of the digital loop filter is connected to the oscillator input of the numerically controlled oscillator to provide a filtered control signal, wherein the unfiltered control signal and the filtered control signal each contain periodic error signals with different amplitudes from each other. - A digital time converter, which is arranged in the forward path or the feedback path and whose converter output is connected to the phase detector input of the phase detector; - A spurious compensation unit, the spurious compensation unit being arranged with two inputs and an output, wherein a first input is configured to receive an unfiltered control signal and a second input is configured to receive a filtered control signal, wherein the spurious compensation unit is configured to determine a compensation signal for a fractional phase instance along the operation of a digital fractional-N PLL, and wherein the spurious compensation unit is further arranged to output the compensation signal to a converter input of a digital time converter, or wherein the spurious compensation unit is further configured to inject the compensation signal into the unfiltered control signal for compensating for periodic error signals.
[0016] Digital fractional-N PLL building blocks not explicitly designated as digital can be analog or at least semi-analog. However, digital fractional-N PLLs can also be implemented as fully digital PLLs, where all building blocks are defined digitally at the input / output stages. Digital building blocks of digital fractional-NPLL circuits can be implemented using digital CMOS technology. All building blocks can take a reference signal and use it as a clock signal for timing operation. For some digital building blocks, using the output AC signal as a clock signal may be useful because higher frequencies may be required when oversampling is needed.
[0017] Digital fractional-N PLLs can be used in communication devices such as transceivers for wireless or wired applications, and in test and measurement devices such as medical devices (e.g., MRI systems), oscilloscopes, spectrum analyzers, and so on (this list is not exhaustive). However, this should not preclude the use of digital fractional-N PLLs in any other application where the generation of a stable clock or carrier signal is required.
[0018] Phase detectors can be configured as digital vernier phase detectors, switch phase detectors, sampling phase detectors, or time-to-digital converters; this list is not final.
[0019] The forward path can be defined as the path that carries the reference signal to the phase detector, then to the digital loop filter, and finally to the numerically controlled oscillator (CNC). Accordingly, the feedback path can refer to the path that carries a portion of the output AC signal generated by the CNC oscillator back to the input of the digital fractional-N PLL to compare it with the reference signal. In the case where the digital fractional-N PLL is configured as a dividerless digital fractional-N PLL, the feedback element can be a variable frequency divider included in the feedback path for dividing the output AC signal, or a phase interpolator, for example, in the form of a retimer circuit.
[0020] The digital loop filter can be configured as an nth-order digital IIR loop filter, or any other type of digital filter that can provide the characteristics of a digital low-pass filter. The phase detector can provide an unfiltered control signal at its output, which may contain noise and distortion generated by the non-ideals of additional building blocks of the phase detector, digital time converter, and digital fractional-N PLL, such as electrical and quantization noise and deterministic distortion. The unfiltered control signal can digitally represent an AC signal and may contain DC offset. The digital loop filter filters the unfiltered control signal to obtain a filtered control signal, which can be used to control the frequency of the output AC signal of the numerically controlled oscillator. The filtered control signal can be a digital representation of a DC signal. Both the unfiltered and filtered control signals may contain periodic error signals, which may originate from the non-ideals of the phase detector or a combination of the phase detector and digital time converter. The amplitude of the periodic error signal varies in the aforementioned control signal because the digital loop filter supports filtering of the periodic error signal, which reduces the amplitude.
[0021] Frequency control words can be fixed-point digital representations and can be used by feedback elements to set the feedback division ratio. Frequency control words can consist of an integer part and a fractional part.
[0022] The fractional phase instance of the operation can refer to the operating point where the fractional portion of the accumulated frequency control word is operated by a digital fractional-N PLL, particularly a phase detector, a digital time converter, and / or feedback element. The length of the fractional phase instance can vary depending on the resolution; in particular, the bit length of the fractional phase instance can be equal to the bit length of the fractional digital word.
[0023] The spurious compensation unit can be configured to output a compensation signal as a digital signal (such as a multi-bit signal) to a digital time converter, which can be used by the digital time converter for calibration or as an adjunct to a frequency control word used by the digital time converter to set delay / phase shift. In summary, the digital signal can either directly correct the operation of the digital time converter or only correct the input code of the digital time converter.
[0024] In summary, the spurious signal compensation unit enables the digital fractional-N PLL to provide a high-purity output AC signal by suppressing, in particular, periodic error signals, which can be represented as spurious signals included in the output AC signal. The advantage of the spurious signal compensation unit is that not only are the periodic error signals before the digital loop filter included in the compensation, but also the portion of the periodic error signal not reduced by the digital loop filter is included. Therefore, the entire control loop's operating behavior is included in the compensation, resulting in improved reduction of periodic error signals and ultimately a corresponding reduction in spurious or fractional spurious signals.
[0025] The spurious compensation unit can be further used to calibrate the digital time converter, while simultaneously operating the digital fractional-N PLL by directly outputting a compensation signal to the digital time converter and thereby performing online calibration. This can be superior to the offline calibration methods disclosed in the literature. The spurious compensation unit can be a building block capable of operating with the main digital fractional-NPLL circuitry, but not part of the main circuitry, thus acting as an auxiliary building block. This advantage can be further realized if the spurious compensation unit directly injects the compensation signal into the unfiltered control signal. In this case, while the spurious compensation unit injects the compensation signal into the unfiltered control signal, the spurious compensation unit can be recalibrated, and thus the PLL can be recalibrated. Therefore, the operation of the digital fractional-N PLL can continue uninterrupted.
[0026] Alternatively or additionally, the spurious compensation unit may provide a compensation signal to the converter input of the digital time converter, and may also simultaneously or alternately inject the compensation signal into the unfiltered control signal. As previously noted, providing a compensation signal to the digital time converter may be useful, such as for the calibration of the converter, whereby a portion of the uncompensated periodic error signal from the calibration of the digital time converter can be suppressed or compensated by the signal injected into the unfiltered control signal.
[0027] In a first embodiment of the main aspect, the feedback element can be configured as a fractional divider or a retimer circuit, and wherein the phase detector can be configured as a time-to-digital converter, particularly as a multi-bit or unit-time digital converter. The fractional divider can be used to take a divider-based configuration of a digital fractional-N PLL, thereby allowing the retimer circuit to take a divider-free configuration of a digital fractional-N PLL.
[0028] In a second embodiment of the main aspect, the spurious compensation unit may include a preprocessing stage configured with a digital high-pass filter, a digital integrator, and a proportional gain arranged in series. The spurious compensation unit is adapted to pass a filtered control signal through the preprocessing stage and is configured to sum the passed filtered control signal with an unfiltered control signal using an adder to provide a preprocessed control signal at the output of the preprocessing stage. The digital high-pass filter, digital integrator, and proportional gain may be arranged in series in the stated order, thereby operatively connecting the input of the digital high-pass filter to the output of the digital loop filter. The digital high-pass filter may also be configured as an nth-order digital IIR filter. However, this order may be lower than that of the digital IIR loop filter. Alternatively, a less complex filter design may be chosen for the digital high-pass filter, since the primary purpose of the high-pass filter is to remove the DC component contained in the filtered control signal. The preprocessed control signal may also be referred to as a pre-filtered control signal.
[0029] In a third embodiment of the main aspect, the spurious compensation unit may further include a time-interleaved low-pass filter configured with low-pass filter inputs and outputs, wherein the low-pass filter input can be connected to the preprocessing stage output, and the low-pass filter output can be coupled to a connection between the phase detector output and the loop filter input to inject the compensation signal into the unfiltered control signal for compensating for periodic error signals. The term "coupled" may refer to a situation where the low-pass filter output can be operatively connected to a connection between the phase detector output and the loop filter input. A time-interleaved filter (such as a time-interleaved low-pass filter) is a type of filter in which multiple filter channels can be used in parallel, with each channel processing a portion of the input signal. These filter channels can be configured similarly; however, it is also possible to configure some or all of the filter channels differently from each other. The output of each channel can be time-interleaved to generate a final filtered output signal for compensating for periodic error signals. The basic concept of a time-interleaved low-pass filter can be to reduce the sampling rate of individual channels and create a frequency-repeating transfer function while maintaining reasonable cost and complexity.
[0030] In another embodiment of the main aspect, the connection between the phase detector output and the loop filter input may include an injection point for injecting a compensation signal into the unfiltered control signal and a tap point for connecting a first input of the spurious compensation unit to the connection, wherein the injection point may be located between the loop filter input and the tap point. As noted, the compensation signal may be provided by the spurious compensation unit and injected into the unfiltered control signal (if the spurious compensation unit is configured to do so).
[0031] In different embodiments of the main aspects, the spurious compensation unit may further include a time-interleaved integrator configured with an integrator input and an integrator output, wherein the integrator input is connected to the preprocessing stage output, and the integrator output is coupled to a connection between the phase detector output and the loop filter input to inject the compensation signal into the unfiltered control signal; or the integrator output is connected to the converter input of the digital time converter to compensate for periodic error signals. Instead of having a time-interleaved low-pass filter, having a time-interleaved integrator may also be possible. Moreover, the time-interleaved integrator may have different channels configured identically, partially identically, or differently from each other. However, the latter two possibilities can lead to increased complexity and additional computational effort, which may be undesirable. An explanation of the time-interleaved low-pass filter can be applied accordingly.
[0032] In another embodiment of the main aspect, the connection between the phase detector output and the loop filter input may include an injection point for injecting a compensation signal into the unfiltered control signal and a tap point for connecting a first input of the spurious compensation unit to the connection, wherein the tap point may be located between the loop filter input and the injection point. The injection point may be provided in the form of a summation point.
[0033] In another embodiment of the main aspect, the time-interleaved low-pass filter or time-interleaved integrator may include a demultiplexer stage configured with two demultiplexer inputs and multiple demultiplexer outputs, wherein a first demultiplexer input may be configured to receive a pre-processed control signal, and a second demultiplexer input may be configured to receive a fractional portion of an accumulated frequency control word signal, wherein the demultiplexer stage may be arranged to output the pre-processed control signal to different demultiplexer outputs depending on the value of the fractional portion of the accumulated frequency control word signal. An accumulator may be used to accumulate the fractional portion of the frequency control word signal to obtain an accumulated frequency control word signal. Alternatively, an accumulator may be used to accumulate the frequency control word signal, and only the fractional portion of the accumulated frequency control word signal may be considered. As explained above, the value of the accumulated frequency control word can be used to select the output of the demultiplexer, which in turn can set the channels of the time-interleaved low-pass filter or time-interleaved integrator.
[0034] In another embodiment of the main aspect, when configured as a time-interleaved low-pass filter, the time-interleaved low-pass filter may include a midpoint clamping stage equipped with multiple midpoint clamping stage outputs, and may be configured with multiple low-pass filters, wherein each low-pass filter may be connected to a demultiplexer output at its low-pass filter input. The purpose of the midpoint clamping stage may be to make each low-pass filter output refer to a reference value. The preprocessed control signal input to a demultiplexer input may have a DC offset. By making the low-pass filter output refer to a predefined reference or a predefined threshold, this offset can be eliminated or at least significantly reduced. Preferably, the reference value is zero, but different values may be used as required by the design.
[0035] In another embodiment of the main aspect, when configured as a time-interleaved integrator, the time-interleaved integrator may include a midpoint clamping stage equipped with multiple midpoint clamping stage outputs, and may be configured with multiple integrators, wherein each integrator may be connected at an integrator input to a demultiplexer output. An explanation of the purpose of the midpoint clamping stage applies accordingly.
[0036] In different embodiments of the main aspect, when configured as a time-interleaved low-pass filter, each low-pass filter may be configured with a low-pass filter output, or when configured as a time-interleaved integrator, each integrator may be equipped with an integrator output, wherein the midpoint clamping stage may be configured to allow each low-pass filter output or each integrator output to reference a reference threshold, respectively.
[0037] In another embodiment of the main aspect, the midpoint clamping stage may include an averaging stage configured with multiple averaging stage inputs and averaging stage outputs, wherein each averaging stage input may be connected to a low-pass filter output (when configured as a time-interleaved low-pass filter) or an integrator output (when configured as a time-interleaved integrator), wherein the averaging stage may be configured to determine an average value based on the output signal output at the low-pass filter output or the integrator output, wherein the averaging stage output may be combined with the midpoint clamping stage output for subtracting the determined average value from the output signal output at the low-pass filter output or the integrator output. The averaging stage may be an alternative means of clamping the low-pass filter output or the integrator output to a reference.
[0038] In another embodiment of the main aspect, the time-interleaved low-pass filter or time-interleaved integrator may include a multiplexer stage configured with multiplexer inputs and multiplexer outputs, wherein each of the first number of multiplexer inputs may be connected to a midpoint clamping stage output, and wherein one of the second number of multiplexer inputs may be configured to receive an accumulated frequency control word signal, wherein the multiplexer stage may be arranged to connect different midpoint clamping stage outputs to the multiplexer outputs depending on the value of a fractional portion of the accumulated frequency control word signal to provide a compensation signal at the multiplexer output. The multiplexer output can then be connected to a digital time converter input or to an injection point.
[0039] In various embodiments of the main aspects, the time-interleaved low-pass filter or time-interleaved integrator may include an interpolation / extrapolation unit configured with multiple inputs and outputs, wherein each input may be connected to the midpoint clamping stage output, and the time-interleaved low-pass filter may be configured to interpolate or extrapolate between signals output at the midpoint clamping stage output. Interpolation of the output signal at the midpoint clamping stage output can be useful because the fractional portion of the accumulated frequency control word can have a finer resolution than the digital code controlling the time-interleaved filter. Therefore, interpolation (such as, for example, linear interpolation) between the output values of the midpoint clamping stage corresponding to additional bits in the accumulated frequency control word not represented in the time-interleaved filter can result in lower fractional spurious emissions in the AC output signal of the PLL compared to not using interpolation.
[0040] In another embodiment of the main aspect, the time-interleaved low-pass filter or time-interleaved integrator may include a multiplexer stage configured with a plurality of multiplexer inputs and multiplexer outputs, wherein each of the first number of multiplexer inputs may be connected to the output of an interpolation / extrapolation unit, and wherein one of the second number of multiplexer inputs may be configured to receive an accumulated frequency control word signal, wherein the multiplexer stage may be arranged to connect different outputs of the interpolation / extrapolation unit to the multiplexer outputs, depending on the value of a fractional portion of the accumulated frequency control word signal, to provide a compensation signal at the multiplexer outputs.
[0041] While the various embodiments of the main aspects cover different aspects of the invention, some or all of the embodiments may be combined when it is useful and feasible from a technical point of view.
[0042] According to a side of the invention, an apparatus for magnetic force measurement in magnetic resonance imaging is provided. The apparatus includes a main aspect of a digital fractional-N PLL (including any embodiment or combination thereof), wherein the digital fractional-N PLL is configured to selectively output an AC signal that can be divided into an application frequency of approximately 60, 120, 280, or 440 MHz. The AC signal can be used as an input signal for either the transmitter or receiver path of the apparatus.
[0043] Digital fractional-N PLLs enable the device to use arbitrary application frequencies with kHz resolution, which is important in the field of magnetic resonance imaging because these systems are built on proprietary specifications where the required application frequencies vary from manufacturer to manufacturer. Digital fractional-N PLLs also allow for faster establishment of the desired frequency than their corresponding integer-N PLLs due to the larger loop bandwidth resulting in lower power consumption when operating in duty cycle mode. Spurious compensation / calibration features enable measurement receivers operating on digital fractional-N PLLs to measure signals limited only by noise (which can be reduced through filtering and bandwidth reduction) and unaffected by periodic signals such as fractional spurs, which are typically impossible to eliminate with simple techniques such as filtering. Attached Figure Description
[0044] Exemplary embodiments of the invention are disclosed in the description and illustrated by means of the accompanying drawings, in which: Figure 1a This schematically illustrates a divider-based digital PLL architecture according to the prior art. Figure 1b This schematically illustrates a dividerless digital PLL architecture based on existing technology. Figure 2a 、 Figure 2b A block diagram illustrating the known prior art Figure 1a or Figure 1b A variation of the stray compensation arrangement of the PLL. Figures 3a to 3c A variation of the digital PLL architecture including the spurious compensation unit according to the invention is shown. Figures 4a to 4c The variant of the stray compensation unit is shown in more detail. Figure 5a 、 Figure 5b A block diagram of a digital PLL configured with stray compensation units is shown, including non-idealities in the injection loop. Figure 6 The simulation results show the noise floor of a digital PLL with and without spurious compensation units. Detailed Implementation
[0045] Figure 1aThe diagram schematically illustrates a digital fractional-N PLL (digital PLL for short) architecture according to the prior art. The digital PLL 1 includes a digital time converter 7, which may be located in the forward path and thus receive a reference AC signal S. ref Alternatively, it may be located in the feedback path and thus receive feedback signals from a feedback element, which in this example is a frequency divider 5 configured as a dual-mode divider coupled to the Δ-Σ modulator 6. Assuming the digital time converter 7 is located in the forward path, it can depend on the accumulated frequency control word signal S. afcw The fractional part is used to delay the reference AC signal S ref The digital time converter 7 will reference the AC signal S. ref The output is fed to the first input of phase detector 4, which is configured as a time-to-digital converter in this example, where the reference AC signal S is used. ref It is compared with the feedback signal input at the second input of phase detector 4.
[0046] Alternatively, assuming the digital time converter 7 is located in the feedback path, it can depend on the accumulated frequency control word signal S. afcw The fractional part is used to delay the feedback signal. The digital time converter 7 outputs the feedback signal to the second input of the phase detector 4, where the feedback signal is compared with the reference AC signal S input at the first input of the phase detector 4. ref Comparison. Like this frequency control word signal S. fcw It is a digital representation of a fixed-point number, where the integer part S fcw,I Set the integer division factor of frequency divider 5, and the fractional part S fcw,F The fractional division factor is set for the frequency divider 5, which works in conjunction with the Δ-Σ modulator 6. The phase detector 4 outputs an unfiltered phase detector output signal S based on the phase difference (or time difference) between the two input signals. uf The unfiltered phase detector output signal S uf It is a digital signal in multi-bit form, which may include AC components and DC offset, and the unfiltered phase detector output signal S is derived from this. uf The input is processed by digital low-pass filter 3, which acts as a loop filter. Digital low-pass filter 3 smooths the unfiltered phase detector output signal S. uf To provide the filtered phase detector output signal S f The filtered phase detector output signal S is in multi-bit signal form. f The signal is input into the numerically controlled oscillator 2, which depends on the filtered phase detector output signal S. f To set the output AC signal S out The frequency. For example, in Figure 1a It can be noted that the reference AC signal S refThe frequency is lower than the output AC signal S out The frequency.
[0047] When digital PLL 1 is operating in fractional mode, divider 5 is set to average and produce a variable value of the desired non-integer division ratio. It is known to control divider 5 in this way using a Δ-Σ modulator 6, and to achieve fine frequency resolution at the divider output by oversampling to utilize the fractional frequencies interpolated from the coarse dual-mode divider. A disadvantage of this approach is that it introduces a large quantization error at the input of time-to-digital converter 4. These quantization errors can be reduced by digital-to-time converter 7, as it can variably delay the reference AC signal S input at the first input of time-to-digital converter 4 (when in the forward path). ref The feedback signal input at the second input of the time-to-digital converter 4 (when in the feedback path) can be variably delayed. However, under various operating conditions, the time-to-digital converter 4, the digital-to-time converter 7, or a combination of both can perform poorly. Non-idealities caused by design flaws and mismatches in random manufacturing processes, combined with varying operating conditions such as electrical noise, temperature variations, aging, EMC, fluctuations in the power supply line, etc., can lead to non-ideal behavior of circuit elements. Any non-idealities in circuit elements can lead to gain errors, or higher-order nonlinearities in the digital-to-time converter 7 can lead to poor cancellation of accumulated fractional time / phase, and the compensation errors after conversion by the time-to-digital converter 4 can ultimately lead to fractional spurious emissions. In general, any non-idealities in the feedback and / or feedforward paths of the frequency divider, digital-to-time converter, and time-to-digital converter can lead to unwanted spurious emissions and noise.
[0048] Figure 1b Showing according to the prior art Figure 1a Examples of alternative implementations of the digital PLL 1 architecture. These can be found in, for example... Figure 1a The loop architecture shown in the diagram has the numerically controlled oscillator 2, digital low-pass filter 3, time-to-digital converter 4, and digital-to-time converter 7 configured or placed in the same manner. However, this loop architecture lacks the combination of frequency divider 5 and Δ-Σ modulator 6, which is replaced by a retimer circuit 8, which optionally operates in conjunction with a frequency-locked loop 9. The retimer circuit 8 and the optional frequency-locked loop 9 serve as alternative feedback elements, according to which the circuit architecture shows a division-free fractional-digital PLL. The retimer circuit 8 acts as a simple selector to select the output AC signal S used for feedback. out The correct edge. Its output is the reference AC signal S. ref The subsequent output AC signal S outThe first edge. A frequency-locked loop 9 can be added to ensure correct frequency locking. In the locked state of digital PLL 1, the output of frequency-locked loop 9 is always constant. As known from the prior art, frequency-locked loop 9 can be implemented differently from the main digital PLL architecture. Even in current dividerless fractional digital PLL architectures, a digital time converter 7 is required because the principle of spurious generation differs from that used in divider-based digital PLLs ( Figure 1a The architecture is exactly the same. The digital time converter 7 can be flexibly located in the forward or feedback path.
[0049] In addition to the possibility of calibrating the digital time converter 7 and / or the time-to-digital converter 4 to reduce the effects of non-idealities under various operating conditions, techniques known from the prior art can suppress spurious signals by using filter elements. Figure 2a and Figure 2b A block diagram illustrates the use of filter elements known from the prior art. Figure 1a or Figure 1b A variation of the stray compensation arrangement of the PLL.
[0050] Figure 2a The closed-loop transfer function in the block diagram shown can be represented as: in: X (S) Indicates the input phase / reference oscillator phase; Y (S) Indicates the output / PLL oscillator phase; E (S) This indicates interference or non-idealities in the injected forward path; H C(S) The transfer function representing the compensation filter element, especially the digital filter element in the forward path; H DCO(S) The transfer function of the numerically controlled oscillator 2 is represented; H LF(S) This represents the transfer function of a digital loop filter (digital low-pass filter). α PD This indicates a proportional signal time-to-digital converter 4.
[0051] The order of the filter elements and digital loop filter in the forward path can be interchanged, and equation (1) applies accordingly.
[0052] By considering equation (1), it can be noted that the poles of the filter loop are affected by adding filter elements. To reduce the error signal E(s), |H cThe value of Y(s) needs to be much smaller than 1, which can shift the poles of Y(s) to higher frequencies, leading to instability. The performance of the filter (especially the frequency settling time in response to a new frequency setpoint) is also degraded by adding filter elements.
[0053] Through such Figure 2b The block diagram shown below illustrates how to reduce the impact of frequency settling time degradation, where the closed-loop transfer function can be written as: in: H C(S) The transfer function represents the compensation filter element, particularly the analog filter element in the forward path, where the analog filter output is feedback; The remaining terms correspond to those definitions for equation (1).
[0054] In the context of Equation 2, |H c (s)| needs to be larger than the other terms in the denominator of (2) in order to effectively suppress the error signal E(s), that is, H c (s) must include peak resonance, which may change the poles of the PLL transfer function and may lead to instability.
[0055] Through such Figures 3a to 3c The example implementation of the digital PLL according to the invention shown here omits the disadvantages previously outlined for solutions known from the prior art. In the following, it is assumed that... Figure 1a or Figure 1b The basic configuration of the digital PLL serves as the basis for further explanation.
[0056] exist Figure 3a It can be noted that the digital time converter 7 is located in the feedback path, but it can alternatively be located in the receiving reference AC signal S. ref In the forward path. The frequency divider 5 and the Δ-Σ modulator 6 located in the feedback path are shown in a single box. Alternatively, and considering... Figure 1b Feedback element 5 corresponds to the retimer circuit. The digital PLL now includes a spurious compensation unit 10 configured as a time-interleaved integrator with two inputs. The first input is coupled to the unfiltered phase detector output signal S. uf The connection line is connected to the loop filter 3 and the input of the numerically controlled oscillator 2, through which the filtered phase detector output signal S is transmitted. f In short, the spurious signal compensation unit 10 acquires two input signals, each carrying an error signal with different amplitudes. These error signals with different amplitudes, when not compensated, serve as the output AC signal S of the digital PLL. outThe spurious signals will be significant. The spurious compensation unit 10 takes two error signals as input and determines the spurious compensation signal S that can compensate for the error. comp This suppresses the output AC signal S out Significant spurious signals are present. The spurious compensation signal S is input from the digital time converter 7. comp The spurious compensation signal can be used to calibrate the digital time converter 7 or as the accumulated frequency control word signal S input to the digital time converter 7. afcw The fractional part is added. In any case, the spurious compensation signal S comp This enables the digital time converter 7 to operate linearly as expected in all operating scenarios.
[0057] Figure 3b Show Figure 1a or Figure 1b Different examples of the application of spurious compensation unit 10 in a digital PLL, wherein spurious compensation unit 10 is also configured as a time-interleaved integrator, but the spurious compensation signal S comp The phase detector output signal S is directly injected without filtering. uf This directly suppresses error signals. The output and tap points of the time-to-digital converter 4 (where the unfiltered phase detector output signal S for the spurious compensation unit 10 is located) directly suppress error signals. uf The spurious compensation signal S is fed from the summation point between the taps. comp . Figure 3c Another variation is shown, in which the unfiltered phase detector output signal S, located at the tap point (where the spurious compensation unit 10 is used), is transmitted. uf The spurious compensation signal S is fed from the summation point between the tapped input and the input of the digital loop filter 3. comp In this example, spurious compensation unit 10 is configured as a time-interleaved low-pass filter.
[0058] Figures 3a to 3c The example implementation of the digital PLL shown in the figure provides superior solutions compared to those known from existing technologies (especially superior to those such as...). Figure 2a and Figure 2b The use of the filter elements shown in the diagram has several advantages. Figures 3a to 3c A common advantage of PLLs in this context is that they consider loop dynamics by having an additional feedback path from the input to the numerically controlled oscillator 2, which is not... Figure 2a , Figure 2bThe implementation details are as follows. With a proper design of the compensation function provided by two feedback paths, the original transfer function of the digital PLL can be maintained when calibration is enabled, which is crucial for its online operation in the background. Therefore, potential instability issues can be avoided. Furthermore, with a proper design of the feedback paths, the error transfer function has zero at the fractional grid defined by those channels of the time-interleaved compensation filter, for... Figure 2a , Figure 2b The situation is not the same for simpler loops. These zeros completely eliminate fractional spurious signals at the corresponding frequencies, something that simpler circuits cannot achieve.
[0059] Figures 4a to 4c A variation of the stray compensation unit 10 is shown in more detail. Figure 4a The stray compensation unit 10 shown is used for Figure 3c In the example, the filtered phase detector output signal S... f The signal is input to the spurious compensation unit 10 and fed through a high-pass filter 11, an integrator 12, and proportionally adjusted using a gain 13. The unfiltered, uncorrected phase detector output signal S is also included. ufc The signal input to the spurious compensation unit 10 and applied to the output of gain 13 is used to form the preprocessed control signal S. ppc High-pass filter 11 removes the filtered phase detector output signal S. f The DC component is included. The preprocessed control signal S... ppc The input is sent to the demultiplexer 14, and the demultiplexer depends on the accumulated frequency control word signal S. afcw,M The fractional part selectively includes the preprocessed control signal S. ppc The output is sent to different demultiplexer outputs. As explained earlier in this article, the digital PLL operates periodically in fractional phases, for example, if the frequency control word S... fcw The fractional part corresponds to frac (S fcw If ) = i / M (i = {1, 2, ..., M-1}), then the digital PLL will operate at a frequency of i*F ref / M operates periodically over M fractional phases. Therefore, the design aims to compensate for non-idealities at M distinct points along the fractional phase instances. M is typically chosen as... (B is an integer value), where B is typically less than the frequency control word signal S. fcw The number of fractional places.
[0060] The signal output from the demultiplexer is input into the time-interleaved low-pass filter 15', where each time-interleaved low-pass filter is configured with an in-band gain of 1, followed by the midpoint clamping stage 15. Due to the preprocessed control signal S... ppcThis may include a DC offset, which is also input to the associated low-pass filter 15'. This DC offset is eliminated by subtracting the output of low-pass filter 15' at position M / 2 (midpoint) from the outputs of all other low-pass filters. As previously mentioned, low-pass filter 15' is time-interleaved and uses F... ref / M (when) frac When (FCW)=i / M, it operates in parallel at a rate of [F]. ref Indicates reference signal S ref The frequency.
[0061] The midpoint clamping stage 15 outputs a DC-free signal (derived from each low-pass filter 15'), upon which the interpolation / extrapolation unit 18 inputs the DC-free signal and stores the relevant signal in units (shown as multiple rectangles). Depending on the value of the accumulated fractional bits, the interpolation / extrapolation unit 18 selects an individual input of the multiplexer 17 and outputs the interpolated / extrapolated value, depending on the fractional bits not covered by the time-interleaved filter from the adjacent DC-free signals stored in the unit, to said individual input. However, the interpolation / extrapolation unit 18 can be optional and can improve spurious reduction because it can increase the number of correction points. When the interpolation / extrapolation unit 18 is omitted, the DC-free signal is directly fed to the individual input of the multiplexer 17 without using the interpolation / extrapolation unit 18. The order of the midpoint clamping stage 15 and the interpolation / extrapolation unit 18 can also be interchanged, which may introduce additional computational workload. The multiplexer 17 depends on the accumulated frequency control word signal S. afcw,M* The fractional part is used to select one of the inputs. The spurious compensation signal S is provided by multiplexer 17. scop The relevant output signal is then injected into the unfiltered phase detector output signal S. uf Furthermore, the periodic errors contained therein are suppressed or at least significantly reduced.
[0062] Figure 4b The stray compensation unit 10 shown is used for Figure 3b In the example. Figure 4b The stray compensation unit is configured equally as Figure 4a The compensation unit described above provides the same functionality. The difference is that the midpoint clamping stage is followed by multiple integrators 16' instead of a low-pass filter 15'. Furthermore, the integrators can be configured identically, partially identically, or differently from each other regarding their summing capabilities. An identical configuration is preferred due to lower complexity. Additionally, this example differs in that the spurious compensation signal S provided by the multiplexer 17... scop The relevant output signal is injected into the unfiltered phase detector output signal S at different locations. uf middle.
[0063] Figure 4cShow Figure 4a , Figure 4b Alternatives to the midpoint clamping stages 15 and 16 used are employed. Instead of having each output of the low-pass filter or integrator reference a defined reference, the output signals of the low-pass filter or integrator are input to averaging stages 15" and 16" to determine an average value, which is then subtracted from each output signal. By doing so, the aforementioned DC offset is eliminated, and the midpoint clamping stage output signals contain a DC-free error signal. Figure 4c In this method, the midpoint clamping is discarded, and the output at position M / 2 also contains a signal that has been processed in the same way as all other signals in array M.
[0064] Figure 5a , Figure 5b A block diagram of a digital PLL configured with spurious compensation units is shown, including the non-ideal nature of the injected PLL loop. Figure 5a The closed-loop transfer function of the block diagram shown can be represented in the s-domain as: in: It represents or signifies a loop function and can be selected to match. In order to preserve the poles of the transfer function; H HPF(S) The transfer function of the high-pass filter representing the spurious compensation unit can be implemented, for example, in the first-order z-domain. The angular frequency is lower than the first fractional spurious frequency; H LPF(S) The transfer function of the time-interleaved low-pass filter included in the spurious compensation unit can be implemented, for example, in the z-domain as F ref The update rate given is / M. ; H DLF(S) The transfer function of a digital loop filter (digital low-pass filter); The remaining terms correspond to those definitions for equation (1).
[0065] Equation (3) presents, in particular, the time-interleaved low-pass filter 19, Figure 3c The case of a digital PLL in the configuration. It can be noted that for frequencies that are not spurious frequencies, equation (3) simplifies to: This indicates that the loop function is not affected by the spurious compensation unit. For high-pass filters H included in the spurious compensation unit... HPF The bandwidth of the low-pass filter H LPFThe frequency within the bandwidth, equation (3) simplifies to: Accordingly, stray dispersion is factored By reducing the number of loops, the stability of the loop is maintained, and if... Selected as If the transfer function remains the same, then the transfer function remains the same.
[0066] Figure 5b The closed-loop transfer function of the block diagram shown can be expressed as: in: It represents or signifies a loop function and can be selected as a match. In order to preserve the poles of the transfer function; H HPF(S) The transfer function of the high-pass filter representing the spurious compensation unit can be implemented, for example, as a first-order filter. The angular frequency is lower than the first fractional spurious frequency; H LPF(S) The transfer function of the time-interleaved low-pass filter included in the spurious compensation unit can be implemented, for example, in the z-domain as F ref The update rate given is / M. ; H DLF(S) The transfer function of a digital loop filter (digital low-pass filter); The remaining terms correspond to those definitions for equation (1).
[0067] Equation (4) presents, in particular, the time-interleaved integrator 20. Figure 3b The case of a digital PLL in the configuration. It can be noted that for frequencies that are not spurious frequencies, equation (4) simplifies to: This indicates that the loop function is not affected by the spurious compensation unit. For frequencies higher than the bandwidth of the high-pass filter included in the spurious compensation unit and close to the fractional spurious frequency, equation (4) can be approximated as: Based on this, the dispersion is classified by factor The number of loops is reduced, and the stability of the loop is maintained.
[0068] Figure 6 Shown on the left Figure 1b Example simulation results of the background noise of the digital PLL are shown on the right. Figures 3a-3cExample simulation results of the noise floor of the digital PLL in each configuration shown. In the two graphs, phase noise (vertical axis) is shown on the frequency (horizontal axis), measured in dB relative to the carrier. A 5% slope error is applied in both scenarios, while a second-order slope with 10% nonlinearity is injected into the unfiltered phase detector output signal to simulate non-ideals that may occur during common operating scenarios. The frequency control word signal is represented by an integer portion of 50 and a fractional portion of 1 / 256 in both scenarios.
[0069] On the left, it can be noted that the signal includes multiple spurious signals, with the most significant spurious signal, having an amplitude of -16.2 dB relative to the carrier, located at 250 kHz. The digital PLL, including the spurious signal compensation unit, provides a more uniform spectrum, and the highest-level spurious signal, with an amplitude of -81.1 dB relative to the carrier, is located at 500 kHz. In summary, in this demanding scenario, the spurious signal compensation unit can achieve a spurious signal reduction of approximately -65 dB relative to the carrier.
[0070] Reference symbols in the figure 1. Digital fractional-N frequency synthesizer, digital fractional-NPLL 2. Digitally Controlled Oscillator (DCO) 3. Low-pass filter (digital, loop) 4. Time-to-digital converter (digital phase detector) 5. Feedback components (e.g., digital frequency dividers) 6 Δ-Σ modulator 7 Digital Time Converter 8-timer circuit 9. Frequency Locking Loop 10 Stray Compensation Units 11 High-pass filter (digital, spurious compensation unit) 12 Integrators (Digital, Spurious Compensation Units) 13 Gain (digital, spurious compensation unit) 14 Demultiplexer 15, 16 Midpoint clamping 15' Low-pass filter (digital, spurious compensation unit) 16' Integrator (Digital, Midpoint Clamped) 15'', 16'' Average (Number, Midpoint Clamping) 17. Multiplexer 18 interpolation / extrapolation units 19. Time-interleaved low-pass filter (digital, spurious compensation unit) 20 Time-interleaved integrator (digital, spurious compensation unit) E (S) Non-ideality, interference H C(S) Transfer function filter element H DCO(S) Transfer function DCO H INT(S) Transfer function integrator (digital, spurious compensation unit) H LF(S) H DLF(S) Transfer function low-pass filter (digital, loop) H HPF(S) Transfer function high-pass filter (digital, spurious compensation unit) S f Filtered phase detector output signal S fcw Frequency control word signal S fcw,F Fractional part of the frequency control word signal S fcw,I Integer part of the frequency control word signal S afcw Fractional part of the accumulated frequency control word signal S afcw,M The fractional part of the accumulated frequency control word signal (highest B bit, ) S out Output AC signal S ppc Preprocessed control signals S ref Reference AC signal S scop Spurious compensation signal S uf Unfiltered phase detector output signal S ufc Unfiltered and calibrated phase detector output signal X (S) Input phase Y (S) Output α PD Proportional signal digital phase detector
Claims
1. A digital fractional-N phase-locked loop (PLL) (1), comprising: - Forward path, which includes a phase detector (4), a digital loop filter (3), and a numerically controlled oscillator (2); - A feedback path, comprising feedback elements (5, 6), wherein the phase detector output of the phase detector (4) is connected to the loop filter input of the digital loop filter (3) to provide an unfiltered control signal (S). uf The loop filter output of the digital loop filter (3) is connected to the oscillator input of the numerically controlled oscillator (2) to provide a filtered control signal (S). f ), wherein the unfiltered control signal (S) uf ) and the filtered control signal (S) f Each contains periodic error signals with different amplitudes. - A digital time converter (7), which is arranged in the forward path or the feedback path and whose converter output is connected to the phase detector input of the phase detector (4); - A spurious signal compensation unit (10) is provided with two inputs and an output, wherein the first input is configured to receive the unfiltered control signal (S). uf The second input is configured to receive the filtered control signal (S). f ), wherein the spurious compensation unit (10) is configured to determine the compensation signal (S) of the fractional phase instance of the operation along the digital fractional-N PLL (1). scop ), and wherein the spurious compensation unit (10) is further arranged to convert the compensation signal (S) scop The output is sent to the converter input of the digital time converter (7), or the spurious compensation unit (10) is further configured to output the compensation signal (S) to the converter input of the digital time converter (7), or wherein the spurious compensation unit (10) is further configured to output the compensation signal (S) to the converter input of the digital time converter (7). scop Inject the unfiltered control signal (S) uf This is used to compensate for the periodic error signal.
2. The digital fractional-N PLL (1) as claimed in claim 1, wherein the feedback elements (5, 6) are configured as a fractional divider or a retimer circuit, and wherein, The phase detector (4) is configured as a time-to-digital converter, preferably a multi-bit or unit-time-to-digital converter.
3. The digital fractional-N PLL (1) as described in claim 1 or 2, wherein the spurious compensation unit (10) comprises a preprocessing stage (11, 12, 13) configured with a digital high-pass filter (11), a digital integrator (12), and a scaling gain (13) arranged in series, wherein, The spurious compensation unit (10) is adapted to make the filtered control signal (S) f The filtered control signal passes through the preprocessing stages (11, 12, 13) and is configured to use an adder to process the unfiltered control signal (S) through the preprocessing stages (11, 12, 13). uf The summation is used to provide a preprocessed control signal (S) at the preprocessing stage output. ppc ).
4. The digital fractional-N PLL (1) as described in claim 3, wherein the spurious compensation unit (10) further comprises a time-interleaved low-pass filter (19) configured with a low-pass filter input and an output, wherein, The low-pass filter input is connected to the preprocessing stage output, and the low-pass filter output is coupled with the connection between the phase detector output and the loop filter input to combine the compensation signal (S) scop Inject the unfiltered control signal (S) uf In ), it is used to compensate for the periodic error signal.
5. The numerical fraction-N PLL (1) as described in claim 4, wherein, The connection between the phase detector output and the loop filter input includes a method for converting the compensation signal (S) into a signal that is compatible with the phase detector output. scop Inject the unfiltered control signal (S) uf The injection point and the tap point for connecting the first input of the spurious compensation unit (10) to the connection, wherein the injection point is located between the loop filter input and the tap point.
6. The digital fractional-N PLL (1) as claimed in claim 3, wherein the spurious compensation unit (10) further comprises a time-interleaved integrator (20) configured with an integrator input and an integrator output, wherein, The integrator input is connected to the preprocessing stage output, and the integrator output is coupled with the connection between the phase detector output and the loop filter input to combine the compensation signal (S) scop Inject the unfiltered control signal (S) uf In the integrator, or the output of the integrator is connected to the converter input of the digital time converter (7) to compensate for the periodic error signal.
7. The numerical fraction-N PLL (1) as described in claim 6, wherein, The connection between the phase detector output and the loop filter input includes a method for converting the compensation signal (S) into a signal that is compatible with the phase detector output. scop Inject the unfiltered control signal (S) uf The injection point in the loop filter and the tap point for connecting the first input of the spurious compensation unit (10) to the connection, wherein the tap point is located between the loop filter input and the injection point.
8. The digital fractional-N PLL (1) as described in any one of claims 4 to 7, wherein the time-interleaved low-pass filter (19) or the time-interleaved integrator (20) comprises a demultiplexer stage (14) configured with two demultiplexer inputs and multiple demultiplexer outputs, wherein, The first demultiplexer input is configured to receive the preprocessed control signal (S). ppc The second demultiplexer input is configured to receive the accumulated frequency control word signal (S). afcw,M The fractional part of the demultiplexer stage (14) is arranged to depend on the accumulated frequency control word signal (S). afcw,M The value of the fractional part of the preprocessed control signal (S) ppc The output is sent to different demultiplexers.
9. The digital fractional-N PLL (1) as claimed in claim 8, wherein the time-interleaved low-pass filter (19) comprises a midpoint clamping stage (15, 16) equipped with a plurality of midpoint clamping stage outputs and configured with a plurality of low-pass filters (15'), wherein, Each low-pass filter (15') is connected to a demultiplexer output at its input.
10. The digital fractional-N PLL (1) of claim 8, wherein the time-interleaved integrator (20) comprises a midpoint clamping stage (15, 16) equipped with a plurality of midpoint clamping stage outputs and configured with a plurality of integrators (16'), wherein, Each integrator (16') is connected to a demultiplexer output at its integrator input.
11. The numerical fraction-N PLL (1) as described in claim 9 or 10, wherein, Each low-pass filter (15') is configured with a low-pass filter output, or each integrator (16') is equipped with an integrator output, wherein the midpoint clamping stages (15, 16) are configured to reference each low-pass filter output or each integrator output to a reference threshold for removing the preprocessed control signal (S). ppc (Includes DC signal components) 12. The digital fraction-N PLL (1) as described in claim 9 or 10, wherein the midpoint clamping stages (15, 16) comprise averaging stages (15'', 16'') configured with a plurality of averaging stage inputs and averaging stage outputs, wherein, Each averaging stage input is connected to a low-pass filter output or an integrator output, wherein the averaging stages (15'', 16'') are configured to determine an average value based on the output signal output at the low-pass filter output or integrator output, wherein the averaging stage output is coupled to a midpoint clamping stage output for subtracting the determined average value from the output signal output at the low-pass filter output or integrator output.
13. The digital fractional-N PLL (1) as claimed in claim 11 or 12, wherein the time-interleaved low-pass filter (19) or the time-interleaved integrator (20) comprises a multiplexer stage (17) configured with multiple multiplexer inputs and multiplexer outputs, wherein, Each of the first number of multiplexer inputs is connected to the midpoint clamping stage output, and wherein one of the second number of multiplexer inputs is configured to receive the accumulated frequency control word signal (S). afcw,M ), wherein the multiplexer stage (17) is arranged to depend on the accumulated frequency control word signal (S afcw,M The value of the fractional portion of the signal is used to connect the outputs of different midpoint clamping stages to the multiplexer output to provide the compensation signal (S) at the multiplexer output. scop ).
14. The digital fractional-N PLL (1) as claimed in claim 11 or 12, wherein the time-interleaved low-pass filter (19) or the time-interleaved integrator (20) includes interpolation / extrapolation units (18) configured with a plurality of inputs and outputs, wherein, Each input is connected to the midpoint clamping stage output, wherein the time-interleaved low-pass filter (19) is configured to output at the midpoint clamping stage output and remain interpolated or extrapolated between signals within the interpolation / extrapolation unit (18).
15. The digital fractional-N PLL (1) of claim 14, wherein the time-interleaved low-pass filter (19) or the time-interleaved integrator (20) comprises a multiplexer stage (17) configured with multiple multiplexer inputs and multiplexer outputs, wherein, Each of the first number of multiplexer inputs is connected to the output of the interpolation / extrapolation unit (18), and wherein one of the second number of multiplexer inputs is configured to receive the accumulated frequency control word signal (S). afcw,M ), wherein the multiplexer stage (17) is arranged to depend on the accumulated frequency control word signal (S afcw,M The value of the fractional portion of the value is used to connect the different outputs of the interpolation / extrapolation unit (18) to the multiplexer output to provide the compensation signal (S) at the multiplexer output. scop ).