Self-adaptive following capacitive sensor chip circuit

Abstract

A self-adaptive following capacitive sensor chip circuit comprises a CDAC circuit which is respectively connected to an external load capacitor, a sampling hold circuit and a digital logic circuit and is used for tracking the external load capacitor so as to keep the capacitance value of the external load capacitor consistent with the capacitance value of the external load capacitor; the RDAC circuit is respectively connected to the digital logic circuit and the comparator circuit group and is used for generating a reference value capable of being automatically adjusted so as to adapt to external triggering actions of different degrees; the input end of the sampling hold circuit is connected between an external load capacitor and the CDAC circuit, the output end of the sampling hold circuit is connected to the comparator circuit group, and the sampling hold circuit is used for controlling and collecting an electric signal of the external load capacitor according to a signal sent to the CDAC circuit by the digital logic circuit and outputting the electric signal to the comparator circuit group for comparison and judgment; and the digital logic circuit is connected to the comparator circuit group and the sampling and holding circuit and is used for providing a control sequence signal for the sampling and holding circuit and providing an excitation voltage signal for the CDAC circuit and the RDAC circuit according to an output result of the comparator circuit group.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of capacitance detection, in particular to a self-adaptive following capacitance sensor chip circuit, which has a load capacitance continuous calibration and an external trigger judgment threshold adjustable capacitance sensor chip circuit, especially to a self-adaptive following detection chip circuit for an electronic cigarette microphone. BACKGROUND

[0002] At present, the mainstream of the field of capacitance sensors mainly uses test RC oscillation frequency to judge the working condition of external capacitance, and this scheme generally has low detection precision and cannot capture the load capacitance deviation caused by slight environmental interference, resulting in difficulty in realizing accurate detection when external calibration or detection trigger action is performed. At the same time, the load capacitance also has consistency problems, and the capacitance size of the same batch will have differences. Most chips will calibrate the load capacitance and write it into the register at the initial power-on, but in the subsequent continuous use process, temperature, humidity and other special conditions will cause the capacitance to continuously deviate, and most mainstream chips cannot calibrate the deviation in real time, thereby causing the risk of failure at the end. In actual application, different application schemes of different clients will cause great differences in external triggering, which is reflected in the difference in input signal size in the circuit. The judgment threshold of the trigger signal in most mainstream circuits is fixed and cannot be changed. At this time, light trigger users may have trigger delay, which causes the external signal to be not judged in time, and for heavy trigger users, if the judgment threshold is low, over-triggering phenomenon is easy to occur.

[0003] In this regard, some high-end chips can support threshold adjustment, but often need external circuit cooperation or use of special tools for configuration. Therefore, it is difficult for ordinary users to achieve this in the use process, which will seriously affect the actual experience of users.

[0004] Therefore, there is an urgent need in the art for a low-cost, high-precision and self-adaptive following capacitance sensor chip. SUMMARY

[0005] The present application aims to solve the problems of low detection precision, inability to continuously track external load capacitance changes and consistency problems caused by different client application habits in the prior art, and provides a self-adaptive following capacitance sensor chip circuit to realize low-cost high-precision capacitance detection, real-time tracking of slight changes in load capacitance caused by environment and other reasons, and improvement of product reliability; by continuously tracking and adjusting the trigger condition according to different application schemes of different clients, the consistency of the product can be greatly improved.

[0006] To achieve the above purpose, the present application provides a self-adaptive following capacitance sensor chip circuit, which comprises a CDAC circuit, an RDAC circuit, a sample and hold circuit, a digital logic circuit and a comparator circuit group, wherein:

[0007] The CDAC circuit is connected to the external load capacitor, the sample-and-hold circuit and the digital logic circuit respectively, and is used to track the external load capacitor to keep the capacitance value consistent with that of the external load capacitor.

[0008] The RDAC circuit is connected to the digital logic circuit and the comparator circuit group respectively, and is used to generate a reference value that can be automatically adjusted to adapt to different degrees of external triggering action.

[0009] The input end of the sample-and-hold circuit is connected between the external load capacitor and the CDAC circuit, and the output end is connected to the comparator circuit group, which is used to control the collection of the electrical signal of the external load capacitor size according to the signal sent by the digital logic circuit to the CDAC circuit, and output it to the comparator circuit group for comparison and judgment.

[0010] The digital logic circuit is also connected to the comparator circuit group and the sample-and-hold circuit, which provides the sample-and-hold circuit with a control timing signal, and generates a digital signal according to the output result of the comparator circuit group to adjust the capacitance value of the CDAC circuit and the resistance value of the RDAC circuit.

[0011] In an embodiment of the present application, the comparator circuit group includes a first comparator, a second comparator and a third comparator.

[0012] In an embodiment of the present application, the input end of the first comparator is connected to the sample-and-hold circuit, and the output end is connected to the digital logic circuit, to track the relationship between the capacitance value of the CDAC circuit and the capacitance value of the external load capacitor, specifically:

[0013] When powered on for the first time, the CDAC circuit, the sample-and-hold circuit, the first comparator and the digital logic circuit form a complete feedback loop.

[0014] The digital logic circuit generates a periodic excitation voltage signal to the CDAC circuit:

[0015] When the excitation voltage appears, the digital logic circuit controls the sample-and-hold circuit to sample the voltage signal of the voltage divider of the CDAC circuit and the external load capacitor and hold it, which is recorded as SHN voltage and output to the first comparator.

[0016] When the excitation voltage disappears, the digital logic circuit controls the sample-and-hold circuit to sample the difference between the power supply voltage and the aforementioned voltage signal and hold it, which is recorded as SHP voltage and output to the first comparator.

[0017] The first comparator compares the SHN voltage and the SHP voltage and outputs a high level or low level signal to the digital logic circuit according to the result;

[0018] The digital logic circuit adjusts the capacitance value of the CDAC circuit in a way of incremental modulation coding, and repeats the above sampling and comparison process until the capacitance value of the CDAC circuit is the same as that of the external load capacitance, and the capacitance sensor chip circuit enters a normal working state.

[0019] In an embodiment of the present application, the specific adjustment of the capacitance value of the CDAC circuit by the digital logic circuit in a way of incremental modulation coding is as follows:

[0020] The digital logic circuit increases or decreases the capacitance value of the CDAC circuit according to the first level value output by the first comparator in a first preset step;

[0021] The sample-and-hold circuit continuously samples the adjusted circuit until the first comparator outputs a level value opposite to the previous one, and then the digital logic circuit decreases or increases the capacitance value of the CDAC circuit in a second preset step;

[0022] When the output levels of the first comparator are low-high-low-high-low or high-low-high-low-high in sequence for five times in succession, the capacitance sensor chip circuit enters a normal working state.

[0023] In an embodiment of the present application, the first preset step is greater than the second preset step, the least significant bit of the CDAC circuit is 1fF, the first comparator is a high-precision dynamic comparator, and the second preset step is 1fF.

[0024] In an embodiment of the present application, the RDAC circuit includes two output ends, the output of the first output end is a target value, and the output of the second output end is a judgment threshold value, wherein the judgment threshold value is used to judge whether there is an external trigger action, and the target value is used to track the amplitude of the external trigger action; and the judgment threshold value is always smaller than the target value and is in a preset proportion to the target value.

[0025] In an embodiment of the present application, the two input ends of the second comparator are connected to the second output end of the RDAC circuit and the output end of the sample-and-hold circuit respectively, to judge whether there is an external trigger action, the output end of the second comparator is used as the signal output end of the capacitance sensor chip circuit, to output a trigger signal when the external trigger action reaches the judgment threshold value; the two input ends of the third comparator are connected to the first output end of the RDAC circuit and the output end of the sample-and-hold circuit respectively, and the output end is connected to the digital logic circuit, to set the target value according to the tracked amplitude of the external trigger action.

[0026] In an embodiment of the present application, when the capacitance sensor chip circuit enters a normal working state, an external trigger action detection is started, specifically:

[0027] The digital logic circuit presets an initial target value and an initial judgment threshold value for the RDAC circuit;

[0028] The RDAC circuit inputs the initial judgment threshold value into the second comparator, and the second comparator compares the initial judgment threshold value with the SHN voltage sampled by the sample-and-hold circuit. Meanwhile, the RDAC circuit inputs the initial target value into the third comparator, and the third comparator compares the initial target value with the SHN voltage sampled by the sample-and-hold circuit, wherein:

[0029] If the outputs of the second comparator and the third comparator are both low, it is judged that there is no external trigger action;

[0030] If the output of the second comparator is high and the output of the third comparator is low, it is judged that there is an external trigger action, but the amplitude of the external trigger action is small, and the change in the capacitance value of the external load capacitor caused by the external trigger action does not exceed the initial target value. In this case, the digital logic circuit does not need to adjust the target value.

[0031] If the outputs of the second comparator and the third comparator are both high, it is judged that there is an external trigger action, and the external trigger action is large. In this case, the digital logic circuit adjusts the target value output by the RDAC circuit according to a preset step size, and the judgment threshold value is adjusted according to a preset ratio at the same time.

[0032] After the adjusted target value and the adjusted judgment threshold value are input into the third comparator and the second comparator respectively, the foregoing steps are repeated to continuously detect the outputs of the third comparator and the second comparator, so as to track the amplitude of the external trigger action, until the output of the third comparator alternately appears as high and low, and the target value and the judgment threshold value of the RDAC circuit at this time are latched.

[0033] In an embodiment of the present application, when the capacitance sensor chip circuit enters a normal working state, the feedback loop formed by the CDAC circuit, the sample-and-hold circuit, the first comparator and the digital logic circuit still exists. If no external trigger action is detected, the CDAC circuit is adjusted by sampling and comparison in a second preset step size to track the capacitance value of the external load capacitor. If an external trigger action is detected, the CDAC circuit is not adjusted.

[0034] In an embodiment of the present application, when no external trigger action is detected, the digital logic circuit is also used to count the output result of the first comparator, and when the output of the first comparator is high, the counter is incremented by 1, and when the output of the first comparator is low, the counter is decremented by 1, and when the counter accumulates to 128 or -128, the digital logic circuit outputs a control signal to adjust the CDAC circuit.

[0035] The adaptive following capacitive sensor chip circuit provided by the present application has at least the following beneficial effects compared with the prior art: the external load capacitance is accurately tracked through the CDAC circuit and the high-precision dynamic comparator, instead of the traditional scheme of counting the RC oscillation as a reference value, the precision can reach 1fF, and the capacitance offset caused by the external environment can be compensated for throughout the service life of the entire circuit, greatly reducing the failure risk of the overall circuit; the RDAC circuit is used to calibrate different degrees of external trigger actions, the target value is adaptively adjusted to track the size of the trigger action, and a judgment threshold is set to detect whether there is an external trigger action, and the two can be combined to meet the application of different clients and adapt to different application schemes, and high consistency can be achieved. BRIEF DESCRIPTION OF DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0037] Figure 1 The circuit structure diagram of an embodiment of the present application;

[0038] Figure 2 The working flow diagram of an embodiment of the present application.

[0039] Explanation of reference numerals: 101-CDAC circuit; 102-RDAC circuit; 103-sampling and holding circuit; 104-digital logic circuit; 1051-first comparator; 1052-second comparator; 1053-third comparator. DETAILED DESCRIPTION

[0040] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0041] Figure 1 A circuit structure diagram of an embodiment of the present application, Figure 2 A working flow diagram of an embodiment of the present application, as Figure 1 and Figure 2 An adaptive following capacitive sensor chip circuit is provided in an embodiment of the present application, which is applied in an electronic cigarette microphone detection circuit, comprising a CDAC (capacitive digital analog converter) circuit 101, an RDAC (resistive digital analog converter) circuit 102, a sample and hold circuit 103, a digital logic circuit 104 and a comparator circuit group, wherein:

[0042] The CDAC circuit 101 is connected to an external load (in this embodiment, an electronic cigarette microphone sensor) capacitor, the sample and hold circuit 103 and the digital logic circuit 104, respectively, to track the external load capacitor to keep the same size as the external load capacitor;

[0043] The RDAC circuit 102 is connected to the digital logic circuit 104 and the comparator circuit group, respectively, to generate a reference value that can be automatically adjusted to adapt to different degrees of external triggering actions;

[0044] The input end of the sample and hold circuit 103 is connected between the external load capacitor and the CDAC circuit 101, and the output end is connected to the comparator circuit group, to control the collection of the electrical signal of the external load capacitor size according to the signal sent by the digital logic circuit 104 to the CDAC circuit 101, and output it to the comparator circuit group for comparison and judgment;

[0045] The digital logic circuit 104 is also connected to the comparator circuit group and the sample and hold circuit 103, to provide control timing signals for the sample and hold circuit 103, and to generate digital signals according to the output results of the comparator circuit group to adjust the size of the capacitance value of the CDAC circuit 101 and the resistance value of the RDAC circuit 102.

[0046] In this embodiment, the comparator circuit group comprises a first comparator 1051, a second comparator 1052 and a third comparator 1053.

[0047] In this embodiment, the input end of the first comparator 1051 is connected to the sample and hold circuit 103, and the output end is connected to the digital logic circuit 104, to track the size relationship between the capacitance value of the CDAC circuit 101 and the capacitance value of the external load capacitor, specifically:

[0048] When powered on for the first time, the CDAC circuit 101, the sample and hold circuit 103, the first comparator 1051 and the digital logic circuit 104 form a complete feedback loop;

[0049] The digital logic circuit 104 generates a periodic excitation voltage signal to the CDAC circuit 101:

[0050] When the excitation voltage appears, the digital logic circuit 104 controls the sample-and-hold circuit 103 to sample the size of the divided voltage signal of the CDAC circuit 101 and the external load capacitor and hold it, record it as the SHN voltage and output it to the first comparator 1051;

[0051] When the excitation voltage disappears, the digital logic circuit 104 controls the sample-and-hold circuit 103 to sample the difference between the power supply voltage (the CDAC circuit is internally connected to the power supply voltage, which is the function and connection mode of the CDAC product itself, so it is not shown in the figure, and the power supply voltage is the internal voltage of the entire chip, which supplies power to all modules (comparator group, logic module, CDAC, RDAC, sample-and-hold, etc.), which is a regular setting of the chip, so the power supply voltage part is not shown in the figure) and the aforementioned divided voltage signal and hold it, record it as the SHP voltage and output it to the first comparator 1051;

[0052] The first comparator 1051 compares the size of the SHN voltage and the SHP voltage and outputs a high or low signal to the digital logic circuit 104 according to the result;

[0053] The digital logic circuit 104 adjusts the capacitance value of the CDAC circuit 101 by means of delta modulation encoding (DM), and then repeats the above sampling and comparison process until the capacitance value of the CDAC circuit 101 is the same as that of the external load capacitor, and the capacitance sensor chip circuit enters the normal working state.

[0054] For clarity, this embodiment sets the capacitance value of the CDAC circuit 101 as C1, the capacitance value of the external load capacitor as C2, and the power supply voltage as V s Therefore, the value of the SHN voltage sampled when the excitation voltage appears is:

[0055]

[0056] The value of the SHP voltage sampled when the excitation voltage disappears is:

[0057]

[0058] By comparing the magnitudes of these two voltage values using the first comparator 1051, it can be determined whether the capacitance value of the CDAC circuit 101 is consistent with the capacitance value of the external load capacitance. If the capacitance values of both are consistent, i.e., C1 = C2, then the SHN voltage and the SHP voltage are of the same magnitude, both being half of the power supply voltage. If the SHN voltage is not lower than the SHP voltage, then C1 ≥ C2, that is, the capacitance value of the CDAC circuit 101 is greater than the capacitance value of the external load capacitance. Assuming that the output of the first comparator 1051 is high level (such as digital signal 1) at this time, the digital logic circuit 104 needs to control the CDAC circuit 101 to reduce the capacitance value according to the high-level input; conversely (C1 < C2), when the output of the first comparator 1051 is low level (such as digital signal 0), the digital logic circuit 104 needs to control the CDAC circuit 101 to increase the capacitance value. In another embodiment, the comparator can output 1 when C1 > C2 and output 0 when C1 ≤ C2. In other embodiments, the judgment of the preset high and low levels can also be replaced. The present invention does not limit the specific judgment logic in this regard, and the logic judgment value of the first comparator can be preset according to requirements during the implementation process.

[0059] In an embodiment of the present invention, the digital logic circuit 104 adjusts the capacitance value of the CDAC circuit 101 by means of delta modulation coding, specifically as follows:

[0060] The digital logic circuit 104 increases or decreases the capacitance value of the CDAC circuit 101 according to the level value (high level or low level) output by the first comparator 1051 for the first time at a first preset step size;

[0061] The sample and hold circuit 103 continuously samples the adjusted circuit until the first comparator 1051 first outputs a level value opposite to the previous one, and then the digital logic circuit 104 decreases or increases the capacitance value of the CDAC circuit 101 at a second preset step size;

[0062] When the output levels of the first comparator 1051 are successively low-high-low-high-low (01010) or high-low-high-low-high (10101) for five consecutive times, the capacitance sensor chip circuit enters the normal working state.

[0063] In this embodiment, the first preset step size is greater than the second preset step size. The least significant bit (LSB) of the CDAC circuit 101 is 1 fF, the first comparator 1051 is a high-precision dynamic comparator, and the second preset step size is 1 fF. Therefore, the output result of the first comparator can control the CDAC circuit through the digital logic circuit to achieve consistency with the capacitance value of the external load capacitance, and the CDAC tracking accuracy of the present invention can reach 1 fF.

[0064] This embodiment uses a 13-bit CDAC circuit with a minimum precision setting of 1fF to illustrate this adjustment process. After power-on, the CDAC defaults to a capacitor value of 13'b0000010000000 (128fF), a first preset step size of 13'b0000000100000 (32fF), and a second preset step size of 13'b0000000000001 (1fF). Assuming the external load capacitance is 190fF, the first comparator output is 0. The digital logic circuit then controls the CDAC to increase by 32fF to 160fF according to the first preset step size. After sampling and comparing the SHN voltage and SHP voltage again, the first comparator output is still 0. So, it increases by another 32fF to 192fF. At this point, the capacitance value of the CDAC exceeds the external load capacitance, so the output of the first comparator becomes 1. In other words, the first comparator outputs a different level signal for the first time. It can be assumed that the difference between the external load capacitance and the CDAC capacitance is within 32fF, and the CDAC can be adjusted with a more precise step size.

[0065] Next, the step size is adjusted to a more precise second preset step size of 1fF. The CDAC capacitance value then begins to decrease according to the second preset step size. After decreasing by 1fF from 192fF to 191fF, the output of the first comparator is still 1. Continue decreasing by 1fF to 190fF. At this point, the target capacitance value has been tracked, and the two capacitance values ​​are now the same, but the first comparator can still output 1.

[0066] Although the target has been tracked, the comparison continues to ensure tracking accuracy. CDAC is further decreased by 1 fF to 189 fF, the first comparator outputs 0, and CDAC is increased by 1 fF (according to the second preset step size) to 190 fF, the first comparator outputs 1. After five consecutive iterations, the output of the first comparator is 101010, and CDAC will continuously change between 189 fF and 190 fF. In other embodiments, the output of the first comparator can also be 01010 after five consecutive iterations. Therefore, when the digital logic circuit 104 receives a change in the output of the first comparator 1051 from 10101 or 01010, it outputs a normal operation signal, indicating that the capacitance sensor chip circuit has entered normal operation.

[0067] In one embodiment of the present invention, when the capacitance sensor chip circuit enters the normal working state, the feedback loop formed by the CDAC circuit 101, the sample and hold circuit 103, the first comparator 1051 and the digital logic circuit 104 still exists. If no external trigger action is detected, the CDAC circuit continues to be adjusted by sampling and comparison with a second preset step size to track the capacitance value of the external load capacitor. If an external trigger action is detected, the CDAC circuit is not adjusted.

[0068] In one embodiment of the present invention, in order to reduce chip power consumption and avoid the large loss caused by continuous tracking, when no external trigger action is detected, the digital logic circuit 104 can also count the output result of the first comparator 1051. When the output of the first comparator 1051 is high level (1), the counter is incremented by 1, and when it is low level (0), the counter is decremented by 1. When the counter accumulates to 128 or -128, the digital logic circuit 104 outputs a control signal to adjust the CDAC circuit 101.

[0069] For example, if the external capacitor is 200fF and the internal CDAC is also adjusted to 200fF, under certain circumstances without external triggering, if the external capacitor changes due to environmental reasons, say to 210fF, because the adjustment step size is 1fF, the output of the first comparator will be zero for the next 10 comparisons. At this time, the digital logic circuit will count to -10 (because each time it receives a 0 signal from the comparator output, the logic circuit will decrement by 1; if it receives a 1 signal from the comparator output, the logic circuit will increment by 1). If the external load capacitor remains at 210fF, after 128 comparisons, the digital logic circuit will count to -128, at which point it will control the CDAC to perform DM modulation with a second preset step size of 1fF LSB (the modulation working principle is the same as described above, so it will not be repeated). If the external load capacitor changes to 198fF, the next comparator output will be 1, and the subsequent digital logic circuit will increment by 1 from the original -10 to -9, and so on, until DM modulation is performed when the count reaches 128.

[0070] The CDAC circuit of this invention can calibrate the external load capacitor at the initial power-on stage, which can improve the problem of external load capacitor consistency in the prior art; during normal operation of the circuit, it can also continuously track and calibrate the external load capacitor to offset the deviation of the external load capacitor caused by environmental changes such as temperature and humidity, which can significantly reduce the failure risk of electronic cigarettes.

[0071] This invention directly outputs the comparator result to the logic terminal and controls the CDAC change through DM modulation, instead of using a complex SRA logic control method. Existing SRA logic requires quantizing the entire input signal. For example, at startup, the DAC generates an intermediate level of the reference voltage, the comparator compares this level with the input analog signal, and the result is stored in a register as the most significant bit. Then, the DAC level is adjusted sequentially, determining the second most significant bit, least significant bit, etc., bit by bit, resulting in an N-bit digital output after N comparisons. For example, a 12-bit SAR ADC requires 12 comparison steps to finally output a 12-bit digital signal. This process lacks incremental quantization and instead approximates the true signal amplitude bit by bit. In contrast, the DM modulation method of this invention does not quantize the input signal itself, but only the difference between it and the previous moment, represented by only one bit of binary code. For example, if the current signal is larger than the previous moment, it outputs 1; if it is smaller, it outputs 0. Subsequent logic circuits only accept the 1-bit comparator output signal. If it accepts 1, it controls the CDAC to decrease the step size ΔC; if it accepts 0, it controls the CDAC to increase the step size ΔC. The step size ΔC is generally fixed, but this invention uses a larger step size initially when tracking the external capacitor after power-on. After the comparator first outputs a result opposite to the previous one, the logic circuit adjusts to the minimum precision. For example, if the comparator consistently outputs 1 during the initial tracking process after power-on, the CDAC decreases continuously with a larger step size of 32fF. When the comparator first outputs 0, the logic circuit determines that the difference between the external capacitor and the CDAC is within 32fF, and the subsequent tracking step size is adjusted to 1fF. The DM modulation used in this invention achieves high-precision tracking through adjustment only by the output of a single comparator and the logic circuit, making it more suitable for scenarios requiring low power consumption, such as detection chips for electronic cigarette microphones. Furthermore, the circuit structure is simple and has low bandwidth usage.

[0072] In one embodiment of the present invention, the RDAC circuit 102 includes two output terminals. The output of the first output terminal is a set target value, and the output of the second output terminal is a judgment threshold. The judgment threshold is used to determine whether there is an external trigger action, and the target value is used to track the magnitude of the external trigger action. The judgment threshold is always less than the target value and is proportional to it.

[0073] In one embodiment of the present invention, the two input terminals of the second comparator 1052 are respectively connected to the second output terminal of the RDAC circuit 102 and the output terminal of the sample-and-hold circuit 103 to determine whether there is an external trigger action. The output terminal of the second comparator 1052 serves as the signal output terminal of the capacitive sensor chip circuit, and is used to output a trigger signal when the external trigger action reaches the judgment threshold. The output of the second comparator can be directly used as the chip's output port to the outside, and the user can process the output result of the port himself. The present invention does not specifically limit this. The two input terminals of the third comparator 1053 are respectively connected to the first output terminal of the RDAC circuit 102 and the output terminal of the sample-and-hold circuit 103, and the output terminal is connected to the digital logic circuit 104 to set a target value according to the magnitude of the tracked external trigger action.

[0074] In one embodiment of the present invention, when the capacitance sensor chip circuit enters normal working state, an external trigger action detection is initiated, specifically as follows:

[0075] Digital logic circuit 104 presets an initial target value and an initial judgment threshold for RDAC circuit 102;

[0076] RDAC circuit 102 inputs the initial judgment threshold to the second comparator 1052. The second comparator 1052 compares the initial judgment threshold with the SHN voltage sampled by the sample-and-hold circuit 103. Simultaneously, RDAC circuit 102 inputs the initial target value to the third comparator 1053. The third comparator 1053 compares the initial target value with the SHN voltage sampled by the sample-and-hold circuit 103, wherein:

[0077] If the outputs of the second comparator 1052 and the third comparator 1053 are both low (0), it is determined that there is no external trigger action.

[0078] If the output of the second comparator 1052 is high (1) and the output of the third comparator 1053 is low (0), it is determined that there is an external trigger action. However, the amplitude of the external trigger action is small, and the change in the capacitance value of the external load capacitor caused by it does not exceed the initial target value. At this time, the digital logic circuit 104 does not need to adjust the target value.

[0079] If the outputs of the second comparator 1052 and the third comparator 1053 are both high (1), it is determined that there is an external trigger action and the external trigger action is large. At this time, the digital logic circuit 104 adjusts the target value output by the RDAC circuit 102 according to the preset step size, and determines that the threshold is adjusted simultaneously according to the preset ratio.

[0080] After inputting the adjusted target value and judgment threshold into the third comparator 1053 and the second comparator 1052 respectively, the aforementioned steps are repeated to continuously detect the output of the third comparator 1053 and the second comparator 1052 in order to track the magnitude of the external trigger action until the output of the third comparator 1053 continuously alternates between high and low levels (0 and 1 alternate), at which point the target value and judgment threshold of the RDAC circuit 102 are latched.

[0081] This embodiment uses a 5-bit RDAC as an example to illustrate the external trigger action judgment process. It is assumed that the RDAC defaults to an initial target value of 11000, and the initial judgment threshold is set to 0.1100 according to a preset ratio. The values ​​are output to the third and second comparators for judgment. If both outputs are 0, it is determined that there is no external trigger action. At this point, as explained above, the voltage at the connection point between the external load capacitor and the CDAC should be half of the input CDAC power supply voltage. When an external trigger action occurs, this voltage value will change abruptly, that is, the airflow disturbance during user operation will be transformed into a voltage change. Specifically, the second comparator output will be 1, and the third comparator output will be 0. This indicates the presence of an external trigger action. Since the actual capacitance change is between the initial judgment threshold and the initial target value, the initial target value setting can be considered appropriate and does not require adjustment. If both comparator outputs are 1, it is determined that an external trigger action has occurred, and the external trigger action is large, requiring adjustment of RDAC. Assuming the adjustment step size is 1, i.e., 5'b00001, the digital logic circuit 104 controls RDAC to increase the initial target value by 5'b00001. The threshold value changes accordingly according to a preset ratio. Then, the outputs of the two comparators are checked to determine whether the target value has been adjusted to a suitable value. During this process, when adjusting with a step size of 5'b00001, the suitable target value is not immediately reached; the outputs of the two comparators will initially remain unchanged. When both values ​​are 1, the target value of RDAC will increase when a suitable target is tracked. This will then result in the second comparator outputting 1 and the third comparator outputting 0. The digital logic circuit 104 controls RDAC to decrease the target value by 5'b00001. If the third comparator output becomes 1 after the decrease (i.e., both comparators are 1), the target value will continue to increase. This process continues until the output of the third comparator alternates between 0 and 1. At this point, the tracked target value is considered suitable, and the target value of RDAC at this time is latched along with the judgment threshold. The RDAC tracking process is similar to CDAC capacitor tracking, thus enabling adaptive judgment for different client applications, improving the user experience. For electronic microphones, it can prevent delayed triggering during light intake or overexposure during heavy intake.

[0082] This invention determines the presence of an external trigger signal against an external load capacitor by comparing a reference value with the change in electrical signal caused by the capacitor change using a comparator. However, the strength of external trigger actions varies among different customers. If a fixed reference value is set initially, it may fail to detect triggers with weak trigger strengths, while causing longer detection times for stronger triggers. Therefore, this invention utilizes an RDAC (Real-Diagnostic Capacitor) to set the reference value (in this invention, this refers to the judgment threshold and target value). By adjusting the RDAC using a comparator to set an adaptive reference value, a better consistency experience can be provided for different customers. For example, suppose the initial judgment threshold is set to 20, and the target value to 40 (the ratio of these two values ​​is fixed by the logic circuit during chip design and cannot be changed in actual operation). Suppose the customer's trigger action strength is 15. In a system without RDAC adaptive adjustment, the chip would determine that there is no external trigger action (the trigger strength must be greater than the judgment threshold). In this invention, the initial judgment threshold and target value are set to be smaller, for example, 5 and 10 respectively. Then, when the customer's trigger action strength is 15, it will determine that an external trigger action exists and exceeds the target value. The RDAC will then be adjusted and increased by the digital logic circuit until the target value is adjusted to 15, at which point the judgment threshold is 7. This not only allows for excellent judgment of the customer's triggering behavior but also avoids overjudgment problems caused by initially setting the threshold to a very small value (to accommodate customers with weak triggering force). (In some applications with sensitive capacitors, if the initial judgment threshold is set to 2 and the customer's force is 50, the chip's judgment triggering time will be longer from triggering to canceling the trigger.) Therefore, this invention, through the adaptive adjustment of the RDAC and comparator in conjunction with the comparator, can meet the needs of different customers (with different sensitivities) or different usage habits, significantly improving product consistency.

[0083] In one embodiment of the present invention, the judgment threshold is preferably set to one-half of the target value.

[0084] The adaptive tracking capacitance sensor chip circuit provided by this invention has the following advantages compared with the prior art: it achieves accurate tracking of the external load capacitance through a CDAC circuit and a high-precision dynamic comparator, replacing the traditional scheme of using RC oscillation counting as a reference value. The accuracy can reach 1fF, and it can compensate for capacitance deviation caused by the external environment throughout the entire circuit's operating life, significantly reducing the overall circuit failure risk. The RDAC circuit calibrates for different levels of external triggering actions, adaptively adjusts the target value to track the magnitude of the triggering action, and simultaneously sets a judgment threshold to detect the existence of external triggering actions. The combination of these two can meet the needs of different client applications and adapt to different application schemes, achieving high consistency in use.

[0085] Those skilled in the art will understand that the accompanying drawings are merely schematic diagrams of one embodiment, and the modules or processes shown in the drawings are not necessarily essential for implementing the present invention.

[0086] Those skilled in the art will understand that the modules in the apparatus of the embodiments can be distributed in the apparatus of the embodiments as described in the embodiments, or they can be located in one or more devices different from this embodiment with corresponding changes. The modules of the above embodiments can be combined into one module, or they can be further divided into multiple sub-modules.

[0087] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An adaptive following capacitive sensor chip circuit, characterized in that, It includes a CDAC circuit, an RDAC circuit, a sample-and-hold circuit, a digital logic circuit, and a comparator circuit group, wherein: The CDAC circuit is connected to the external load capacitor, the sample-and-hold circuit, and the digital logic circuit, respectively, to track the external load capacitor and maintain a capacitance value consistent with that of the external load capacitor. The RDAC circuit is connected to the digital logic circuit and the comparator circuit group respectively, and is used to generate a reference value that can be automatically adjusted to adapt to different external triggering actions. The input terminal of the sample-and-hold circuit is connected between the external load capacitor and the CDAC circuit, and the output terminal is connected to the comparator circuit group. It is used to control the acquisition of an electrical signal of the size of the external load capacitor according to the signal sent to the CDAC circuit by the digital logic circuit, and output it to the comparator circuit group for comparison and judgment. The digital logic circuit is also connected to the comparator circuit group and the sample-and-hold circuit to provide control timing signals for the sample-and-hold circuit and to generate digital signals based on the output of the comparator circuit group to adjust the capacitance value of the CDAC circuit and the resistance value of the RDAC circuit.

2. The adaptive following capacitive sensor chip circuit according to claim 1, characterized in that, The comparator circuit group includes a first comparator, a second comparator, and a third comparator.

3. The adaptive following capacitive sensor chip circuit according to claim 2, characterized in that, The input of the first comparator is connected to the sample-and-hold circuit, and the output is connected to the digital logic circuit to track the relationship between the capacitance value of the CDAC circuit and the capacitance value of the external load capacitor, specifically: Upon initial power-on, the CDAC circuit, the sample-and-hold circuit, the first comparator, and the digital logic circuit form a complete feedback loop; The digital logic circuit generates a periodic excitation voltage signal for the CDAC circuit: When the excitation voltage occurs, the digital logic circuit controls the sample-and-hold circuit to sample and hold the voltage divider signal between the CDAC circuit and the external load capacitor, record it as the SHN voltage, and output it to the first comparator. When the excitation voltage disappears, the digital logic circuit controls the sample-and-hold circuit to sample and hold the difference between the power supply voltage and the aforementioned voltage divider signal, record it as the SHP voltage, and output it to the first comparator. The first comparator compares the magnitudes of the SHN voltage and the SHP voltage and outputs a high-level or low-level signal to the digital logic circuit based on the result. After the digital logic circuit adjusts the capacitance value of the CDAC circuit through incremental modulation coding, it repeats the above sampling and comparison process until the capacitance value of the CDAC circuit is the same as the capacitance value of the external load capacitor, at which point the capacitance sensor chip circuit enters normal working state.

4. The adaptive following capacitive sensor chip circuit according to claim 3, characterized in that, The digital logic circuit adjusts the capacitor value of the CDAC circuit using incremental modulation encoding as follows: The digital logic circuit increases or decreases the capacitance value of the CDAC circuit according to the first preset step size based on the level value of the first output of the first comparator. The sample-and-hold circuit continuously samples the adjusted circuit until the first comparator outputs a level value opposite to the previous one. Then, the digital logic circuit decreases or increases the capacitance value of the CDAC circuit according to the second preset step size. When the output level of the first comparator is low-high-low-high or high-low-high-low for five consecutive times, the capacitive sensor chip circuit enters normal operation.

5. The adaptive following capacitive sensor chip circuit according to claim 4, characterized in that, The first preset step size is greater than the second preset step size, the least significant bit of the CDAC circuit is 1fF, the first comparator is a high-precision dynamic comparator, and the second preset step size is 1fF.

6. The adaptive following capacitive sensor chip circuit according to claim 3, characterized in that, The RDAC circuit includes two output terminals. The output of the first output terminal is the target value, and the output of the second output terminal is the judgment threshold. The judgment threshold is used to determine whether there is an external trigger action, and the target value is used to track the magnitude of the external trigger action. The judgment threshold is always less than the target value and is in a preset ratio with it.

7. The adaptive following capacitive sensor chip circuit according to claim 6, characterized in that, The two inputs of the second comparator are respectively connected to the second output of the RDAC circuit and the output of the sample-and-hold circuit to determine whether there is an external trigger action. The output of the second comparator serves as the signal output of the capacitive sensor chip circuit, and is used to output a trigger signal when the external trigger action reaches the judgment threshold. The two inputs of the third comparator are respectively connected to the first output of the RDAC circuit and the output of the sample-and-hold circuit, and the output is connected to the digital logic circuit to set a target value according to the magnitude of the tracked external trigger action.

8. The adaptive following capacitive sensor chip circuit according to claim 7, characterized in that, Once the capacitance sensor chip circuit enters normal operating mode, an external trigger action detection is initiated, specifically as follows: The digital logic circuit presets an initial target value and an initial judgment threshold for the RDAC circuit. The RDAC circuit inputs an initial judgment threshold to the second comparator, which compares the initial judgment threshold with the SHN voltage sampled by the sample-and-hold circuit. Simultaneously, the RDAC circuit inputs an initial target value to the third comparator, which compares the initial target value with the SHN voltage sampled by the sample-and-hold circuit. If the outputs of the second comparator and the third comparator are both low, it is determined that there is no external trigger action; If the output of the second comparator is high and the output of the third comparator is low, it is determined that there is an external trigger action. However, the external trigger action is small and the change in the capacitance value of the external load capacitor caused by it does not exceed the initial target value. In this case, the digital logic circuit does not need to adjust the target value. If the outputs of the second comparator and the third comparator are both high, it is determined that there is an external trigger action and the external trigger action is large. At this time, the digital logic circuit adjusts the target value output by the RDAC circuit according to a preset step size, and the threshold is adjusted simultaneously according to a preset ratio. After inputting the adjusted target value and judgment threshold into the third comparator and the second comparator respectively, the aforementioned steps are repeated to continuously detect the outputs of the third comparator and the second comparator in order to track the magnitude of the external trigger action until the output of the third comparator continuously alternates between high and low levels, at which point the target value and judgment threshold of the RDAC circuit are latched.

9. The adaptive following capacitive sensor chip circuit according to claim 7, characterized in that, When the capacitance sensor chip circuit enters normal operation, the feedback loop formed by the CDAC circuit, the sample-and-hold circuit, the first comparator, and the digital logic circuit still exists. If no external trigger action is detected, the CDAC circuit continues to be adjusted in a second preset step size by sampling and comparison to track the capacitance value of the external load capacitor. If an external trigger action is detected, the CDAC circuit is not adjusted.

10. The adaptive following capacitive sensor chip circuit according to claim 9, characterized in that, When no external trigger action is detected, the digital logic circuit is used to count the output result of the first comparator. When the output of the first comparator is high, the counter is incremented by 1, and when it is low, the counter is decremented by 1. When the counter accumulates to 128 or -128, the digital logic circuit outputs a control signal to adjust the CDAC circuit.

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