IEC task scheduling method, device and equipment based on hardware interruption and medium

Abstract

The invention relates to the technical field of IEC tasks, in particular to an IEC task scheduling method and device based on hardware interruption, equipment and a medium, and the method comprises the following steps: determining an interruption number corresponding to an interruption flag bit and an interruption execution program corresponding to the interruption number by responding to the interruption flag bit set in a hardware peripheral; writing the interrupt number into a preset event bitmap according to the interrupt execution program to obtain an updated event bitmap and trigger an interrupt scheduler of the interrupt execution program; analyzing the updated event bitmap according to the interrupt scheduler to obtain an IEC task ID corresponding to at least one analysis interrupt number in the updated event bitmap; and according to the priority of each IEC task ID, inserting each IEC task ID into a priority ready queue and executing task scheduling, thereby realizing real-time response and execution of the IEC tasks based on hardware interruption. And the response delay of the system to high-priority external events is optimized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of IEC tasks, and particularly relates to an IEC task scheduling method and device based on a hardware interrupt, equipment and a medium. BACKGROUND

[0002] The IEC 61131-3 standard defines the programming model and task concept of a PLC, and tasks are usually scheduled according to a cycle (periodic task) or an event (event task). Traditional PLC scheduling is completed by a software timer and a task manager (RTOS or self-developed scheduler).

[0003] For interrupts caused by strong real-time or external asynchronous events (such as emergency shutdown, pulse counting, high-speed input), pure software polling or task scheduling based on a system clock may have problems such as response delay, jitter or excessive CPU time occupation. SUMMARY

[0004] The present application aims to provide an IEC task scheduling method and device based on a hardware interrupt, equipment and a medium, which solves the problems in the prior art.

[0005] The present application is implemented by the following technical solutions:

[0006] In a first aspect, the present application provides an IEC task scheduling method based on a hardware interrupt, comprising:

[0007] In response to an interrupt flag bit set in a hardware peripheral, determining an interrupt number corresponding to the interrupt flag bit and an interrupt execution program corresponding to the interrupt number;

[0008] According to the interrupt execution program, writing the interrupt number into a preset event bitmap to obtain an updated event bitmap and triggering an interrupt scheduler of the interrupt execution program;

[0009] According to the interrupt scheduler, analyzing the updated event bitmap to obtain an IEC task ID corresponding to at least one analysis interrupt number in the updated event bitmap;

[0010] According to the priority of each IEC task ID, inserting each IEC task ID into a priority ready queue;

[0011] According to the priority ready queue, performing task scheduling to realize real-time response and execution of IEC tasks based on a hardware interrupt.

[0012] Preferably, in response to the interrupt flag bit set in the hardware peripheral, determining the interrupt number corresponding to the interrupt flag bit and the interrupt execution program corresponding to the interrupt number comprises:

[0013] According to a preset hardware interrupt source, a set bit of an interrupt flag bit in a hardware peripheral device is responded, the hardware interrupt source corresponds to the hardware peripheral device, and the hardware interrupt source is at least one of an external digital input interrupt, a high-precision hardware timer interrupt, a pulse counting peripheral device interrupt, and a communication receiving interrupt pre-configured on a PLC hardware platform;

[0014] According to the hardware interrupt source and a preset hardware interrupt and logical interrupt number mapping table, a corresponding interrupt number of the interrupt flag bit is determined;

[0015] According to the interrupt number, an interrupt execution program corresponding to the interrupt number is determined.

[0016] Preferably, the interrupt execution program writes the interrupt number into a preset event bitmap, obtains an updated event bitmap, and triggers an interrupt scheduler of the interrupt execution program, including:

[0017] According to the interrupt execution program, a key context in the hardware peripheral device is stored into a memory;

[0018] According to the interrupt execution program, an interrupt flag bit of the hardware peripheral device is cleared;

[0019] According to the interrupt execution program, the interrupt number is written into a preset event bitmap, an updated event bitmap is obtained, and an interrupt scheduler of the interrupt execution program is triggered.

[0020] Preferably, the interrupt execution program writes the interrupt number into a preset event bitmap, obtains an updated event bitmap, and triggers an interrupt scheduler of the interrupt execution program, including:

[0021] According to the interrupt execution program, the interrupt number is converted into bitmap information;

[0022] The bitmap information is written into a preset event bitmap, an updated event bitmap is obtained, and an interrupt scheduler of the interrupt execution program is triggered.

[0023] Preferably, the interrupt scheduler parses the updated event bitmap, and obtains an IEC task ID corresponding to at least one parsed interrupt number in the updated event bitmap, including:

[0024] According to the interrupt scheduler, the updated event bitmap is parsed, and at least one parsed interrupt number in the updated event bitmap is obtained;

[0025] According to a preset interrupt number and IEC task mapping table, an IEC task ID corresponding to each parsed interrupt code is searched;

[0026] The updated event bitmap is emptied.

[0027] Preferably, the inserting each IEC task ID into the priority ready queue according to the priority of each IEC task ID comprises:

[0028] For each IEC task ID, determining the priority corresponding to the IEC task ID;

[0029] Comparing the priority of the IEC task ID with the priorities of other IEC task IDs in the priority ready queue;

[0030] According to the comparison result, inserting the IEC task ID into the priority ready queue.

[0031] Preferably, the performing task scheduling according to the priority ready queue to realize the real-time response and execution of the IEC task based on the hardware interrupt comprises:

[0032] Maintaining a plurality of priority ready queues, each priority ready queue corresponding to a task priority;

[0033] If the priority of the highest priority task in the plurality of priority ready queues is higher than the priority of the currently running task, triggering task preemption;

[0034] Performing context switching to schedule the highest priority task to run.

[0035] In a second aspect, an embodiment of the present application provides an IEC task scheduling device based on a hardware interrupt, comprising:

[0036] A response module, configured to determine an interrupt number corresponding to the interrupt flag bit and an interrupt execution program corresponding to the interrupt number in response to the interrupt flag bit set in the hardware peripheral device;

[0037] A writing module, configured to write the interrupt number into a preset event bitmap according to the interrupt execution program, to obtain an updated event bitmap and trigger an interrupt scheduler of the interrupt execution program;

[0038] An analysis module, configured to analyze the updated event bitmap according to the interrupt scheduler, to obtain an IEC task ID corresponding to at least one analysis interrupt number in the updated event bitmap;

[0039] A priority module, configured to insert each IEC task ID into a priority ready queue according to the priority of each IEC task ID;

[0040] A scheduling module, configured to perform task scheduling according to the priority ready queue to realize the real-time response and execution of the IEC task based on the hardware interrupt.

[0041] In a third aspect, an electronic device is provided, comprising at least one processor, at least one memory, and computer program instructions stored in the memory that, when executed by the processor, implement the method of the first aspect in the above-described embodiments.

[0042] In a fourth aspect, a storage medium is provided, having stored thereon computer program instructions that, when executed by a processor, implement the method of the first aspect in the above-described embodiments.

[0043] Compared with the prior art, the present application has the following advantages and beneficial effects:

[0044] By responding to the interrupt flag bit set in the hardware peripheral, determining the interrupt number corresponding to the interrupt flag bit, and the interrupt execution program corresponding to the interrupt number, the unified identification and fast service positioning of the hardware interrupt source are realized; according to the interrupt execution program, the interrupt number is written into the preset event bitmap, the updated event bitmap is obtained, and the interrupt scheduler of the interrupt execution program is triggered, the process decouples the key operation with extremely short time consumption and the complex data processing, reduces the execution time of the interrupt service program, and improves the response ability of the system to concurrent interrupts; according to the interrupt scheduler, the updated event bitmap is parsed to obtain the IEC task ID corresponding to at least one parsed interrupt number in the updated event bitmap, the translation from hardware events to software task requirements is completed, a loosely coupled event-task association mechanism is established, and the flexibility of system configuration is enhanced; according to the priority of each IEC task ID, each IEC task ID is inserted into the priority ready queue and the task scheduling is executed, and the real-time response and execution of the IEC task based on the hardware interrupt are realized. Through priority, the tasks are classified and organized, a set of tasks to be executed are constructed according to the degree of urgency, the preemptive scheduling of the tasks is realized, and the response delay of the system to high-priority external events is optimized. BRIEF DESCRIPTION OF DRAWINGS

[0045] In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be considered as a limitation to the scope. For those skilled in the art, other related drawings can also be obtained without creative labor. In the drawings:

[0046] Figure 1 A flowchart of the IEC task scheduling method based on hardware interrupt provided by the present embodiment is shown in the figure;

[0047] Figure 2 A flowchart of the example provided by the present embodiment is shown in the figure;

[0048] Figure 3 A structure schematic diagram of the IEC task scheduling device based on hardware interrupt provided in the embodiment is shown in the figure.

[0049] Figure 4 A structure schematic diagram of the electronic device provided in the embodiment is shown in the figure. DETAILED DESCRIPTION

[0050] In order to make the objects, technical solutions and advantages of the present application clearer, further detailed description will be given to the present application in combination with embodiments and drawings, and the illustrative embodiments of the present application and the description thereof are only used to explain the present application, and do not limit the present application.

[0051] It should be noted that, in this document, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitations, the elements defined by the statement "include" do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0052] It should be noted that all the actions of acquiring signals, information or data in the present application are performed under the premise of complying with the corresponding data protection regulations and policies of the place, and with the authorization given by the owner of the corresponding device.

[0053] Embodiment 1

[0054] Please refer to Figure 1 The embodiment of the present application provides an IEC task scheduling method based on hardware interrupt, which comprises the following steps.

[0055] S1, in response to the interrupt flag bit set in the hardware peripheral, determining the interrupt number corresponding to the interrupt flag bit and the interrupt execution program corresponding to the interrupt number;

[0056] The invention motive of this step is to establish the initial mapping from hardware interrupt events to specific software processing programs, laying the foundation for subsequent standardized processing. Interrupt flag bits are bit positions in the peripheral status register that represent the occurrence of a specific event, such as the setting of the receive interrupt flag bit of a universal asynchronous receiver transmitter when data reception is completed. In implementation, the central processing unit determines the unique interrupt number bound to the physical interrupt source by querying the interrupt vector table or directly according to the physical interrupt line number after detecting the interrupt request; then, the system indexes the corresponding interrupt execution program, i.e. the starting address of the interrupt service program, from the preset program entry address table according to the interrupt number. This process converts chaotic hardware signals into standardized software numbers and processing entries, achieving unified identification and rapid service positioning of hardware interrupt sources.

[0057] S2, writing the interrupt number into a preset event bitmap according to the interrupt execution program, obtaining an updated event bitmap and triggering an interrupt scheduler of the interrupt execution program;

[0058] The invention motive of this step is to record interrupt events with minimal overhead and separate the emergency part and the delayable part of interrupt processing, thereby reducing the blocking time of high-priority interrupts. The event bitmap is a global data structure composed of multiple bit positions, each of which corresponds to a logical interrupt number and is used to asynchronously record the occurrence of interrupt events. In implementation, the interrupt execution program sets the bit position corresponding to the interrupt number determined in step S1 to 1 through an atomic bit OR operation in its top-half phase, thereby generating an updated event bitmap; after completing the recording, the program triggers the interrupt scheduler responsible for subsequent processing by setting a software interrupt flag or releasing a semaphore. This process decouples time-consuming critical operations from complex data processing, reducing the execution time of the interrupt service program and improving the system's response capability to concurrent interrupts.

[0059] S3, parsing the updated event bitmap according to the interrupt scheduler to obtain an IEC task ID corresponding to at least one parsed interrupt number in the updated event bitmap;

[0060] The invention motive of this step is to convert the bottom layer interrupt event into the task trigger instruction of the upper layer programmable logic controller application layer, and realize the connection of hardware signal and software logic. The parsing interrupt number refers to the logical interrupt identification restored from the bit set in the event bitmap. In implementation, the interrupt scheduler reads the updated event bitmap, identifies the set bits one by one through bit scanning operation, and restores the position index of each bit to the corresponding parsing interrupt number; then, the scheduler queries the preconfigured interrupt-task mapping table with each parsing interrupt number as the key, and obtains the IEC task ID bound thereto. This process completes the translation from hardware event to software task requirement, establishes the loosely coupled event-task association mechanism, and enhances the flexibility of system configuration.

[0061] S4, inserting each IEC task ID into a priority ready queue according to the priority of each IEC task ID;

[0062] The invention motive of this step is to organize the execution order of tasks according to the importance of the tasks, provide structured input for subsequent scheduling decisions, and ensure that high criticality tasks are processed preferentially. The priority of the IEC task ID is a property statically assigned during the system design phase according to the real-time requirement and functional criticality of the task. In implementation, the scheduler retrieves the task control block corresponding to the IEC task ID according to the IEC task ID, and obtains the preset priority attribute thereof from the task control block; then, according to the priority value, the task control block is inserted into the tail of the queue corresponding to the priority level in the multi-level priority ready queue. This process classifies and organizes the tasks by priority, and constructs a set of tasks to be executed in order of urgency, providing a decision basis for preemptive scheduling.

[0063] S5, performing task scheduling according to the priority ready queue, to realize real-time response and execution of the IEC task based on hardware interrupt.

[0064] The invention motive of this step is to dynamically allocate processor resources to the most important task to be run at present, to meet the determinacy requirement of the programmable logic controller system on event response time. In implementation, the task scheduler continuously monitors the state of the priority ready queue, and the scheduling logic thereof is as follows: first, it is judged whether the priority of the highest priority task in the ready queue is higher than the priority of the task being run at present; if yes, the scheduler performs context switching, that is, saves the running site of the current task and restores the site of the highest priority ready task, so that the processor starts to execute the task; if no, the execution state of the current task is maintained. This process ensures that the processor always executes the highest priority task in the ready state, realizes preemptive scheduling of the task, and optimizes the response delay of the system to high-priority external events.

[0065] In some embodiments, S1, in response to an interrupt flag bit being set in a hardware peripheral, determines an interrupt number corresponding to the interrupt flag bit, and an interrupt execution procedure corresponding to the interrupt number, including:

[0066] S11, in response to an interrupt flag bit being set in a hardware peripheral, the hardware interrupt source corresponding to the hardware peripheral, the hardware interrupt source being at least one of an external digital input interrupt, a high-precision hardware timer interrupt, a pulse counting peripheral interrupt, and a communication receiving interrupt, pre-configured on a PLC hardware platform;

[0067] The invention motive of this step is to establish a deterministic hardware event response basis for a programmable logic controller, ensuring that the system can perceive and process asynchronous signals from critical external modules. The hardware interrupt source is a physical channel that can be independently configured on the internal or external interrupt controller of the processor, and its correspondence with specific hardware peripherals is fixed during the hardware design phase. For example, a specific external digital input pin is routed to a specific input line of the interrupt controller. When the system hardware circuit detects a peripheral event, such as a digital input level jump or a timer count value match, it automatically sets the interrupt flag bit of the peripheral. The flag state is then captured by the interrupt controller, which will send an interrupt request to the processor core if the interrupt source is enabled, triggering the interrupt response sequence. This process establishes a direct path from physical events to processor core responses, providing a low-latency hardware-level notification mechanism for system interaction with the external environment.

[0068] S12, according to the hardware interrupt source and a preset hardware interrupt and logical interrupt number mapping table, determining an interrupt number corresponding to the interrupt flag bit;

[0069] The invention motive of this step is to abstract the physical interrupt identification that depends on specific hardware implementation into a logical identification that is uniformly managed at the software level, thereby shielding hardware differences and improving software portability and configurability. The hardware interrupt and logical interrupt number mapping table is a configuration data structure loaded during system initialization, and its entries associate physical interrupt numbers with system-defined logical interrupt numbers. When implemented, the processor obtains the physical interrupt number representing the interrupt source from the interrupt controller after responding to the interrupt. The system software, typically the common entry part of the interrupt service routine, uses this physical interrupt number as an index to query the mapping table, thereby retrieving the corresponding logical interrupt number that is unique in the global scope of the system, i.e., the interrupt number. This process completes a hardware identification to software identification conversion, decouples the interrupt handling logic from the hardware physical layout, and makes the software architecture independent of specific hardware wiring or chip selection.

[0070] S13, determining an interrupt execution program corresponding to the interrupt number according to the interrupt number.

[0071] The invention motive of this step is to assign specific processing logic to each abstracted logical interrupt event, ensuring that different types of interrupts can be responded to quickly and specifically. The interrupt execution program refers to a software routine specially written for processing a specific logical interrupt, usually containing critical field operation and event recording code. In implementation, the system maintains an interrupt vector table or interrupt handler registration table, in which each logical interrupt number is associated with a pre-registered function entry pointer; after obtaining the interrupt number through step S12, the system uses this number as an index to query the table, and obtains the memory address of the specific interrupt execution program to be executed, and jumps to the address to start execution. This process realizes the dynamic linking of events and processors through table lookup, ensuring the correctness of interrupt response and providing a unified program entry point for subsequent top half and bottom half processing.

[0072] In some embodiments, S2, according to the interrupt execution program, writes the interrupt number into a preset event bitmap, obtains an updated event bitmap, and triggers an interrupt scheduler of the interrupt execution program, including:

[0073] S21, according to the interrupt execution program, storing the critical context in the hardware peripheral into the memory;

[0074] The invention motive of this step is to completely save the execution field of the interrupted task before executing the interrupt service logic, providing a data basis for correct recovery after subsequent possible task switching or interrupt return. The critical context refers to the register state in the processor core that changes dynamically during task execution, including program counter, status register, general register, and stack pointer, etc. necessary data to form the task execution field. In implementation, after obtaining control, the interrupt execution program first compresses the register content saved by hardware automatically into the current task stack or a specified memory area through software instructions, thereby solidifying and storing the running state of the current processor. This operation ensures that the execution state of the interrupted task is completely preserved, maintains the continuity of the task execution flow, and provides a prerequisite for preemptive scheduling and reliable interrupt nesting in a multi-task environment.

[0075] S22, according to the interrupt execution program, clearing the interrupt flag bit of the hardware peripheral;

[0076] The invention motive of this step is to inform the hardware that the interrupt request has been responded, so that it returns to the state of receiving new events again, preventing the repeated triggering or loss of interrupt signals due to the persistent validity of the flag bit. The interrupt flag bit is a specific bit in the peripheral status register, which is set by hardware when an event occurs, and usually needs to be cleared by software executing a specific write operation. In implementation, the interrupt execution program writes a preset clearing sequence, such as writing 1 to clear or writing 0 to clear, to the register address corresponding to the interrupt flag bit by accessing the register space of the peripheral, so as to reset the flag bit to the invalid state. This operation completes the confirmation of the hardware interrupt event, ensures the single nature of the interrupt trigger signal, avoids the same interrupt event being repeatedly responded by the processor, ensures the correctness of the interrupt processing logic and the stability of the system.

[0077] S23, according to the interrupt execution program, writes the interrupt number into a preset event bitmap to obtain an updated event bitmap and trigger an interrupt scheduler of the interrupt execution program.

[0078] The invention motive of this step is to record the occurrence of interrupt events with minimal software overhead, and to decouple the interrupt emergency processing and the subsequent scheduling logic, thereby shortening the interrupt closing time. The event bitmap is a global, multi-bit-wide shared variable, each bit of which corresponds to a logical interrupt number, used to asynchronously record the occurrence of interrupt events. In implementation, the interrupt execution program sets the bit position corresponding to the logical interrupt number of the current interrupt by a bit or operation instruction, thereby generating an updated event bitmap; then, the program activates an interrupt scheduler which is responsible for subsequent task scheduling function by setting a software interrupt flag or releasing a kernel semaphore. This process separates the time-consuming flag recording operation from the possibly complex task management logic, significantly reduces the execution time of the interrupt service program, reduces the response delay of the system to high-priority interrupts, and provides a clear event trigger source for the core scheduler.

[0079] In some embodiments, S23, according to the interrupt execution program, writes the interrupt number into a preset event bitmap to obtain an updated event bitmap and trigger an interrupt scheduler of the interrupt execution program, including:

[0080] According to the interrupt execution program, the interrupt number is converted into bitmap information;

[0081] The invention motive of this step is to convert the abstract logical interrupt identification into a data structure format suitable for fast and atomic update, and to establish a basis for recording events in shared resources. The bitmap information specifically refers to a bit mask in which only one bit is set, and its position has a direct mapping relationship with the logical interrupt number. In implementation, the interrupt execution program receives the logical interrupt number as input and generates bitmap information by performing a left bit shift operation. Specifically, an operand with a value of 1 is shifted to the left by the number of bits specified by the logical interrupt number, for example, when the logical interrupt number is 5, 1 is shifted to the left by 5 bits to generate the binary value 00100000 as bitmap information. This conversion process converts the interrupt number into a machine word that can be directly used for bit-level operations, preparing a uniform format and facilitating bit operation for event representation, and preparing data for subsequent safe modification of event bitmap.

[0082] Write the bitmap information into the preset event bitmap to obtain an updated event bitmap and trigger the interrupt dispatcher of the interrupt execution program.

[0083] The invention motive of this step is to record interrupt events in a thread-safe manner and notify the background scheduling process, thereby realizing the separation of responsibilities of the emergency part and the delayable part of interrupt processing. The event bitmap is a global variable declared as a volatile type, and its width is sufficient to cover all logical interrupt numbers in the system, which is used to pass event status between multiple interrupt sources and a single dispatcher. In implementation, the interrupt execution program merges the bitmap information with the current value of the event bitmap through an atomic operation instruction such as atomic bit or operation, thereby setting the bit position representing the new event and generating an updated event bitmap. This operation ensures that multiple event flags can be correctly accumulated without overlapping each other in a concurrent interrupt scenario. Subsequently, the program triggers the asynchronous execution of the interrupt dispatcher by sending a soft interrupt request or task signal to it. This process completes the persistence of event status with extremely low overhead and reduces the residence time of the interrupt service program in the critical section, and establishes an efficient and reliable event notification mechanism, providing a guarantee for the real-time response of the system.

[0084] In some embodiments, S3, according to the interrupt dispatcher, parses the updated event bitmap to obtain an IEC task ID corresponding to at least one parsed interrupt number in the updated event bitmap, including:

[0085] S31, according to the interrupt dispatcher, parses the updated event bitmap to obtain at least one parsed interrupt number in the updated event bitmap;

[0086] The invention motive of this step is to accurately separate each occurred interrupt event identification from the aggregated event record, to provide accurate input for the subsequent one-to-one task mapping. The resolution interrupt number refers to the logical interrupt code corresponding to the set bit identified by scanning the event bitmap. In implementation, the interrupt scheduler first reads and temporarily stores the current value of the updated event bitmap, and then scans the temporarily stored value bit by bit by combining the cyclic shift and the bit mask detection; for each bit whose value is 1, the corresponding resolution interrupt number is directly calculated according to its position index in the bitmap. This process realizes the expansion of the compressed bitmap information into a discrete event number sequence, completes the batch resolution and extraction of interrupt events, and provides the possibility for the system to handle multiple pending interrupt events at the same time.

[0087] S32, according to the preset interrupt number and IEC task mapping table, finding the IEC task ID corresponding to each resolution interrupt code;

[0088] The invention motive of this step is to establish the deterministic association between the underlying hardware interrupt event and the upper programmable logic controller application task, to drive the execution of specific business logic. The interrupt number and IEC task mapping table is a static configuration table defined by the user in the engineering configuration phase, which specifies which IEC task should be activated for a specific interrupt event. In implementation, the interrupt scheduler takes each resolution interrupt number obtained in step S31 as a query key to retrieve the mapping table, thereby obtaining the IEC task ID bound thereto. This table lookup operation completes the conversion from a general event to a specific application function, realizes decoupling and flexibility, so that the same hardware interrupt event can trigger different control logic in different application scenarios without modifying the core scheduling code.

[0089] S33, emptying the updated event bitmap.

[0090] The invention motive of this step is to reset the shared event record area, to prepare for receiving and recording the next batch of interrupt events, to prevent the flag bit of the processed event from interfering with the subsequent event, and to avoid repeated scheduling. In implementation, after completing the resolution and event processing of the current updated event bitmap, the interrupt scheduler clears the value of the global event bitmap variable through an atomic write memory operation. This operation must be performed after ensuring that all currently recorded events have been properly processed, so as to ensure that no event notification is lost. This emptying action marks the end of the current batch interrupt processing period, maintains the clean state of the event bitmap as a communication medium for cyclic use, and ensures the continuity and correctness of the interrupt event stream processing process.

[0091] In some embodiments, S4, according to the priority of each IEC task ID, inserts each IEC task ID into the priority ready queue, comprising:

[0092] S41, determine the priority corresponding to each IEC task ID;

[0093] The invention motivation of this step is to obtain the critical execution order attribute of each task to be scheduled, which is the basic prerequisite for making any priority-driven scheduling decision. The priority corresponding to the IEC task ID is an integer attribute value statically assigned according to the functional criticality, real-time requirement and system design constraints of the task at the time of task creation. In implementation, the interrupt scheduler indexes the IEC task ID, retrieves the task control block array of the system, and reads the preset priority field from the matching task control block data structure. This query operation maps the abstract task identifier to a numerical value that can be used for comparison and sorting, providing the scheduler with the core basis for judging the urgency of the task and deciding the execution order.

[0094] S42, compare the priority of the IEC task ID with the priorities of other IEC task IDs in the priority ready queue;

[0095] The invention motivation of this step is to dynamically evaluate the relative importance of the new ready task in the current set of tasks to be executed in the system to determine its appropriate insertion position. The priority ready queue is a typical multi-queue data structure, and different queues or different positions in the same queue represent the order of task execution. In implementation, the scheduler first locates the sub-queue corresponding to the priority of the new task, and then according to the adopted queue scheduling strategy, such as strict priority scheduling or priority combined with time slice rotation, compares the priority of the new task with the priorities of existing tasks in the sub-queue to determine its specific position in the queue, such as placing it at the end or sorting it according to a more fine-grained strategy. This comparison process realizes the dynamic sorting of tasks in the ready state, maintains the internal order of the ready queue, and ensures that the scheduler can quickly locate the highest priority task to be executed.

[0096] S43, insert the IEC task ID into the priority ready queue according to the comparison result.

[0097] The inventive motivation of this step is to formally incorporate the task into the task pool to be scheduled for execution according to the determined order based on the priority comparison, and complete the final conversion from the interrupt event to the executable state of the task. In implementation, the scheduler links the task control block corresponding to the current IEC task ID to the predetermined position of the sub-queue to which the priority belongs, for example, the tail of the first-in-first-out queue, or the position satisfying the sorting condition according to the comparison result of step S42. The insertion operation updates the content of the priority ready queue, so that the newly ready task can enter the sequence waiting for execution according to its priority attribute, providing an updated and structured input for the subsequent scheduler to select the highest priority task for execution.

[0098] In some embodiments, S5, performing task scheduling according to the priority ready queue, implements real-time response and execution of the IEC task based on hardware interrupt, including:

[0099] S51, maintaining a multi-level priority ready queue, each priority ready queue corresponding to a task priority;

[0100] The inventive motivation of this step is to construct a task execution set organization structure that can clearly reflect the urgency of the task, and provide data support for efficient and deterministic scheduling decisions. The multi-level priority ready queue is a data structure composed of multiple independent sub-queues, each sub-queue is assigned a unique priority identifier, and is used to accommodate all task control blocks in the ready state and having the specific priority. In implementation, a set of such sub-queues will be created during system initialization; when a task enters the ready state, its task control block is added to the tail of the corresponding priority sub-queue according to its static priority attribute. By grouping tasks according to their priorities, this organization allows the scheduler to quickly determine the next task to run by simply looking for the highest non-empty priority queue, optimizing the decision speed of the scheduler and ensuring that high-priority tasks are always discovered first.

[0101] S52, if the priority of the highest priority task in the multi-level priority ready queue is higher than the priority of the currently running task, triggering task preemption;

[0102] The invention motive of this step is to ensure that the processor resource can be immediately allocated to the newly emerging more urgent task, so as to meet the strict real-time response requirement of the system to the high-priority event. Task preemption refers to the process of forcibly interrupting the currently running low-priority task and transferring the processor control right to a higher-priority ready task. When implemented, the scheduler performs a preemption check at a specific event point, such as after a task is inserted into the ready queue or when the running task actively releases the processor: it first determines the highest priority in all non-empty queues in the multi-level priority ready queue, and then compares this highest priority with the priority value recorded in the current running task control block; if the former is greater than the latter, a preemption request is generated. This decision logic realizes dynamic evaluation of the system execution state, establishes a priority-based resource preemption mechanism, and effectively reduces the scheduling delay of high-priority tasks.

[0103] S53, perform context switching and schedule the highest-priority task to run.

[0104] The invention motive of this step is to actually complete the transfer of processor execution flow and convert the scheduling decision into specific task execution, while ensuring that the interrupted task can be seamlessly restored subsequently. Context switching is the process of saving the running environment of the current task and restoring the previously saved running environment of another task, and its core is the saving and loading of the processor register set. When implemented, first, the program counter, stack pointer, general registers, and other key contexts of the currently running task are saved to its task control block; then, the control block of the target task is taken out from the head of the highest-priority ready queue, and the context information saved in it is loaded into the corresponding registers of the processor, including restoring its program counter, thereby guiding the processor to start executing the code of the highest-priority task. This operation is the final physical implementation of task scheduling, which realizes the time-sharing concurrent execution of multiple tasks on a single processor and ensures the integrity and continuity of the task execution state.

[0105] The embodiment will be described below through specific examples, as shown in Figure 2 The hardware platform includes:

[0106] CPU: ARM Cortex-M series or industrial real-time microprocessor;

[0107] Peripheral: GPIO interrupt, general timer, PWM / pulse counter, UART / ETH receive interrupt, etc.

[0108] Software architecture (layered):

[0109] Hardware interrupt source layer: each peripheral generates an interrupt, and a hardware interrupt number mapping table associates the physical interrupt with the logical interrupt number; the interrupt source configuration completes the mapping of the physical interrupt and the logical interrupt.

[0110] Top half ISR: Each interrupt vector corresponds to a small interrupt execution procedure (ISR), which executes:

[0111] Read the interrupt status register and clear the interrupt;

[0112] Write event flags into a volatile uint32_t event_bitmap or lockfree queue;

[0113] If the bottom half needs to be triggered, generate a soft interrupt / signal;

[0114] Return as quickly as possible;

[0115] Interrupt bottom half / Interrupt dispatcher (runs in kernel context or high priority thread):

[0116] Read the event_bitmap and resolve events one by one;

[0117] Find the corresponding IEC task ID according to the event and the mapping table;

[0118] Insert the task into the priority ready queue; if the task priority is higher than the currently running task, trigger context switching;

[0119] IEC task management module (high-level task scheduling):

[0120] Maintain the task control block (TCB), recording priority, type (periodic / event), WCET, periodic / trigger source, resource lock information, etc.

[0121] Execute task scheduling decisions and state transitions;

[0122] Resource management and protection:

[0123] Protect shared data structures with fine-grained mutual exclusion (such as interrupt-safe spinlocks or short interrupt-disabled critical sections);

[0124] Enable priority inheritance when needed to avoid inversion.

[0125] Key data structure example (pseudo code)

[0126] typedef struct {

[0127] uint16_t task_id;

[0128] uint8_t priority;

[0129] uint8_t type; / / 0=periodic,1=event

[0130] uint32_t wcet_us;

[0131] uint32_t period_us;

[0132] uint32_t bound_deadline; / / optional

[0133] } IEC_TaskControlBlock;

[0134] volatile uint32_t event_bitmap; / / Bit map, each bit corresponds to one interrupt event

[0135] Queue ready_queues[MAX_PRIORITY];

[0136] Scheduling process

[0137] Hardware interrupt triggered -> ISR sets event_bitmap and triggers software interrupt;

[0138] The bottom half of the interrupt is read from the event_bitmap, bits are cleared, and the corresponding task is found bit by bit.

[0139] Insert the corresponding task TCB into the ready_queue of the corresponding priority;

[0140] If the highest priority task in the ready_queue has a higher priority than the currently running task, a context switch is performed, and the task execution begins.

[0141] After a task is completed or preempted, the execution time will be written back to the monitoring module. If the execution time exceeds WCET, an anomaly will be recorded and protection measures may be triggered.

[0142] In scenarios involving time-sensitive communications (such as TSN and PROFINET IRT), communication reception events can be mapped to high-priority events, and hardware timestamps can be used to assist in deterministic scheduling. It also supports phase alignment between periodic tasks and communication cycles to reduce jitter.

[0143] To prevent the top half of the ISR from becoming too long and causing system unresponsiveness, the maximum execution time of the ISR is limited, and complex processing is forced to be moved to the bottom half. Short-term interrupt protection is used for shared resources, combined with priority inheritance protocols, or hardware mutual exclusion (such as dedicated mutual exclusion peripherals) is used to reduce waiting time.

[0144] Example 2

[0145] Please see Figure 3The embodiment of the present application provides an IEC task scheduling device based on a hardware interrupt, comprising:

[0146] A response module 301 is configured to determine an interrupt number corresponding to an interrupt flag bit set in a hardware peripheral and an interrupt execution program corresponding to the interrupt number in response to the interrupt flag bit.

[0147] A writing module 302 is configured to write the interrupt number into a preset event bitmap according to the interrupt execution program, obtain an updated event bitmap and trigger an interrupt scheduler of the interrupt execution program.

[0148] An analysis module 303 is configured to analyze the updated event bitmap according to the interrupt scheduler, and obtain an IEC task ID corresponding to at least one analysis interrupt number in the updated event bitmap.

[0149] A priority module 304 is configured to insert each IEC task ID into a priority ready queue according to a priority of each IEC task ID.

[0150] A scheduling module 305 is configured to perform task scheduling according to the priority ready queue, and realize real-time response and execution of the IEC task based on the hardware interrupt.

[0151] It should be noted that the modules and units in the IEC task scheduling device based on the hardware interrupt in the embodiment correspond to the steps in the IEC task scheduling method based on the hardware interrupt in the foregoing embodiment one by one, and therefore, the specific implementation of the embodiment can refer to the implementation of the foregoing IEC task scheduling method based on the hardware interrupt, which will not be described here again.

[0152] Embodiment 3

[0153] Please refer to Figure 4 The embodiment provides an electronic device, comprising at least one processor 401 and a memory 402. Optionally, the device further comprises a communication component 403. Wherein, the processor 401, the memory 402 and the communication component 403 are connected through a bus 404.

[0154] In the specific implementation process, the at least one processor 401 executes the computer execution instruction stored in the memory 402, so that the at least one processor 401 executes the method described above.

[0155] The specific implementation process of the processor 401 can refer to the method embodiment described above, which has similar implementation principles and technical effects, and will not be described here again.

[0156] In the above embodiments, it should be understood that the processor can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), etc. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor. The steps of the method disclosed in combination with the application can be directly embodied as hardware processor execution, or executed by a combination of hardware and software modules in the processor.

[0157] The memory can include a random access memory (RAM), and can also include a non-volatile memory (NVM), such as at least one disk memory.

[0158] The bus can be an industry standard architecture (ISA) bus, a peripheral component (PCI) bus, or an extended industry standard architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, the bus in the drawings of the present application does not limit to only one bus or one type of bus.

[0159] The present application also provides a computer program product, comprising a computer program, which, when executed by a processor, implements the above method.

[0160] The present application also provides a computer readable storage medium, which stores computer execution instructions, and when a processor executes the computer execution instructions, the above method is implemented.

[0161] The above readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. The readable storage medium can be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0162] An example readable storage medium is coupled to the processor such that the processor can read information from the readable storage medium and can write information to the readable storage medium. Of course, the readable storage medium can also be a part of the processor. The processor and the readable storage medium can be located in an application specific integrated circuit (ASIC). Of course, the processor and the readable storage medium can also exist as discrete components in the device.

[0163] The division of units is only a logical functional division, and in actual implementation, there can be another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interfaces, devices or units, and can be electrical, mechanical or other forms.

[0164] The units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, that is, can be located in one place, or can be distributed on a plurality of network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment scheme.

[0165] In addition, the functional units in each embodiment of the present application can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit.

[0166] If the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application or the part of the present application that essentially contributes to the prior art or the part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method of each embodiment of the present application. The foregoing storage medium includes a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various program code storage media.

[0167] Those skilled in the art can understand that all or part of the steps of the above-mentioned method embodiments can be completed by program instruction related hardware. The foregoing program can be stored in a computer readable storage medium. The program executes to perform the steps of the above-mentioned method embodiments; and the foregoing storage medium includes various storage media that can store program codes, such as ROM, RAM, magnetic disk or optical disk.

[0168] The above detailed description further describes the purpose, technical solutions and beneficial effects of the present application. It should be understood that the above description is only a specific embodiment of the present application and is not used to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A hardware interrupt-based IEC task scheduling method, characterized in that, The method comprises the following steps: in response to the interrupt flag bit set in the hardware peripheral, determining the interrupt number corresponding to the interrupt flag bit and the interrupt execution program corresponding to the interrupt number; writing the interrupt number into a preset event bitmap according to the interrupt execution program to obtain an updated event bitmap and trigger an interrupt scheduler of the interrupt execution program; parsing the updated event bitmap according to the interrupt scheduler to obtain an IEC task ID corresponding to at least one parsed interrupt number in the updated event bitmap; inserting each IEC task ID into a priority ready queue according to the priority of each IEC task ID; performing task scheduling according to the priority ready queue to realize real-time response and execution of the IEC task based on the hardware interrupt.

2. The method of claim 1, wherein, The method comprises the following steps: in response to the interrupt flag bit set in the hardware peripheral, determining the interrupt number corresponding to the interrupt flag bit and the interrupt execution program corresponding to the interrupt number; according to a preset hardware interrupt source, the hardware interrupt source corresponds to the hardware peripheral, and the hardware interrupt source is at least one of an external digital input interrupt, a high-precision hardware timer interrupt, a pulse counting peripheral interrupt and a communication receiving interrupt pre-configured on a PLC hardware platform; determining the interrupt number corresponding to the interrupt flag bit according to the hardware interrupt source and a preset hardware interrupt and logical interrupt number mapping table; 3. The method of claim 1, wherein, determining the interrupt execution program corresponding to the interrupt number according to the interrupt number. The method comprises the following steps: storing the key context of the hardware peripheral into the memory according to the interrupt execution program; clearing the interrupt flag bit of the hardware peripheral according to the interrupt execution program; 4. The method of claim 3, wherein, writing the interrupt number into a preset event bitmap according to the interrupt execution program to obtain an updated event bitmap and trigger an interrupt scheduler of the interrupt execution program. The method comprises the following steps: converting the interrupt number into bitmap information according to the interrupt execution program; 5. The method of claim 1, wherein, writing the bitmap information into a preset event bitmap to obtain an updated event bitmap and trigger an interrupt scheduler of the interrupt execution program. The method comprises the following steps: parsing the updated event bitmap according to the interrupt scheduler to obtain at least one parsed interrupt number in the updated event bitmap; according to a preset interrupt number and IEC task mapping table, finding the IEC task ID corresponding to each parsed interrupt code; 6. The method of claim 1, wherein, emptying the updated event bitmap. The method comprises the following steps: For each IEC task ID, determine the priority corresponding to the IEC task ID; Compare the priority of the IEC task ID with the priorities of other IEC task IDs in the priority ready queue; Insert the IEC task ID into the priority ready queue according to the comparison result.

7. The method of claim 1, wherein, The task scheduling is performed according to the priority ready queue, and the IEC task is responded and executed in real time based on the hardware interrupt, including: Maintain a plurality of priority ready queues, each priority ready queue corresponding to a task priority; If the priority of the highest priority task in the plurality of priority ready queues is higher than the priority of the currently running task, trigger task preemption; Perform context switching and schedule the highest priority task to run.

8. A hardware interrupt-based IEC task scheduling apparatus, characterized by comprising: It includes: A response module for determining the interrupt number corresponding to the interrupt flag bit set in the hardware peripheral and the interrupt execution program corresponding to the interrupt number in response to the interrupt flag bit set in the hardware peripheral; A writing module for writing the interrupt number into a preset event bitmap according to the interrupt execution program, obtaining an updated event bitmap and triggering an interrupt scheduler of the interrupt execution program; An analysis module for analyzing the updated event bitmap according to the interrupt scheduler to obtain the IEC task ID corresponding to at least one analysis interrupt number in the updated event bitmap; A priority module for inserting each IEC task ID into a priority ready queue according to the priority of each IEC task ID; A scheduling module for performing task scheduling according to the priority ready queue to realize real-time response and execution of the IEC task based on the hardware interrupt.

9. An electronic device, comprising: It includes: To a processor, at least one memory and computer program instructions stored in the memory, when the computer program instructions are executed by the processor, the method as claimed in any one of claims 1-7 is realized.

10. A computer-readable storage medium having stored thereon computer program instructions, wherein, When the computer program instructions are executed by the processor, the method as claimed in any one of claims 1-7 is realized.

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