Main control board programming detection method and device

Abstract

The invention relates to the field of detection, in particular to a main control board programming detection method and device.The method comprises the steps that after a main chip is selected, an initial task is issued to the main chip, so that the main chip generates output data, then entanglement tasks of other auxiliary chips can be constructed according to the output data, the entanglement tasks are issued to all the chips, and the main control board programming detection is completed. The chips are entangled, so that the time sequence entanglement degree when the chips execute tasks can be monitored; after each chip executes a round of task, the main chip can be replaced, so that the master-slave relationship of each chip is changed, new entangled data is constructed according to output data of the main chip, the entangled data is issued again, each chip executes the entangled data, and the time sequence entanglement condition of each chip under the switching of various master-slave relationships can be realized by repeating the steps. Therefore, the overall collaboration of the chips is determined, the overall performance of the mainboard after programming can be accurately judged, and whether programming is qualified or not is determined.

Description

Technical Field

[0001] This invention relates to the field of testing, and in particular to a method and apparatus for testing the programming of a main control board. Background Technology

[0002] With the rapid development of artificial intelligence and industrial control technology, single chips can no longer meet the comprehensive requirements of complex tasks for computing performance, control precision and flexible configuration. Therefore, multi-chip architecture motherboards have emerged.

[0003] In existing technologies, the functional testing of multi-chip motherboards generally adopts a "single-chip independent verification + simple board-wide integration testing" model. The core logic is: if the functional test of each chip is qualified, the overall board's collaborative function is considered normal. Specifically, after programming, independent test tasks are sent to the three chips using testing tools to verify the single chip's computational accuracy, interface response speed, and other indicators. Then, a simple data stream transmission test verifies the basic connectivity of the entire board, thus completing the testing process. However, existing solutions do not consider potential deviations that may occur during the three-chip collaboration process. For example, even if a single chip's function is fully qualified, due to minute clock drifts (e.g., on the order of 1 ppm) in the clock sources of each chip, or "chaotic sensitive points" such as frame rate matching in the communication protocol, these minute timing differences can be continuously amplified when collaboratively processing dynamic load tasks, ultimately leading to severe collaborative synchronization failures. Summary of the Invention

[0004] Therefore, it is necessary to provide a main control board programming detection method to address the above problems. The method includes: S1: After the chips on the motherboard have been programmed, select one chip as the main chip and the others as secondary chips. S2: Send a preset initial task signal to the main chip to enable the main chip to execute the initial task; S3: Monitor the output data of the main chip, determine the entanglement task of the sub-chip based on the output data of the main chip, send the entanglement task signal to the sub-chip, so that the sub-chip can execute the entanglement task, monitor and store the timing characteristics of the execution task. Among them, the execution of the entanglement task by one chip requires the output data of other chips to trigger it. S4: Switch another chip to be the master chip, and the remaining chips to be slave chips. Repeat steps S3 to S4 to complete the detection of each chip under all master-slave relationships. S5: After each chip completes its task, retrieve the task sequence completed by each chip, and determine the temporal entanglement degree of each chip when performing the entanglement task based on each task sequence and the stored temporal characteristics. S6: Determine the overall coordination degree of each chip based on the entanglement degree of each timing sequence, thereby judging whether the motherboard programming is qualified.

[0005] In one embodiment, the present invention provides a main control board programming detection device, wherein a module in the main control board programming detection device is used to execute the main control board programming detection method, specifically including: The first processing module is used to select one chip as the main chip and the other chips as auxiliary chips after the chips on the motherboard have been programmed. The second processing module is used to send a preset initial task signal to the main chip, so that the main chip can execute the initial task. The third processing module is used to monitor the output data of the main chip, determine the entanglement task of the sub-chip based on the output data of the main chip, send the entanglement task signal to the sub-chip, so that the sub-chip can execute the entanglement task, monitor and store the timing characteristics of the execution task. Among them, the execution of the entanglement task by one chip requires the output data of other chips to trigger it. The switching module is used to switch another chip to be the main chip and the remaining chips to be the secondary chips. Steps S3 to S4 are executed repeatedly to complete the detection of each chip under all the main and secondary relationships. The fourth processing module is used to retrieve the task sequence completed by each chip after each chip completes its task, and determine the temporal entanglement degree of each chip when performing the entanglement task based on each task sequence and the stored temporal characteristics. The judgment module is used to determine the overall coordination degree of each chip based on the entanglement degree of each timing sequence, thereby determining whether the motherboard programming is qualified.

[0006] This invention provides a method for detecting the programming of a main control board, comprising: after programming of all chips on the motherboard, selecting one chip as the main chip and the others as slave chips; sending a preset initial task signal to the main chip to enable it to execute the initial task; monitoring the output data of the main chip, determining the entanglement task of the slave chips based on the output data, sending the entanglement task signal to the slave chips to enable them to execute the entanglement task, and monitoring and storing the timing characteristics of the executed task; switching another chip to be the main chip and the remaining chips to be slave chips, and repeatedly executing steps S3 to S4 to complete the detection of each chip under all master-slave relationships; after each chip completes its task, retrieving the task sequence completed by each chip, determining the temporal entanglement degree of each chip when executing the entanglement task based on each task sequence and the stored timing characteristics; and determining the temporal entanglement degree based on the temporal entanglement degree. The overall coordination level of each chip is determined to assess whether the motherboard programming is successful. In this application, after selecting the master chip, an initial task is sent to the master chip to generate output data. Based on the output data, entanglement tasks for other slave chips can be constructed and sent to each chip to perform entanglement. This allows monitoring of the timing entanglement degree of each chip during task execution. After each chip completes one round of tasks, the master chip can be replaced, thereby changing the master-slave relationship among the chips. New entanglement data is then constructed based on the output data of the master chip, and entanglement data is sent to each chip again for execution. This cycle is repeated to realize the timing entanglement of each chip under various master-slave relationship switching, thereby determining the overall coordination of each chip and accurately judging the overall performance of the motherboard after programming to determine whether the programming is successful. Attached Figure Description

[0007] Figure 1 A flowchart of a main control board programming and detection method provided in one embodiment; Figure 2 This is an application environment diagram of the main control board programming detection method in one embodiment; Figure 3 This is a timeline diagram of the main control board programming detection method in one embodiment; Figure 4 Here is a flowchart of the main control board programming and detection device in one embodiment. Figure 5 This is a block diagram of the internal structure of a computer device in one embodiment. Detailed Implementation

[0008] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0009] It is understood that the terms 'first,' 'second,' etc., used in this invention may be used to describe various elements, but unless specifically stated otherwise, these elements are not limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this invention, a first script may be referred to as a second script, and similarly, a second script may be referred to as a first script.

[0010] like Figure 1 As shown, in one embodiment, a method for detecting the programming of a main control board is proposed, the method comprising: S1: After the chips on the motherboard have been programmed, select one chip as the main chip and the others as secondary chips. S2: Send a preset initial task signal to the main chip to enable the main chip to execute the initial task; S3: Monitor the output data of the main chip, determine the entanglement task of the sub-chip based on the output data of the main chip, send the entanglement task signal to the sub-chip, so that the sub-chip can execute the entanglement task, monitor and store the timing characteristics of the execution task. Among them, the execution of the entanglement task by one chip requires the output data of other chips to trigger it. S4: Switch another chip to be the master chip, and the remaining chips to be slave chips. Repeat steps S3 to S4 to complete the detection of each chip under all master-slave relationships. S5: After each chip completes its task, retrieve the task sequence completed by each chip, and determine the temporal entanglement degree of each chip when performing the entanglement task based on each task sequence and the stored temporal characteristics. S6: Determine the overall coordination degree of each chip based on the entanglement degree of each timing sequence, thereby judging whether the motherboard programming is qualified.

[0011] In this embodiment, as Figure 2 As shown, this method is executed in a computer device, which can be an independent physical server or terminal, or a server cluster consisting of multiple physical servers, or a cloud server that provides basic cloud computing services such as cloud servers, cloud databases, cloud storage, and CDN. The computer device communicates with the various chips on the motherboard. After the chips on the motherboard are programmed, it can send tasks to each chip and monitor the execution data of each chip to determine whether the motherboard programming is successful.

[0012] In this embodiment, there may be three or more chips on the motherboard, and each chip may be the same chip, different chips, or only some chips may be the same. There is no limitation here, and the user can select according to actual needs. In this embodiment, an entanglement task is a task that requires the output data generated by other chips after they have executed corresponding tasks to trigger it. That is, the execution of an entanglement task by one chip has entanglement with other chips (i.e., the execution timing of the entanglement task by one chip is related to the previous chip, and the degree of following is characterized by the timing deviation, which can be characterized by the timing entanglement degree). In this embodiment, the computer device has a preset lower limit value for the overall coordination level. After the overall coordination level is finally calculated, it is compared with the lower limit value. If it exceeds the lower limit value, the motherboard can be determined to be successfully programmed; otherwise, the motherboard programming is unsuccessful. In this application, after selecting the master chip, an initial task is sent to the master chip to generate output data. Based on the output data, entanglement tasks for other slave chips can be constructed and sent to each chip to perform entanglement. This allows for monitoring the temporal entanglement degree of each chip when executing tasks. After each chip completes a round of tasks, the master chip can be replaced, thereby changing the master-slave relationship of each chip. New entanglement data is then constructed based on the output data of the master chip, and entanglement data is sent to each chip again for execution. This process is repeated to realize the temporal entanglement of each chip under various master-slave relationship switching, thereby determining the overall coordination of each chip. This allows for accurate judgment of the overall performance of the motherboard after programming, thus determining whether the programming is qualified.

[0013] In a preferred embodiment, determining the entanglement task of the secondary chip based on the output data of the main chip includes: S31: Determine all data transmission paths for the main chip and the sub-chips, wherein the data transmission paths connect the main chip to each sub-chip, and the main chip is located at the first node of each data transmission path; S32: Select a data transmission path; S33: Determine the order of each sub-chip based on the position of each sub-chip in the data transmission path; S34: For each chip, determine the entanglement task of the chip based on the output data of the previous chip and the data dependency rules; S35: Repeat steps S32 to S34 until the entanglement task of each sub-chip under each data transmission path is determined, and the correspondence between the sub-chip and the entanglement task under each data transmission path is obtained.

[0014] In this embodiment, determining the complete data transmission path starting from the main chip and including all chips essentially involves solving a Hamiltonian path problem with a fixed starting point (each node is visited only once, covering all nodes). This requires combining the physical connection topology between chips with algorithm enumeration. The specific method for determining this path is as follows: Backtracking method to enumerate all valid paths: Phase 1: Initialization State 1. Create a 'Current Path Record Sheet': Initially, only the starting node (node ​​z) is filled in, indicating that the path starts from the main chip; Establish a 'node access tag list': initially only 'node z has been visited' is marked, and all other nodes are marked 'not visited'; Create a 'Summary List of Valid Paths': initially empty, used to store the complete paths that ultimately meet all constraints.

[0015] Phase 2: Probe the next node layer by layer (recursive core) 1. Using the last node of the 'Current Path Record' as the 'Current Node', perform the following operations: 2. Traverse all nodes marked as 'unvisited' as 'candidate next hop nodes'; 3. Verify candidate nodes: Only retain nodes whose 'current node → candidate next hop node' exists in the unidirectional connectivity list; For each eligible candidate node, execute: Mark the candidate node as 'visited'; Add the candidate node to the end of the 'Current Path Record List'; Check path integrity: If the 'Current Path Record' already contains all m+1 nodes (main chip + all sub-chips, the number of sub-chips is m), then copy the complete path to the 'Valid Path Summary List'; If the path is incomplete (there are still unvisited nodes), then take the candidate node as the new 'current node' and repeat steps 1-3 of this stage to continue exploring the next level of nodes; Backtracking operation: After completing all lower-level explorations of the current candidate node, remove the node from the 'Current Path Record List' and mark it back to 'Unvisited', then return to the previous level to continue exploring other candidate nodes.

[0016] Phase 3: Terminating the trial Once all candidate next-hop nodes of the starting node have completed the 'probe-backtrack' process, all operations are stopped. At this point, the 'effective path summary list' has recorded all transmission paths that meet the constraints.

[0017] In this embodiment, the correspondence between the sub-chip and the entanglement task under each data transmission path represents the entanglement task corresponding to each sub-chip in each data transmission path. As a preferred embodiment, the types of data dependencies include: Startup dependency, that is, the entanglement task startup data must be triggered by the output data of the previous chip; The processing dependency means that the processing data for the entangled task must come directly from the output data of the previous chip; Before executing step S34, the process also includes: splitting each task in the task library into several subtasks to obtain a set of subtasks, wherein each subtask is triggered by specific data received by the chip, and after the subtask is executed, it generates output data and is output by the chip to another chip.

[0018] Based on the output data of the preceding chip and the data dependency rules, the entanglement task of this secondary chip is determined to include: Determine the data type of the output data from the previous chip as the target type; From the set of subtasks, identify all subtasks that need to be triggered by data belonging to the target type, and obtain the first set of subtasks; From the set of subtasks, identify all subtasks that use data of the target type as the data to be processed, and obtain the second set of subtasks; Determine the intersection of the first task set and the second task set, and select a subtask from the intersection as the entanglement task of the sub-chip.

[0019] In this embodiment, all tasks in the task library are serial tasks, each consisting of several subtasks. Each subtask needs to be assigned to a specific chip (one-to-one) for execution. Starting from the second subtask, each subtask can only be triggered upon receiving the output data of the previous subtask. For example, a serial task for industrial product visual sorting includes four subtasks: image acquisition and processing (subtask A), weight detection (subtask B), material recognition (subtask C), and sorting execution control (subtask D). The triggering relationship between these subtasks is as follows: Subtask A: Action performed: Acquire product appearance images using an industrial camera, and perform image noise reduction and edge extraction; Output data: Product dimensions + appearance defect markings; Subtask B: Triggering condition: The chip that receives the defect-free appearance flag output by executing subtask A; Actions performed: Based on the "no defects" mark, determine that the appearance is qualified, control the weighing sensor to collect the product weight, and compare it with the standard weight threshold; Output data: Actual product weight + weight compliance mark; Subtask C: Triggering condition: Receive the weight qualification flag output by the chip executing subtask B; Actions performed: Determine if the weight is within acceptable limits based on the weight qualification mark, and control the infrared spectroscopy sensor to analyze the material composition of the product; Output data: Product material type (metal / plastic / glass) + material matching indicator; Subtask D: Triggering condition: Receive material type data output by the chip executing subtask C; Action execution: Generate sorting robot movement instructions based on material type; Output data: Robotic arm drive commands + sorting completion status feedback; In this embodiment, the above-mentioned serial task can be represented as 'ABC-D', which divides each task in the task library into several sub-tasks, that is, it divides each serial task into, for example, 'ABC-D' into four sub-tasks 'A', 'B', 'C', and 'D'. In this embodiment, determining the entanglement task of each chip in a data transmission path is equivalent to recombining and concatenating the subtasks to obtain a new concatenated task that the data transmission path can complete (which must meet both the requirement of the number of nodes and the requirement of the output data generated by the first node executing the initial task). The reason for splitting the concatenated data is that the original concatenated task may not match the data transmission path. After splitting the original concatenated task, the subtasks can be recombined to create new concatenated tasks, increasing the possibility of matching the data transmission path. For example, the two subtasks 'EF-G' and 'TF-Q' can be split into five subtasks 'E', 'T', 'F', 'G', and 'Q', which can then be recombined into concatenated tasks such as 'EF-Q' and 'TF-G' that did not exist originally.

[0020] In a preferred embodiment, sending the entanglement task signal to the secondary chip, causing the secondary chip to perform the entanglement task, includes: S301: Select a data transmission path; S302: Retrieve the correspondence between the sub-chip and the entanglement task under this data transmission path; S303: Based on the correspondence of entanglement tasks, the determined entanglement tasks are sent to the corresponding sub-chips; S304: Instruct the main chip to re-execute the initial task, so as to trigger each sub-chip to execute the corresponding entanglement task; S305: After the last chip in the data transmission path completes the corresponding entanglement task, another data transmission path is taken, and steps S302 to S303 are executed until the simulation of each sub-chip performing the entanglement task under each data transmission path is completed. Monitoring and storing the temporal characteristics of the executed tasks includes: Monitor the start time of each chip's task execution and the time when output data is generated after the task is executed; Store all monitored moments.

[0021] In this embodiment, the correspondence between the secondary chips and entanglement tasks under a data transmission path is defined as the entanglement task corresponding to each secondary chip under that data transmission path. For each data transmission path, an initial task needs to be sent to the main chip twice. After the first initial task is sent, the main chip generates output data, and then determines a series of entanglement tasks corresponding to subsequent chips based on the output data, thereby determining the correspondence between the secondary chips and entanglement tasks under that data transmission path. Then, the output data is deleted. At this time, since the secondary chips have not yet been assigned entanglement tasks, there will be no response. Next, each entanglement task is sent to the corresponding secondary chip. Since there is no data trigger, the secondary chips also do not respond temporarily. After the same initial task is sent to the main chip for the second time, each entanglement task is executed by the corresponding secondary chip under the trigger of the output data generated by the main chip, thereby enabling the monitoring and storage of the timing characteristics of the executed tasks.

[0022] like Figure 3 As shown, in a preferred embodiment, determining the temporal entanglement degree of each chip when performing the entanglement task based on each task sequence and the stored timing characteristics includes: For each data transmission path, the tasks executed by each sub-chip under that data transmission path are screened out from each task sequence; Assign corresponding temporal features to each selected task; Generate a timeline and mark the time period of each screened task on the timeline according to the corresponding time series characteristics. The time period is the segment on the timeline from the start time of the task to the time when the output data is generated. The temporal entanglement degree of each sub-chip executing tasks under the data transmission path is calculated based on the location of each time period.

[0023] The temporal entanglement degree of each sub-chip executing its task along the data transmission path is calculated based on its position in each time period, including: If the number of time segments on the timeline is determined to be n, then the number of time segment intervals is n-1. The temporal matching degree for each time interval is calculated using the following formula: in, Let be the temporal matching degree corresponding to the i-th time interval. This is the time difference between the end time of the time interval preceding the i-th time interval and the beginning time of the time interval preceding the i-th time interval. The preset standard time difference; The temporal entanglement degree of each sub-chip executing its task along this data transmission path is calculated using the following formula: in, For temporal entanglement degree, The data volume coefficient is calculated using the following formula: in, The standard data volume for output data. This represents the amount of output data of the chip when performing the corresponding task during the time period preceding the i-th time interval.

[0024] in, To improve the overall level of coordination, To obtain the j-th temporal entanglement degree, m is the number of temporal entanglement degrees.

[0025] In this embodiment, the preset standard time difference can be 5ms. The standard time deviation is the standard time interval that characterizes the chip's response speed. The closer the actual monitored time difference is to the standard time deviation, the higher the corresponding timing matching degree, which can reflect that the chip has good entanglement with the previous chip; and the timing entanglement degree This can demonstrate the entanglement of chips along a data transmission path. A high degree of temporal entanglement across all data transmission paths indicates that each chip exhibits high entanglement under various master-slave relationships and connection methods, resulting in a higher degree of overall coordination among them. Furthermore, considering the different data volumes of output data from different subtasks, this embodiment introduces a data volume coefficient to further improve computational accuracy. The standard data volume in the data volume coefficient is a preset data volume, such as 32 bytes.

[0026] like Figure 4 As shown, in one embodiment, a main control board programming detection device is proposed. A module in the main control board programming detection device is used to execute the main control board programming detection method, specifically including: The first processing module is used to select one chip as the main chip and the other chips as auxiliary chips after the chips on the motherboard have been programmed. The second processing module is used to send a preset initial task signal to the main chip, so that the main chip can execute the initial task. The third processing module is used to monitor the output data of the main chip, determine the entanglement task of the sub-chip based on the output data of the main chip, send the entanglement task signal to the sub-chip, so that the sub-chip can execute the entanglement task, monitor and store the timing characteristics of the execution task. Among them, the execution of the entanglement task by one chip requires the output data of other chips to trigger it. The switching module is used to switch another chip to be the main chip and the remaining chips to be the secondary chips. Steps S3 to S4 are executed repeatedly to complete the detection of each chip under all the main and secondary relationships. The fourth processing module is used to retrieve the task sequence completed by each chip after each chip completes its task, and determine the temporal entanglement degree of each chip when performing the entanglement task based on each task sequence and the stored temporal characteristics. The judgment module is used to determine the overall coordination degree of each chip based on the entanglement degree of each timing sequence, thereby determining whether the motherboard programming is qualified.

[0027] The process by which each module in the main control board programming and testing device provided in this application implements its respective function can be found in the foregoing. Figure 1 The description of the illustrated embodiment will not be repeated here.

[0028] Figure 5 An internal structural diagram of a computer device in one embodiment is shown. Figure 5 As shown, the computer device includes a processor, memory, network interface, input device, and display screen connected via a system bus. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system and may also store a computer program. When executed by the processor, this computer program enables the processor to implement the main control board programming detection method provided in this embodiment of the invention. The internal memory may also store a computer program, which, when executed by the processor, enables the processor to execute the main control board programming detection method provided in this embodiment of the invention. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen. The input device of the computer device can be a touch layer covering the display screen, or buttons, a trackball, or a touchpad mounted on the casing of the computer device, or an external keyboard, touchpad, or mouse, etc.

[0029] Those skilled in the art will understand that Figure 5 The structure shown is merely a block diagram of a portion of the structure related to the present invention and does not constitute a limitation on the computer device to which the present invention is applied. A specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0030] In one embodiment, the main control board programming detection device provided by this invention can be implemented as a computer program, and the computer program can be implemented as follows: Figure 5 The program runs on the computer device shown. The computer device's memory can store the various program modules that make up the main control board's programming and testing device, for example... Figure 4The diagram shows a first processing module, a second processing module, a third processing module, a switching module, a fourth processing module, and a judgment module. The computer program comprised of these modules causes the processor to execute the steps in the main control board programming and detection methods described in the various embodiments of the present invention.

[0031] For example, Figure 5 The computer device shown can be used as follows Figure 4 The first processing module in the main control board burning and detection device shown executes step S1; the computer device can execute step S2 through the second processing module; the computer device can execute step S3 through the third processing module; the computer device can execute step S4 through the switching module; the computer device can execute step S5 through the fourth processing module; and the computer device can execute step S6 through the switching module.

[0032] In one embodiment, a computer device is provided, the computer device including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, performs the following steps: S1: After the chips on the motherboard have been programmed, select one chip as the main chip and the others as secondary chips. S2: Send a preset initial task signal to the main chip to enable the main chip to execute the initial task; S3: Monitor the output data of the main chip, determine the entanglement task of the sub-chip based on the output data of the main chip, send the entanglement task signal to the sub-chip, so that the sub-chip can execute the entanglement task, monitor and store the timing characteristics of the execution task. Among them, the execution of the entanglement task by one chip requires the output data of other chips to trigger it. S4: Switch another chip to be the master chip, and the remaining chips to be slave chips. Repeat steps S3 to S4 to complete the detection of each chip under all master-slave relationships. S5: After each chip completes its task, retrieve the task sequence completed by each chip, and determine the temporal entanglement degree of each chip when performing the entanglement task based on each task sequence and the stored temporal characteristics. S6: Determine the overall coordination degree of each chip based on the entanglement degree of each timing sequence, thereby judging whether the motherboard programming is qualified.

[0033] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, causes the processor to perform the following steps: S1: After the chips on the motherboard have been programmed, select one chip as the main chip and the others as secondary chips. S2: Send a preset initial task signal to the main chip to enable the main chip to execute the initial task; S3: Monitor the output data of the main chip, determine the entanglement task of the sub-chip based on the output data of the main chip, send the entanglement task signal to the sub-chip, so that the sub-chip can execute the entanglement task, monitor and store the timing characteristics of the execution task. Among them, the execution of the entanglement task by one chip requires the output data of other chips to trigger it. S4: Switch another chip to be the master chip, and the remaining chips to be slave chips. Repeat steps S3 to S4 to complete the detection of each chip under all master-slave relationships. S5: After each chip completes its task, retrieve the task sequence completed by each chip, and determine the temporal entanglement degree of each chip when performing the entanglement task based on each task sequence and the stored temporal characteristics. S6: Determine the overall coordination degree of each chip based on the entanglement degree of each timing sequence, thereby judging whether the motherboard programming is qualified.

[0034] It should be understood that although the steps in the flowcharts of the various embodiments of the present invention are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the various embodiments may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least a portion of the sub-steps or stages of other steps. Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided by this invention can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0035] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0036] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A master control board burning detection method, characterized in that, The method comprises: S1: after each chip on the mainboard is completed, a chip is selected as a main chip, and the other chips are auxiliary chips; S2: a preset initial task signal is issued to the main chip, so that the main chip executes the initial task; S3: the output data of the main chip is monitored, the entanglement task of the auxiliary chip is determined according to the output data of the main chip, the entanglement task signal is issued to the auxiliary chip, so that the auxiliary chip executes the entanglement task, and the time sequence characteristics of the executed task are monitored and stored, wherein the output data of the other chips triggers the execution of the entanglement task by one chip; S4: another chip is switched as the main chip, and the remaining chips are auxiliary chips, and steps S3 to S4 are repeatedly executed to complete the detection of each chip under all main and auxiliary relationships; S5: after each chip completes the task, the task sequence completed by each chip is called, and the time sequence entanglement degree of each chip when executing the entanglement task is determined according to each task sequence and the stored time sequence characteristics; S6: the comprehensive cooperation degree of each chip is determined according to the time sequence entanglement degree, so as to judge whether the mainboard burning is qualified.

2. The method of claim 1, wherein, The determination of the entanglement task of the auxiliary chip according to the output data of the main chip comprises: S31: all data transmission paths of the main chip and the auxiliary chip are determined, wherein the data transmission path connects the main chip and each auxiliary chip, and the main chip is located at the first node of each data transmission path; S32: one data transmission path is selected; S33: the order of each auxiliary chip is determined according to the position of each auxiliary chip in the data transmission path; S34: for each auxiliary chip, the entanglement task of the auxiliary chip is determined according to the output data of the previous chip and the data dependency rule; S35: steps S32 to S34 are repeatedly executed until the entanglement task of each auxiliary chip under each data transmission path is determined, and the corresponding relationship between the auxiliary chip and the entanglement task under each data transmission path is obtained.

3. The method of claim 2, wherein, The type of data dependency comprises: start dependency, that is, the entanglement task start data must be triggered by the output data of the previous chip; processing dependency, that is, the processing data of the entanglement task must directly come from the output data of the previous chip; Before step S34 is executed, each task in the task library is divided into a plurality of subtasks to obtain a subtask set, wherein each subtask is triggered by specific data received by the chip, and the output data generated after the subtask is executed is output to another chip by the chip.

4. The method of claim 3, wherein, The determination of the entanglement task of the auxiliary chip according to the output data of the previous chip and the data dependency rule comprises: determining that the data type of the output data of the previous chip is a target type; determining all subtasks that need to be triggered by data belonging to the target type from the subtask set to obtain a first subtask set; determining all subtasks that take data belonging to the target type as processing data from the subtask set to obtain a second subtask set; determining the intersection of the first task set and the second task set, and selecting one subtask from the intersection as the entanglement task of the auxiliary chip.

5. The method of claim 2, wherein, The issuance of the entanglement task signal to the auxiliary chip so that the auxiliary chip executes the entanglement task comprises: S301: take one data transmission path; S302: retrieve the corresponding relationship between the sub-chips and the entanglement tasks under the data transmission path; S303: according to the corresponding relationship of the entanglement task, the determined each entanglement task is issued to the corresponding sub-chip; S304: make the main chip re-execute the initial task to trigger each sub-chip to execute the corresponding entanglement task; S305: after the last chip in the data transmission path completes the corresponding entanglement task, take another data transmission path, execute steps S302 to S303, until complete each sub-chip in each data transmission path to execute the entanglement task simulation; Monitoring and storing the timing characteristics of executing tasks include: Monitoring the starting time of each chip executing the task and the time of generating output data after executing the task; Store all the monitoring time storage.

6. The method of claim 5, wherein, According to the task sequence and the stored timing characteristics, the timing entanglement degree of each chip when executing the entanglement task includes: For each data transmission path, the tasks executed by the sub-chips under the data transmission path are filtered out from the task sequence; Each filtered task is assigned a corresponding timing characteristic; Generate a time axis and mark the time period of each filtered task on the time axis according to the corresponding timing characteristic, wherein the time period is the section corresponding to the starting time of the task to the time of generating output data on the time axis; According to the position of each time period, the timing entanglement degree of each sub-chip executing the task under the data transmission path is calculated.

7. The method of claim 6, wherein, According to the position of each time period, the timing entanglement degree of each sub-chip executing the task under the data transmission path is calculated. Determine the number of time periods on the time axis as n, then the number of time period intervals is n-1; The timing matching degree of each time period interval is calculated by the following formula: wherein, is a time sequence matching degree corresponding to the i-th time period interval, is a time difference between the end time of the time period before the i-th time period interval and the start time of the time period before the i-th time period interval, is a preset standard time difference; The timing entanglement degree of each sub-chip executing the task under the data transmission path is calculated by the following formula: wherein, is a timing entanglement, is a data volume coefficient; the data volume coefficient is calculated by the following formula: wherein, is a standard data amount of output data, is an output data amount of the chip corresponding to the i-th time period interval when performing a corresponding task.

8. The method of claim 7, wherein, The comprehensive cooperation degree is calculated by the following formula: wherein, is the degree of synergy, is the jth temporal entanglement obtained, and m is the number of temporal entanglements.

9. A master control board burn detection device, characterized in that, The module in the main control board burning detection device is used to execute the main control board burning detection method in claim 1, specifically including: The first processing module is used to select one chip as the main chip and the other chips as the sub-chips after the chips on the mainboard complete the burning; The second processing module is used to issue the preset initial task signal to the main chip to make the main chip execute the initial task; The third processing module is used to monitor the output data of the main chip, determine the entanglement task of the sub-chip according to the output data of the main chip, issue the entanglement task signal to the sub-chip to make the sub-chip execute the entanglement task, and monitor and store the timing characteristics of executing the task, wherein one chip executing the entanglement task needs the output data of other chips to trigger; The switching module is used to switch another chip as the main chip and the remaining chips as the sub-chips, and repeatedly execute steps S3 to S4 to complete the detection of each chip under all main-sub relationships; The fourth processing module is used to retrieve the task sequence completed by each chip after the chips complete the task, and determine the timing entanglement degree of each chip when executing the entanglement task according to the task sequence and the stored timing characteristics; The judging module is used to determine the comprehensive cooperation degree of each chip according to the timing entanglement degree, so as to judge whether the mainboard burning is qualified.

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