Analog signal verification method and system for digital-analog hybrid simulation

Abstract

The invention relates to the technical field of electronic design automation, in particular to an analog signal verification method for digital-analog hybrid simulation, which comprises the following steps: identifying a plurality of verification nodes in an analog module to be tested; configuring an analog-to-digital conversion threshold parameter for the verification node; in a simulation process, monitoring an analog signal value on the verification node in real time, and converting the analog signal value into a digital logic value according to an analog-to-digital conversion threshold parameter; transmitting the digital logic value to a digital verification platform through an emulator interface; the digital verification platform applies the digital logic value to a digital shadow model corresponding to the tested analog module interface; function coverage collection and assertion check are performed based on the signals of the digital shadow model. According to the method, the problem that analog signals cannot be effectively verified through traditional digital-analog hybrid simulation is solved, verification completeness is remarkably improved, design errors can be automatically found in the early stage, existing digital verification platform resources are fully reused, and verification efficiency and reliability of a mixed signal chip are greatly improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic design automation, and in particular to an analog signal verification method, system and storage medium for mixed-signal simulation. BACKGROUND

[0002] Mixed-signal simulation is a key technology in the field of electronic design automation for verifying complex chip systems containing both digital circuits and analog circuits. It combines the high speed and efficiency of digital simulation with the high precision and high fidelity of analog simulation through a co-simulation engine, enabling designers to comprehensively verify the functionality, performance and reliability of the entire system before tape-out.

[0003] In the field of pure digital verification, a complete and highly automated verification methodology has been established. The most core of which is assertion-based verification and coverage-driven verification. Verification engineers can use languages such as SystemVerilog to write assertions to monitor the behavior of digital signals in real time and report errors immediately if they violate design specifications, greatly accelerating the debugging process. At the same time, by defining a functional coverage model, the coverage of test cases on pre-set function points can be quantitatively measured to ensure the completeness of the verification. These verification activities are usually carried out on a unified verification platform, achieving a high degree of automation and reusability.

[0004] However, the traditional mixed-signal simulation process can only effectively act on the digital signal domain, and has little effect on the analog signal domain. In existing mixed-simulation, analog modules are usually treated as a black box, and the continuously changing signals inside cannot be directly accessed and analyzed by the digital verification platform. Verification work can only indirectly determine whether the analog module is working correctly by observing a few boundary signals, lacking deep monitoring and systematic verification of the behavior of internal key nodes. This limitation cannot apply real-time assertion checks to the complex behavior inside the analog module, and many potential design defects cannot be discovered in the simulation stage; it is difficult for engineers to determine whether the test excitation has fully stimulated all working modes and critical conditions of the analog circuit by defining and collecting functional coverage of key behaviors of analog signals; when system-level faults occur, it becomes extremely difficult to determine whether the problem is from the digital or analog part due to the lack of continuous monitoring and automated checks of analog internal signals, greatly prolonging the debugging cycle.

[0005] Therefore, there is an urgent need in the art for a new method that can effectively extend the assertion and coverage techniques in digital verification to the analog signal domain, thereby achieving complete, efficient and automated verification of mixed-signal systems. SUMMARY

[0006] The application aims to solve the problems in the prior art and provides an analog signal verification method for digital-analog hybrid simulation, comprising: S1: identifying a plurality of key analog signal nodes inside a to-be-tested analog module in a digital-analog hybrid simulation circuit as verification nodes; S2: configuring an analog-digital conversion threshold parameter for each verification node, wherein the analog-digital conversion threshold parameter at least includes a high-level threshold and a low-level threshold; S3: monitoring an analog signal value on the verification node in real time during simulation, and converting the analog signal value into a discrete digital logic value according to the analog-digital conversion threshold parameter; S4: transferring the converted digital logic value to a digital verification platform in real time through a simulator interface; S5: in the digital verification platform, taking the received digital logic value as an input signal and applying it to a digital shadow model corresponding to an interface of the to-be-tested analog module; S6: based on the signal of the digital shadow model, performing at least one of function coverage collection and assertion checking to complete verification of the analog signal.

[0007] Preferably, in step S1, the plurality of key analog signal nodes inside the to-be-tested analog module in the digital-analog hybrid simulation circuit are identified as verification nodes, further comprising: filtering out candidate nodes from the to-be-tested analog module according to dimensions including interface boundary nodes, internal performance key nodes, internal control and state nodes, and fault detection and safety mechanism nodes; determining verification nodes from the candidate nodes according to verification plan priorities and simulation performance overhead, and obtaining a verification node list including node names, belonging submodules, and monitoring reasons.

[0008] Preferably, in step S2, the analog-digital conversion threshold parameter is configured for each verification node, and the analog-digital conversion threshold parameter at least includes a high-level threshold and a low-level threshold, further comprising: configuring the analog-digital conversion threshold parameter for the verification node, wherein the analog-digital conversion threshold parameter includes core parameters and extended parameters, and the core parameters include a high-level threshold and a low-level threshold; storing the analog-digital conversion threshold parameter into an independent configuration file, wherein the configuration file can be read by an analog side simulation environment and a digital side verification platform respectively.

[0009] Preferably, in step S3, the analog signal value on the verification node is monitored in real time, and the analog signal value is converted into a discrete digital logic value, further comprising: When the mixed-signal simulation begins initialization, the simulator dynamically creates and instantiates an independent software monitor object for each of the verification nodes in the verification node list according to the configuration file. Each monitor loads the analog-to-digital conversion threshold parameter of its corresponding verification node from the configuration file; The monitor performs a decision on the analog signal to digital logic. When the analog signal is greater than or equal to the high-level threshold, the decision outputs logic 1; when the analog signal is less than or equal to the low-level threshold, the decision outputs logic 0.

[0010] Preferably, each monitor has a register inside it for tracking the digital logic state of the verification node after the last decision; The new state generated by this judgment is compared with the digital logic state after the previous judgment. If the new state is equal to the digital logic state after the previous judgment, the monitor does not generate any output and waits to be scheduled again. If the new state is not equal to the digital logic state after the previous judgment, it indicates that a digital logic transition event has occurred. At this time, the monitor updates its internal state and generates a digital logic transition event, and encapsulates the digital logic transition event information into an event data structure containing a timestamp, node identifier, and new logical value.

[0011] Preferably, in step S4, the converted digital logic value is transmitted to the digital verification platform in real time through the simulator interface, further including: Use DPI-C, VPI, or emulator-specific APIs as the communication interface. The event data structure, including the digital logical value, is transmitted to the digital verification platform via interface function calls, and is received and cached by a dedicated receiver module on the digital side.

[0012] Preferably, in step S5, applying the received digital logic value to the digital shadow model further includes: Instantiate a shadow model in the digital verification platform with an interface identical to the simulation module under test; Establish a mapping relationship from the node aliases defined in the configuration file for the simulated node under test to the ports of the shadow model; After the receiver module performs time synchronization based on the timestamp in the event data structure, it drives the logical value to the corresponding port of the shadow model.

[0013] Preferably, in step S6, based on the signal of the digital shadow model, at least one of functional coverage collection and assertion checking is performed, further comprising: Define coverage groups for the signals of the shadow model, and sample signal values ​​under clock events to collect functional coverage; Write immediate assertion and concurrent assertion attributes for the signals of the shadow model to check in real time whether the signal behavior meets the expected specifications; An error message is reported immediately when an assertion fails, and a coverage analysis report is generated after the simulation ends.

[0014] Based on the same concept, the present invention also provides a mixed-signal simulation verification system, including: A node identification unit is used to identify and define verification nodes in mixed-signal simulation circuits. A configuration management unit is used to store and manage the analog-to-digital conversion threshold parameters configured for the verification node; The analog-side monitor runs in an analog simulation environment and is used to monitor analog signals and perform analog-to-digital conversion based on threshold parameters. The communication interface unit is used to transmit the converted digital logic value from the analog side to the digital side; The digital shadow model, located in the digital verification platform, has the same interface as the simulation module under test and is used to receive and map digital logic values ​​from the communication interface unit. The verification execution unit, integrated into the digital verification platform, is used to collect functional coverage and perform assertion checks on the signals of the digital shadow model. The verification execution unit is a UVM-based test platform.

[0015] Based on the same concept, the present invention also provides a computer-readable storage medium storing computer code, which, when executed, performs the steps of the analog signal verification method for mixed-signal simulation as described in any one of the embodiments.

[0016] Compared with the prior art, the beneficial effects of the present invention are: This invention identifies several key analog signal nodes within the analog module under test in a mixed-signal simulation circuit as verification nodes, configures analog-to-digital conversion threshold parameters for the verification nodes, monitors the analog signal values ​​on the verification nodes in real time during the simulation process, and converts the analog signal values ​​into discrete digital logic values ​​according to the analog-to-digital conversion threshold parameters. This extends the application of mature digital verification methodologies to analog circuits, enabling the key behaviors of analog signals to be quantified and checked in real time. As a result, it achieves true full-chip functional verification of mixed-signal systems, greatly improving the depth and breadth of verification.

[0017] This invention utilizes a digital verification platform, where received digital logic values ​​are used as input signals and applied to a digital shadow model corresponding to the interface of the analog module under test. The digital verification platform, verification IP, assertions, and coverage libraries can all be directly used to process signals from the shadow model. This allows existing verification assets and engineers' skills to be preserved; by simply adding the modules and interfaces specified in this method, mixed-signal verification capabilities can be obtained, protecting existing investments and reducing the difficulty and cost of technology migration. This invention verifies analog signals by performing at least one of functional coverage collection and assertion checks based on signals from a digital shadow model. It can immediately capture abnormal behavior of the analog module during simulation and report errors promptly. This changes the inefficient traditional method of relying on engineers to manually examine waveforms to troubleshoot analog faults, transforming debugging from manual post-incident analysis to in-process automatic alerts, significantly shortening the debugging cycle. Early error detection also prevents defects from spreading throughout the development process, thereby significantly reducing the cost and risk of later repairs. Attached Figure Description

[0018] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention.

[0019] Figure 1 This is a flowchart of an analog signal verification method for mixed-signal simulation according to the present invention; Figure 2 This is a schematic diagram illustrating the conversion of an analog signal verification method for mixed-signal simulation according to the present invention. Figure 3 This is a schematic diagram illustrating the transmission of digital logic values ​​to the digital verification platform according to the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. Obviously, the described embodiments are only some, not all, of the embodiments described in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without creative effort are within the scope of protection of this application.

[0021] Those skilled in the art will understand that, unless otherwise stated, the singular forms “a” and “an” used herein, and “the”, may also include the plural forms. It should be further understood that the term “comprising” as used in this specification means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0022] First Embodiment Please see Figure 1 As shown in the figure, this embodiment provides an analog signal verification method for mixed-signal simulation, including: S1: Identify several key analog signal nodes inside the analog module under test in the mixed-signal simulation circuit as verification nodes.

[0023] The detailed design specification document for the input analog module defines the module's functions, performance indicators (such as gain, bandwidth, and settling time), operating modes (such as normal operating mode and power saving mode), and electrical characteristics of the input / output interfaces.

[0024] Input the transistor-level or macro-model-level netlist of the analog circuit, analyze the circuit's topology, identify the main functional sub-blocks (e.g., operational amplifiers, bandgap reference voltage sources, comparators, filters, etc.), and understand the signal flow paths between these sub-blocks.

[0025] The input should be a verification plan based on the design specifications, clearly defining the verification objectives. The verification plan will list the functionalities and scenarios to be tested. For example: testing the output clamping function of the operational amplifier under input overload or verifying the behavior of the power management module under undervoltage lockout (UVLO).

[0026] Preferably, in step S1, identifying several key analog signal nodes inside the analog module under test in the mixed-signal simulation circuit as verification nodes further includes: Candidate nodes are selected from the analog module under test based on dimensions including interface boundary nodes, internal performance key nodes, internal control and state nodes, and fault detection and safety mechanism nodes. Specifically, in this embodiment, candidate nodes are selected based on the input detailed design specification document, the transistor-level or macro-model-level network of the analog circuit, and the verification plan. Interface boundary nodes are the points where the analog module exchanges information with the external digital module and are naturally key points. Internal performance key nodes include the output of operational amplifiers / comparators, high-impedance nodes, key nodes of bias circuits, and the output of internal voltage regulators. The signal quality of these nodes directly determines the performance indicators of the module. Internal control and state nodes are those inside the analog module that often contain finite state machines or digital control logic (e.g., for power-on sequences, mode switching). Fault detection and safety mechanism nodes are circuit nodes specifically designed to detect abnormal conditions (such as over-temperature, over-current, and short circuit). Based on the priority of the verification plan and the simulation performance overhead (monitoring too many nodes will reduce the simulation speed), the verification nodes are determined from the candidate nodes, and a list of verification nodes including the node name, the submodule to which it belongs, and the monitoring reason is obtained. Specifically, in this embodiment, the list of verification nodes is formally incorporated into the setup script or configuration file of the mixed-signal simulation.

[0027] S2: Configure analog-to-digital conversion threshold parameters for each verification node. The analog-to-digital conversion threshold parameters include at least a high-level threshold and a low-level threshold.

[0028] This embodiment allows users to precisely define under what circumstances an analog signal is considered a valid digital event, based on different verification stages and concerns, through configurable threshold parameters (such as hith, loth, hysteresis).

[0029] Preferably, in step S2, an analog-to-digital conversion threshold parameter is configured for each verification node. The analog-to-digital conversion threshold parameter includes at least a high-level threshold and a low-level threshold, and further includes: To verify the configuration of analog-to-digital conversion threshold parameters for nodes, the analog-to-digital conversion threshold parameters include core parameters and extended parameters. The core parameters include high-level thresholds and low-level thresholds. Specifically, in this embodiment, the extended parameters include hysteresis voltage to prevent frequent logic jumps when the signal fluctuates near the threshold, high-impedance threshold to determine when a node should be identified as a high-impedance state, and for multi-level signals, multiple sets of thresholds can be defined to map a specific voltage range to different digital states. The analog-to-digital conversion threshold parameter is stored in a separate configuration file that can be read by both the analog simulation environment and the digital verification platform. Specifically, in this embodiment, the analog-to-digital conversion threshold parameter is stored in JSON, YAML, XML, CSV / Toml or plain text format.

[0030] Before starting the mixed-signal simulation, you need to ensure that both the analog-side monitor and the digital-side verification platform can access the same configuration file.

[0031] The simulator (or its monitor plugin) reads the configuration file during initialization, finds the corresponding circuit node based on simulation_net_name, loads its threshold parameters, and establishes real-time monitoring and conversion rules.

[0032] The digital validation platform (Testbench) reads the same file (configuration file) during the build phase, primarily to obtain aliases and expected logical behavior for subsequent build assertions and coverage groups. While the digital side does not directly perform the conversion, it must be aware of the rules to ensure validation accuracy. Figure 1 To.

[0033] At the start of the simulation, the digital Testbench queries the threshold parameters of a certain node from the simulation side via an API (such as a DPI call) and compares them with the configuration read locally. If there is a difference, an error is reported and the simulation is terminated to prevent incorrect verification conclusions caused by inconsistent configurations. This achieves consistency checks and ensures that the simulation side and the digital side have the same understanding of the same node.

[0034] The following is an example stored in JSON format, which intuitively reflects the mapping relationship between nodes and parameters. { "a2d_monitor_config": { "nodes": [ { "simulation_net_name": "I_analog_core.opa1.out", # simulation_net_name: The complete node path in the simulation netlist, used for precise positioning by tools. "alias": "opamp_output", #alias: An alias for this node, making it easy to reference in the digital verification platform and avoiding the use of lengthy netlist paths. "thresholds": {#thresholds contains sub-objects of all threshold parameters} "hith": 1.25, #High-level threshold "loth": 0.15, #low level threshold "hysteresis": 0.05, #hysteresis voltage "vsup": 1.8 } }, { "simulation_net_name": "I_analog_core.comparator.in_n", "alias": "vref_compare", "thresholds": { "hith": 0.9, "loth": 0.9, "hysteresis": 0.02 } } ] }}.

[0035] S3: During the simulation, the analog signal values ​​on the verification node are monitored in real time, and the analog signal values ​​are converted into discrete digital logic values ​​according to the analog-to-digital conversion threshold parameter.

[0036] Please see Figure 2 As shown, in step S3, the analog signal value on the verification node is monitored in real time, and the analog signal value is converted into discrete digital logic value, which further includes: When the mixed-signal simulation begins initialization, the simulator dynamically creates and instantiates an independent software monitor object for each verification node in the verification node list according to the configuration file. Specifically, in this embodiment, the dynamic creation of software monitor objects is usually implemented using the programming interface provided by the simulator, such as: threshold cross functions such as @cross() or above() in Erilog-AMS, VPI (Verilog Procedural Interface) for accessing and monitoring the signal values ​​of a specific network, and the simulator's dedicated APIs (such as Cadence's SimVision API, Synopsys' VCS API, etc.). Each monitor loads the analog-to-digital conversion threshold parameters for its corresponding verification node from the configuration file. Specifically, in this embodiment, each monitor loads the threshold parameters (hith, loth, hysteresis, etc.) for its corresponding node from the configuration file. During the simulation process of solving the circuit equations, the simulator tracks voltage changes on each network. The monitors are not checked at every simulation point in time (that would be extremely slow). Instead, an event-driven approach is used. When the voltage value of a monitored node is likely to change enough to alter its logic state (i.e., approaching a set threshold), the corresponding monitor is scheduled and activated to perform an evaluation check. This ensures high efficiency. The monitor performs analog signal to digital logic decision-making. When the analog signal is greater than or equal to a high-level threshold, it outputs logic 1; when the analog signal is less than or equal to a low-level threshold, it outputs logic 0. Specifically, in this embodiment, the precise voltage value V_current of the node at this moment is obtained from the simulation kernel. V_current is compared with the stored threshold. If V_current >= hith, logic 1 is output; if V_current <= loth, logic 0 is output; if loth < V_current < hith, the output is unknown X or the previous state is maintained. With hysteresis, assuming the current state is 0, the state only flips to 1 when V_current >= (hith + hysteresis / 2); assuming the current state is 1, the state only flips to 0 when V_current <= (loth - hysteresis / 2). This effectively eliminates jitter caused by noise.

[0037] Preferably, each monitor has an internal register for tracking the digital logic state of the verification node after its last decision; The new state `new_state` generated by this decision is compared with the digital logic state `new_state` after the previous decision. If the new state is equal to the digital logic state after the previous decision, the monitor does not generate any output and waits to be scheduled again. If the new state is not equal to the digital logic state after the previous decision, it indicates that a digital logic transition event has occurred (e.g., a rising edge from 0 to 1, or a falling edge from 1 to 0). At this time, the monitor updates its internal state (updates `previous_state` to `new_state`) and generates a digital logic transition event. The generated digital logic transition event information is encapsulated into an event data structure containing a timestamp (simulation time), a node identifier (an alias defined in the configuration file), and a new logic value (`new_state`).

[0038] S4: The converted digital logic value is transmitted to the digital verification platform in real time through the simulator interface. Specifically, in this embodiment, the simulator interface is one of VPI, DPI or Verilog-AMS's $abstime interface.

[0039] Please see Figure 3 As shown, in step S4, the converted digital logic value is transmitted to the digital verification platform in real time through the simulator interface, further including: Use DPI-C, VPI, or simulator-specific APIs as communication interfaces. Specifically, in this embodiment, DPI-C is used as the communication interface. In SystemVerilog Testbench, import a C function that receives data sent from the analog side. In the C code (or Verilog-AMS's $extern), implement a transfer function that can be called by the analog monitor. This function calls the function defined on the digital side to push the data to the digital domain. The event data structure, including digital logical values, is passed to the digital verification platform via interface function calls. A dedicated receiver module on the digital side receives and caches the data. Specifically, in this embodiment, since the `push_analog_event` function is imported on the digital side, the simulator schedules and executes this function within the digital simulation domain. After receiving data from the analog side, its core task is to write the data into a thread-safe FIFO (First-In-First-Out queue) or a mailbox. This caching structure serves to decouple and synchronize the data, balancing the potentially different execution rhythms of the two simulation domains. The digital testbench has a dedicated receiver module. This module monitors the FIFO / mailbox in a continuous process. Once new data appears in the FIFO, the receiver module immediately retrieves the event data structure. The receiver parses the data packet, extracting the node alias, logical value, and timestamp. The receiver compares the timestamp in the data packet with `$realtime` or `$time` to ensure that the event is processed at the correct simulation time. If needed, it can use #delay or clock-based events to wait for a precise time point, at which point the receiver will drive the logic value to the corresponding port of the digital shadow model (DUTx) defined by S5.

[0040] S5: In the digital verification platform, the received digital logic value is used as an input signal and applied to a digital shadow model corresponding to the interface of the analog module under test.

[0041] Preferably, in step S5, applying the received digital logic value to the digital shadow model further includes: In the digital verification platform (Testbench), a shadow model (DUTx) with the same interface as the simulation module under test is instantiated. Specifically, in this embodiment, the port list (interface) of the shadow model must be completely consistent with the ports of the simulation module (DUTa) being monitored (including port name, bit width and orientation). A mapping relationship is established from the node alias defined in the configuration file for the simulated node under test to the shadow model port. Specifically, in this embodiment, the simulated node alias is "opamp_output", the DUTx port name is dutx.analog_out, and the mapping table entry is "opamp_output" -> dutx.analog_out. The received data packets (event data structure) are not immediately driven to the DUTx, but are placed in a thread-safe FIFO (first-in, first-out queue) or mailbox. In the digital testbench, a dedicated receiver module or process continuously monitors this FIFO. Once the FIFO is not empty, the receiver takes a data packet from the queue. After synchronizing time based on the timestamp in the event data structure, the receiver module drives the logical value to the corresponding port of the shadow model. Specifically, in this embodiment, the receiver compares the timestamp in the data packet with the current simulation time ($realtime). If the timestamp is a past time, it indicates that the data arrived late due to simulation scheduling. This may be an error condition and a warning needs to be reported. If the timestamp is a future time, the receiver will actively wait using timing control statements such as #delay or @(time) until the simulation time advances to the precise timestamp. This is a crucial step to ensure timing correctness. If the timestamp is the current time, the next step is immediately performed. The receiver uses Force / Deposit or non-blocking assignment (NBA) to drive the new logical value in the data packet to the target port of DUTx.

[0042] The SystemVerilog pseudocode for driving the new logical value in the data packet to the target port of the DUTx is as follows: systemverilog / / At the correct simulation time point receiver_module force_dutx; string node_alias = pkt.node_alias; logic value = pkt.value; / / Look up the mapping table string dutx_net_name = lookup_map(node_alias); / / Drive Shadow Model $deposit(dutx_net_name, value); / / Or use force / release S6: Based on the digital shadow model, perform at least one of functional coverage collection and assertion checking to complete the verification of the analog signal. Specifically, in this embodiment, assertion checking includes immediate assertions and clock cycle-based concurrent assertions; concurrent assertions are used to verify the timing behavior and state transition relationships of the analog signal.

[0043] Preferably, in step S6, based on the signal from the digital shadow model, at least one of functional coverage collection and assertion checking is performed, further comprising: Coverage groups are defined for the shadow model's signals, and signal values ​​are sampled at clock events to collect functional coverage. Specifically, in this embodiment, according to the verification plan, the functional characteristics that the simulation module needs to verify are converted into measurable coverpoints and cross coverages. The coverage groups need to record the signal state at specific sampling events. The most commonly used is the rising edge of the clock (@(posedge clk)), which ensures sampling at stable moments and avoids glitches.

[0044] Write immediate and concurrent assertion properties for the signals of the shadow model to check whether the signal behavior conforms to the expected specifications in real time. Specifically, in this embodiment, during simulation, the assertion checker will continuously monitor the signals of DUTx. Once it detects that the signal behavior does not match the property description, the assertion will fail immediately and print error information (including time, file name, line number, and reason for failure) in the simulation log, thereby quickly locating design defects.

[0045] According to the design specifications, write assertion properties for the signals of the shadow model (DUTx): Immediate assertions: Used to check static conditions.

[0046] systemverilog / / Check if the analog power supply monitoring signal is always valid (not X or Z). always_comb begin assert (std::isunknown(DUTx.pwr_good) == 0) else $error("Analog power good signal is invalid!"); end Concurrent assertions: Used to check timing relationships. This is the most common form.

[0047] systemverilog / / After the enable check is completed, the analog output should respond within a specified time (e.g., go high within 3 clock cycles). property p_analog_response; @(posedge clk) disable iff (!rst_n) ($rose(DUTx.enable)) |-> ##[1:3] ($rose(DUTx.output_high)); endproperty a_analog_response: assert property (p_analog_response).

[0048] An error message is reported immediately when an assertion fails, and a coverage analysis report is generated after the simulation ends.

[0049] Coverage data can drive automated regression testing to identify uncovered functionalities; assertion checks can be seamlessly integrated into continuous integration / CD processes, providing a technological foundation for establishing standardized, automated mixed-signal verification processes and helping to improve the reliability and efficiency of the entire chip design process. Second Embodiment Based on the same concept, the present invention also provides a mixed-signal simulation verification system, including: A node identification unit is used to identify and define verification nodes in mixed-signal simulation circuits. The configuration management unit is used to store and manage the analog-to-digital conversion threshold parameters configured for the verification nodes; The analog-side monitor runs in an analog simulation environment and is used to monitor analog signals and perform analog-to-digital conversion based on threshold parameters. The communication interface unit is used to transmit the converted digital logic value from the analog side to the digital side; The digital shadow model, located in the digital verification platform, has the same interface as the simulation module under test and is used to receive and map digital logic values ​​from the communication interface unit. The verification execution unit, integrated into the digital verification platform, is used to collect functional coverage and perform assertion checks on the signals of the digital shadow model. The verification execution unit is a UVM-based test platform.

[0050] Third Embodiment In this embodiment, a computer device is provided, including a memory and one or more processors. The memory stores computer code, and when the computer code is executed by one or more processors, the one or more processors perform the steps of the analog signal verification method for mixed-signal simulation in the first embodiment.

[0051] In some embodiments of this application, a computer-readable storage medium is also provided, wherein when the computer-readable instructions are executed by one or more processors, the one or more processors perform the steps of the analog signal verification method for mixed-signal simulation as described in any one of the first embodiments.

[0052] It is understood that, for the aforementioned analog signal verification methods for mixed-signal simulation, if all are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer server or a network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes: USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, optical disks, and other media capable of storing program code.

[0053] Computer-readable storage media may include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable storage medium may also be any readable medium other than a readable storage medium that can transmit, propagate, or transfer a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the readable storage medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0054] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A method for verifying analog signals in mixed-signal simulation, characterized in that, Includes the following steps: S1: Identify several key analog signal nodes inside the analog module under test in the mixed-signal simulation circuit as verification nodes; S2: Configure an analog-to-digital conversion threshold parameter for each of the verification nodes, wherein the analog-to-digital conversion threshold parameter includes at least a high-level threshold and a low-level threshold; S3: During the simulation, the analog signal value on the verification node is monitored in real time, and the analog signal value is converted into discrete digital logic value according to the analog-to-digital conversion threshold parameter; S4: The converted digital logic value is transmitted to the digital verification platform in real time through the simulator interface; S5: In the digital verification platform, the received digital logic value is used as an input signal and applied to a digital shadow model corresponding to the interface of the simulation module under test. S6: Based on the signal from the digital shadow model, perform at least one of functional coverage collection and assertion checking to complete the verification of the analog signal.

2. The analog signal verification method for mixed-signal simulation according to claim 1, characterized in that, In step S1, identifying several key analog signal nodes within the analog module under test in the mixed-signal simulation circuit as verification nodes further includes: Candidate nodes are selected from the simulation module under test based on dimensions including interface boundary nodes, internal performance key nodes, internal control and status nodes, and fault detection and security mechanism nodes. Verification nodes are determined from the candidate nodes based on the verification plan priority and simulation performance overhead, and a list of verification nodes including node name, submodule to which they belong, and monitoring reason is obtained.

3. The analog signal verification method for mixed-signal simulation according to claim 1, characterized in that, In step S2, an analog-to-digital conversion threshold parameter is configured for each verification node. The analog-to-digital conversion threshold parameter includes at least a high-level threshold and a low-level threshold, and further includes: Configure the analog-to-digital conversion threshold parameters for the verification node. The analog-to-digital conversion threshold parameters include core parameters and extended parameters. The core parameters include high-level thresholds and low-level thresholds. The analog-to-digital conversion threshold parameter is stored in a separate configuration file, which can be read by both the analog simulation environment and the digital verification platform.

4. The analog signal verification method for mixed-signal simulation according to claim 3, characterized in that, In step S3, the analog signal value on the verification node is monitored in real time, and the analog signal value is converted into discrete digital logic value, further including: When the mixed-signal simulation begins initialization, the simulator dynamically creates and instantiates an independent software monitor object for each of the verification nodes in the verification node list according to the configuration file. Each monitor loads the analog-to-digital conversion threshold parameter of its corresponding verification node from the configuration file; The monitor performs a decision on the analog signal to digital logic. When the analog signal is greater than or equal to the high-level threshold, the decision outputs logic 1; when the analog signal is less than or equal to the low-level threshold, the decision outputs logic 0.

5. The analog signal verification method for mixed-signal simulation according to claim 4, characterized in that, Each monitor has an internal register used to track the digital logic state of the verification node after its last decision; The new state generated by this decision is compared with the digital logic state after the previous decision. If the new state is equal to the digital logic state after the previous decision, the monitor does not generate any output and waits to be scheduled next. If the new state is not equal to the digital logic state after the last decision, it indicates that a digital logic transition event has occurred. At this time, the monitor updates its internal state and generates a digital logic transition event, and encapsulates the digital logic transition event information into an event data structure containing a timestamp, node identifier, and new logical value.

6. The analog signal verification method for mixed-signal simulation according to claim 1, characterized in that, In step S4, the converted digital logic value is transmitted to the digital verification platform in real time through the simulator interface, further including: Use DPI-C, VPI, or emulator-specific APIs as the communication interface. The event data structure, including the digital logical value, is transmitted to the digital verification platform via interface function calls, and is received and cached by a dedicated receiver module on the digital side.

7. The analog signal verification method for mixed-signal simulation according to claim 6, characterized in that, In step S5, the received digital logic value is applied to the digital shadow model, which further includes: Instantiate a shadow model in the digital verification platform with an interface identical to the simulation module under test; Establish a mapping relationship from the node aliases defined in the configuration file for the simulated node under test to the ports of the shadow model; After the receiver module performs time synchronization based on the timestamp in the event data structure, it drives the logical value to the corresponding port of the shadow model.

8. The analog signal verification method for mixed-signal simulation according to claim 1, characterized in that, In step S6, based on the signal from the digital shadow model, at least one of functional coverage collection and assertion checking is performed, further including: Define coverage groups for the signals of the shadow model, and sample signal values ​​under clock events to collect functional coverage; Write immediate assertion and concurrent assertion attributes for the signals of the shadow model to check in real time whether the signal behavior meets the expected specifications; An error message is reported immediately when an assertion fails, and a coverage analysis report is generated after the simulation ends.

9. A hybrid simulation verification system for implementing the method of any one of claims 1 to 8, characterized in that, include: A node identification unit is used to identify and define verification nodes in mixed-signal simulation circuits. A configuration management unit is used to store and manage the analog-to-digital conversion threshold parameters configured for the verification node; The analog-side monitor runs in an analog simulation environment and is used to monitor analog signals and perform analog-to-digital conversion based on threshold parameters. The communication interface unit is used to transmit the converted digital logic value from the analog side to the digital side; The digital shadow model, located in the digital verification platform, has the same interface as the simulation module under test and is used to receive and map digital logic values ​​from the communication interface unit. The verification execution unit, integrated into the digital verification platform, is used to collect functional coverage and perform assertion checks on the signals of the digital shadow model. The verification execution unit is a UVM-based test platform.

10. A computer-readable storage medium storing computer code, wherein when the computer code is executed, the steps of the analog signal verification method for mixed-signal simulation as described in any one of claims 1-8 are performed.

Images