Signal time sequence verification method and device, electronic equipment, chip and medium

Abstract

The invention provides a signal time sequence verification method and device, electronic equipment, a chip and a medium, and relates to the technical field of chip verification, and the method comprises the steps: carrying out the real number modeling of a first analog circuit module, and obtaining a target behavior model; performing netlist extraction on the first analog circuit module by using a netlist extraction tool to obtain a target netlist file; and obtaining a to-be-tested analog circuit module based on the target netlist file, so as to construct a digital-analog simulation verification platform according to the to-be-tested analog circuit module and a predetermined to-be-tested digital circuit module. A digital-analog verification platform is constructed in a mode of performing real number modeling on an analog circuit module, so that chip signal time sequence verification simulation is performed according to the digital-analog verification platform, and the simulation speed can be effectively improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip verification, and in particular to a signal timing verification method and device, an electronic device, a chip and a medium. BACKGROUND

[0002] With the rapid development of integrated circuit design and manufacturing technology, digital-analog hybrid circuit chips (such as memory chips, high-speed interface chips, etc.) are widely used in various electronic devices due to their analog signal processing and digital logic control functions. However, in the verification phase, the timing verification of the digital-analog interface often faces the problems of a large number of interfaces, complex constraints between signals, and the need to improve the simulation speed of interface timing verification to improve verification efficiency.

[0003] Currently, there are three main ways to perform timing verification of digital-analog hybrid circuits in related technologies. One is to use SPICE (Simulation Program with Integrated Circuit Emphasis) to simulate the physical characteristics of the circuit for verification. Another is to abstract the analog circuit schematic into a behavior-level model based on the Verilog language, and then combine it with the register transfer level (RTL) code of the digital logic for VCS (Verilog Compiled Simulator) simulation verification. The third is to use the digital simulation tool VCS and the analog simulation tool XA (Xcelium Analog) for co-simulation verification.

[0004] However, when related technologies face scenarios such as memory chips containing a large number of storage units, the computational load of the analog part is still large, and the simulation speed will decrease significantly, making it difficult to meet the needs of efficient verification. SUMMARY

[0005] The present application provides a signal timing verification method, device, electronic device, chip and medium to solve the problem of low simulation speed in related technologies. By modeling the first analog circuit module as a real number to obtain a signal behavior model containing both analog electrical information and digital logic information, and using a netlist extraction tool to extract top-level port information to obtain a target netlist file containing a behavior model file, a digital-analog simulation verification platform is constructed with the to-be-tested analog circuit module and the to-be-tested digital circuit module, which can effectively improve the simulation speed of digital-analog interface timing verification.

[0006] The first aspect of the embodiments of the present application provides a signal timing verification method, which comprises: performing real number modeling on a first analog circuit module to obtain a target behavior model, the target behavior model comprising signals carrying analog electrical information and digital logic information, the analog electrical information and the digital logic information being associated; performing netlist extraction on the first analog circuit module by using a netlist extraction tool to obtain a target netlist file, the target netlist file comprising top port information of the first analog circuit module and a behavior model file corresponding to the target behavior model; and obtaining a to-be-tested analog circuit module based on the target netlist file, so as to construct a digital-analog simulation verification platform according to the to-be-tested analog circuit module and a pre-determined to-be-tested digital circuit module, the digital-analog simulation verification platform being used for timing verification on interactive signals between the to-be-tested analog circuit module and the to-be-tested digital circuit module.

[0007] In some embodiments of the present application, the obtaining of the target behavior model by performing real number modeling on the first analog circuit module comprises: performing real number modeling on the first analog circuit module to generate an initial behavior model; obtaining delay information of the first analog circuit module by using a simulation tool; and labeling the delay information in the initial behavior model to obtain the target behavior model.

[0008] In some embodiments of the present application, the obtaining of the target netlist file by performing netlist extraction on the first analog circuit module by using the netlist extraction tool comprises: performing netlist extraction on the first analog circuit module by using the netlist extraction tool to obtain an initial netlist file, the initial netlist file comprising top port information of the first analog circuit module; and adding the behavior model file corresponding to the target behavior model to the initial netlist file to obtain the target netlist file.

[0009] In some embodiments of the present application, the obtaining of the to-be-tested analog circuit module based on the target netlist file comprises: obtaining delay information of a second analog circuit module from a pre-set basic unit database, and labeling the delay information in the second analog circuit module; and combining the second analog circuit module with the labeled delay information and the target netlist file to obtain the to-be-tested analog circuit module.

[0010] In some embodiments of the present application, the construction of the digital-analog simulation verification platform according to the to-be-tested analog circuit module and the pre-set to-be-tested digital circuit module comprises: combining the to-be-tested analog circuit module and the to-be-tested digital circuit module to obtain a target to-be-tested module; and combining the target to-be-tested module and a pre-set verification component to construct the digital-analog simulation verification platform.

[0011] In some embodiments of this application, a digital-to-analog circuit verification platform is constructed based on the analog circuit module under test and a pre-defined digital circuit module under test. The method then includes: determining the names of the interaction signals between the analog circuit module under test and the digital circuit module under test; determining the timing constraints of the interaction signals based on the interaction signal names; generating timing verification code based on the timing constraints; and embedding the timing verification code into the digital-to-analog circuit verification platform to verify the timing relationship of the interaction signals between the analog circuit module under test and the digital circuit module under test using the digital-to-analog circuit verification platform with embedded timing verification code.

[0012] A second aspect of this application provides a signal timing verification apparatus, the apparatus comprising: The real-number modeling unit is used to perform real-number modeling on the first analog circuit module to obtain the target behavior model. The target behavior model includes signals carrying analog electrical information and digital logic information, and the analog electrical information and digital logic information are associated. The extraction unit is used to extract the netlist of the first analog circuit module using a netlist extraction tool to obtain a target netlist file. The target netlist file includes the top-level port information of the first analog circuit module and the behavior model file corresponding to the target behavior model. The construction unit is used to obtain the analog circuit module under test based on the target netlist file, and to build a digital simulation verification platform based on the analog circuit module under test and the pre-determined digital circuit module under test. The digital simulation verification platform is used to perform timing verification of the interaction signals between the analog circuit module under test and the digital circuit module under test.

[0013] A third aspect of this application provides an electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the methods described in the first aspect of this application.

[0014] A fourth aspect of this application provides a chip including one or more interface circuits and one or more processors; the interface circuits are configured to receive signals from the memory of an electronic device and send signals to the processors, the signals including computer instructions stored in the memory, which, when executed by the processors, cause the electronic device to perform the methods described in the first aspect of this application.

[0015] A fifth aspect of this application provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause a computer to perform the methods described in the first aspect of this application.

[0016] In summary, according to the signal timing verification method proposed in this application, a target behavioral model is obtained by performing real-valued modeling on the first analog circuit module; a netlist extraction tool is used to extract the netlist from the first analog circuit module to obtain a target netlist file containing the top-level port information of the first analog circuit module and the behavioral model file corresponding to the behavioral model; based on the target netlist file, the analog circuit module under test is obtained, and a digital simulation verification platform for timing verification of the interaction signals between the analog circuit module under test and the pre-determined digital circuit module under test is constructed according to the analog circuit module under test and the pre-determined digital circuit module under test. This process simplifies the physical details of the analog circuit and reduces the amount of computation by establishing a behavioral model through real-valued modeling of the analog circuit module, thereby effectively improving the simulation speed of timing verification of digital-analog interface interaction signals.

[0017] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application, and do not constitute an undue limitation of this application.

[0019] Figure 1 A flowchart of a signal timing verification method provided in an embodiment of this application; Figure 2 A flowchart illustrating the second signal timing verification method provided in this application embodiment; Figure 3 A flowchart of the third signal timing verification method provided in the embodiments of this application; Figure 4 A flowchart illustrating the fourth signal timing verification method provided in this application embodiment; Figure 5 This is a schematic diagram of the structure of a digital simulation verification platform provided in an embodiment of this application; Figure 6 A general flowchart for signal timing verification provided in an embodiment of this application; Figure 7 A schematic diagram of an interactive signal timing table provided in an embodiment of this application; Figure 8 This is a schematic diagram of the structure of a signal timing verification device provided in an embodiment of this application; Figure 9 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application; Figure 10 This is a schematic diagram of the structure of a chip provided in an embodiment of this application. Detailed Implementation

[0020] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0021] Against the backdrop of rapid development in integrated circuit design and manufacturing technology, mixed-signal circuit chips (such as memory chips and high-speed interface chips) have been widely used in consumer electronics, communication equipment, and industrial control due to their combination of analog signal processing capabilities and digital logic control functions. In mixed-signal circuit chips, analog circuits are responsible for processing continuously changing physical signals (such as voltage and current), while digital circuits undertake functions such as logic operations, data storage, and control instruction execution. The analog-digital interface connecting the two is a key node for signal interaction, and its timing characteristics, including signal delay, edge alignment, and level transition synchronization, directly affect the overall performance, stability, and reliability of the chip.

[0022] Currently, there are three main approaches to signal timing verification of mixed-signal circuits: The first is SPICE-based simulation, which uses a physical model of the circuit to solve the current and voltage equations of semiconductor devices, simulating the circuit's behavior under different operating conditions, including subtle signal changes and delay characteristics. The second is abstracting the analog circuit schematic into a behavioral-level model based on Verilog, combining it with digital logic RTL code for VCS simulation. The third is joint simulation using VCS and XA, where VCS is used to simulate the digital circuit portion, XA is used to simulate the analog circuit portion, and standard interfaces such as VPI (Verilog Procedural Interface), DPI (Direct Programming Interface), or a collaborative engine are used to achieve real-time data interaction between the two, jointly completing the timing verification of the mixed-signal circuit.

[0023] However, especially for memory chips, due to the load characteristics of memory chips (such as massive cells and high-density connections), when related technologies face the huge load of memory cells, the amount of computation, data and timing analysis required for simulation increases exponentially, which makes the simulation speed very slow. Moreover, timing checks rely heavily on manual work and some assertions, lacking quantitative standards, which makes it difficult to meet the requirements for verification accuracy, efficiency and completeness.

[0024] To address the aforementioned issues, this application proposes a signal timing verification method. This method involves real-valued modeling of a first analog circuit module and injecting delay information to obtain a target behavioral model containing associated analog electrical and digital logic information. A netlist file containing top-level port information and the behavioral model file is then obtained using a netlist extraction tool. This netlist file is combined with a second analog circuit module containing the injected delay information to obtain the analog circuit module under test (DUT). The DUT and DUT are then combined to construct a digital-analog simulation verification platform for timing verification of interactive signals. This process simplifies the physical details of the analog circuit and reduces computational load by establishing a behavioral model for the analog circuit module, thereby improving simulation speed during timing simulation verification of digital-analog interface interactive signals. Furthermore, injecting delay information into the analog circuit module further improves simulation accuracy and enhances the completeness of interface signal timing verification.

[0025] The signal timing verification method provided in this application will be described in detail below with reference to the accompanying drawings.

[0026] Figure 1 This is a flowchart illustrating a signal timing verification method provided in an embodiment of this application. Figure 1 As shown, the signal timing verification method includes steps 101-103.

[0027] Step 101: Perform real-number modeling on the first analog circuit module to obtain the target behavior model.

[0028] In the embodiments of this application, the first analog circuit module refers to a non-digital logic analog circuit module, that is, a circuit module that operates entirely with analog signals (continuously changing voltage, current, etc.) and does not involve digital logic (such as 0 / 1 discrete states, logic gate operations). The target behavior model is an abstract description of the "input-to-output functional behavior" of the analog circuit. It does not focus on which specific components the analog circuit is composed of, but only on what output result the analog circuit will produce under what input conditions.

[0029] The signals in the target behavior model contain two types of information: analog electrical information and digital logic information. The analog electrical information (continuous voltage and current values) is represented by real numbers, reflecting the physical characteristics of the analog signal. The digital logic information, such as logic 0 or 1 corresponding to high and low levels, reflects the digital logic state of the signal.

[0030] Analog electrical information and digital logic information are related, that is, there is a certain mapping relationship between analog physical quantities and digital logic states. For example, a voltage greater than or equal to 2.5V corresponds to logic 1, and a voltage less than or equal to 0.5V corresponds to logic 0.

[0031] Specifically, for the first analog circuit module, a real-number modeling method that preserves continuous numerical characteristics is adopted to construct a behavioral model for non-digital logic analog circuit modules (such as analog-to-digital converters (ADCs), operational amplifiers, sampling circuits, etc.) that can both reflect their core functions and key characteristics and simplify calculations.

[0032] Step 102: Use a netlist extraction tool to extract the netlist from the first analog circuit module to obtain the target netlist file. The target netlist file includes the top-level port information of the first analog circuit module and the behavior model file corresponding to the behavior model.

[0033] In the embodiments of this application, the top-level port information refers to the list of interfaces through which the first analog circuit module interacts with the outside world, including port name, signal type (such as input or output, voltage or current), electrical characteristics (such as voltage range, driving capability), etc., which are used to clarify how the analog circuit module is connected to the external circuit and ensure that the analog circuit module can correctly interface with other modules (especially digital modules).

[0034] The behavioral model file records the functional logic of the first analog circuit module, such as the mathematical relationships between inputs and outputs and timing characteristics, rather than the low-level component connection details. The behavioral model file (SystemVerilog, a hardware description and verification language) is stored in the same folder as the schematic file of the first analog circuit module so that the netlist extraction tool can automatically identify and associate the behavioral model file.

[0035] Specifically, a netlist extraction tool (such as Virtuoso, an Electronic Design Automation (EDA) tool) is used to automatically extract the netlist for the first analog circuit module. For analog modules with established behavioral models, the netlist extraction tool does not delve into the internal circuit details (i.e., it does not analyze the component connections layer by layer), but only extracts the top-level port information of the module. The internal circuit details of the analog module are replaced by the behavioral model. The final target netlist file contains two parts of information: Top-level port information: This specifies the interface for analog circuit modules to interact with external circuits, ensuring connection compatibility with external circuits (such as digital circuit modules). Behavioral model file: also known as SystemVerilog type file, which replaces internal circuit details with functional descriptions (such as the conversion logic from input voltage to digital output) to support functional calculations during subsequent simulations.

[0036] Step 103: Based on the target netlist file, obtain the analog circuit module under test. Then, construct a digital-analog simulation verification platform based on the analog circuit module under test and the pre-determined digital circuit module under test. The digital-analog simulation verification platform is used to perform timing verification of the interaction signals between the analog circuit module under test and the digital circuit module under test.

[0037] In the embodiments of this application, the analog circuit module under test includes a non-digital logic analog circuit module and a digital logic analog circuit module. The non-digital logic analog circuit module has been replaced by a behavioral model, retaining only core behavioral characteristics (such as continuous signal processing logic) and top-level ports. The digital logic analog circuit module retains its digital control logic and interface timing. The digital circuit module under test typically exists in RTL code form (such as Verilog or SystemVerilog description), and its functional logic, interface definitions, and timing constraints have been preliminarily verified through digital simulation.

[0038] Specifically, the top-level ports of the analog circuit module under test (DUT) and the corresponding ports of the digital circuit module under test (DUT) (such as data input and control output of a digital processor) are connected according to predefined signal rules (such as bit width matching, level compatibility, and direction correspondence) to form the final Design Under Test (DUT), ensuring that signals can be correctly transmitted between the digital and analog interfaces. Based on the DUT, various verification components are integrated to build a digital-analog simulation verification platform to achieve comprehensive automated verification of the timing characteristics of the digital-analog interface interaction signals.

[0039] In summary, according to the signal timing verification method proposed in this application, a target behavioral model is obtained by performing real-valued modeling on the first analog circuit module; a netlist extraction tool is used to extract the netlist from the first analog circuit module to obtain a target netlist file containing the top-level port information of the first analog circuit module and the behavioral model file corresponding to the behavioral model; based on the target netlist file, the analog circuit module under test is obtained, and a digital simulation verification platform for timing verification of the interaction signals between the analog circuit module under test and the pre-determined digital circuit module under test is constructed according to the analog circuit module under test and the pre-determined digital circuit module under test. This process simplifies the physical details of the analog circuit and reduces the amount of computation by establishing a behavioral model through real-valued modeling of the analog circuit module, thereby effectively improving the simulation speed of timing verification of digital-analog interface interaction signals.

[0040] As one possible implementation method, Figure 2 A flowchart of the second signal timing verification method is shown. Based on the above embodiments, Figure 2 right Figure 1 Step 101 is further defined, and includes the following steps: Step 201: Perform real-number modeling on the first analog circuit module to generate an initial behavioral model.

[0041] In the embodiments of this application, the delay of the initial behavior model is relatively idealized. In order to obtain a behavior model that is more consistent with the actual circuit delay, it is necessary to inject delay information into the initial behavior model so that the behavior model is closer to the timing performance of the actual analog circuit.

[0042] Specifically, a real-number modeling approach is adopted, using continuous real-number variables to describe analog signals such as voltage, current, and time. This abstracts the functional logic of the first analog circuit module, generating an initial behavioral model that does not contain actual circuit delay information. The signals in the initial behavioral model include both analog electrical information and digital logic information. Here, the first analog circuit module refers to the non-digital logic analog circuit module.

[0043] Step 202: Obtain the delay information of the first analog circuit module using simulation tools.

[0044] In the embodiments of this application, delay information refers to the time delay characteristics of the first analog circuit module during signal processing, including transmission delay, setup time (the time required for the output signal to reach a stable state) delay, and delays related to the input signal (such as delays that may be caused by analog inputs of different amplitudes).

[0045] Specifically, simulation tools (such as SPICE simulation) are used to simulate the complete schematic diagram of the first analog circuit module (including the specific parameters and connections of components such as transistors and resistors) to obtain delay information under different process corners (i.e., extreme combinations of operating conditions that affect circuit performance). These corners may include: Process variation: fluctuations in transistor parameters during chip manufacturing (such as fast process FF (Fast NMOS FastPMOS) and slow process SS (Slow NMOS Slow PMOS)). Temperature variation: Extreme values ​​of the working environment temperature (e.g., -40℃, 25℃, 125℃); Power supply voltage fluctuation: deviation of the supply voltage (e.g., ±10% of the nominal voltage).

[0046] The simulation tool will run SPICE simulations under these different Corners to obtain delay data for the corresponding operating conditions.

[0047] It is understood that the different corners described above are merely illustrative and should not limit this application.

[0048] Step 203: Label the delay information in the initial behavior model to obtain the target behavior model.

[0049] In the embodiments of this application, delay information under different corners (such as "FF process -125℃: delay 5ns" and "SS process -25℃: delay 10ns") can be embedded into the initial behavior model in a parameterized form, so that the model can automatically call the delay parameters of the corresponding corner according to the simulation scenario, thereby obtaining a target behavior model containing actual analog circuit delay information.

[0050] Compared to the initial behavior model, the target behavior model has more accurate delay information.

[0051] In summary, this application obtains a target behavior model by performing real-number modeling on the first analog circuit module and injecting delay information. The target behavior model simplifies the physical details of the analog circuit module and has delay characteristics consistent with the actual circuit and adaptable to multiple scenarios, thereby improving the simulation speed and accuracy of subsequent digital-analog interactive signal timing verification.

[0052] As one possible implementation method, Figure 3 A flowchart of the third signal timing verification method is shown. Based on the above embodiments, Figure 3 right Figure 1 Step 102 is further defined and includes the following steps: Step 301: Use a netlist extraction tool to extract the netlist of the first analog circuit module to obtain an initial netlist file, which includes the top-level port information of the first analog circuit module.

[0053] In the embodiments of this application, for analog circuit modules with established behavioral models, netlist extraction tools (such as the EDA tool Virtuoso) will automatically extract the top-level interface of the analog circuit module, rather than extracting the netlist level by level downwards. That is, it does not delve into the internal structure of the analog circuit module to analyze the connection relationships of components such as transistors and resistors (to avoid netlist redundancy), but only focuses on the top-level port information of the module's external interaction.

[0054] The core content of the obtained initial netlist file only includes the top-level port information of the first analog circuit module, such as port name, signal direction, signal type, electrical constraints, etc. This information is the basic specification for the analog circuit module to interface with external circuits (such as digital circuit modules), ensuring that after the subsequent embedding of the behavioral model, the analog circuit module can participate in digital-analog interaction through a standardized interface.

[0055] Step 302: Add the behavior model file corresponding to the target behavior model to the initial netlist file to obtain the target netlist file.

[0056] In the embodiments of this application, the behavior model file corresponding to the target behavior model is added to the initial netlist file containing only the top-level port information of the first analog circuit module. The behavior model replaces the internal details of the actual analog circuit; that is, the functional logic of the first analog circuit module is described by SystemVerilog code, replacing the internal transistor-level physical connection details. The resulting target netlist file contains both the top-level port information of the first analog circuit module (the module can participate in analog-to-digital interaction through a standardized interface) and the behavior model file describing the functional logic of the first analog circuit module.

[0057] The core objective is to generate a standardized netlist that is compatible with mixed-signal simulation, ensuring the compatibility of analog circuit modules with external interfaces while avoiding excessive computation caused by analyzing the underlying analog circuits during simulation.

[0058] In summary, this application extracts top-level port information from the first analog circuit module and then uses a behavioral model to replace the actual analog circuit, thereby obtaining a target netlist file containing interface specifications and functional descriptions. This ensures both the interface compatibility of the module with external interfaces and simplifies the simulation complexity of the analog circuit through the behavioral model.

[0059] As one possible implementation method, Figure 4 A flowchart of the fourth signal timing verification method is shown. Based on the above embodiments, the analog circuit module under test is obtained based on the target netlist file, including the following steps: Step 401: Obtain the delay information of the second analog circuit module from the preset basic unit database, and mark the delay information in the second analog circuit module.

[0060] In the embodiments of this application, the preset basic unit database refers to the digital standard unit library (commoncell). The second analog circuit module is a digital logic analog circuit module.

[0061] The digital logic components (such as registers, logic gates, and timing controllers) within the second analog circuit module essentially belong to the category of common cells, meaning they are composed of common cells. Common cells are predefined basic digital units (such as AND gates, OR gates, and D flip-flops) in the chip manufacturing process, serving as fundamental components for digital logic design. The delay characteristics of various basic digital units within the common cell (such as gate-level delay and routing delay) have been verified through the manufacturing process and stored in a standardized database. Therefore, the delay information of the second analog circuit module can be directly retrieved from the predefined basic unit database (i.e., common cell).

[0062] Specifically, the composition of the digital logic in the second analog circuit module is analyzed, the common cell type used in the second analog circuit module (such as two D flip-flops and one AND gate) and the connection relationship (such as the output of the flip-flop being used as the input of the AND gate) are identified, the delay data of the corresponding unit is called from the common cell library (such as the clock-to-output delay of the D flip-flop being 2ns, the propagation delay of the AND gate being 1ns, and the wiring delay being 0.5ns), the total delay of the digital logic is calculated (such as the complete delay from the control signal input to the analog module trigger signal output), and the calculated total delay information is embedded in the description of the second analog circuit module in the form of timing constraints (such as marking the timing attributes in the netlist).

[0063] Step 402: Combine the second analog circuit module with the marked delay information with the target netlist file to obtain the analog circuit module under test.

[0064] In the embodiments of this application, the target netlist file includes top-level port information and behavioral model file of the first analog circuit module (non-digital logic). The target netlist file is essentially an analog circuit module of non-digital logic generated by replacing the actual analog circuit with a behavioral model.

[0065] Specifically, the second analog circuit module (digital logic) with the marked delay information is strictly aligned with the internal interface of the target netlist file (non-digital logic) (e.g., the input and output of the digital logic module and the non-digital logic module are connected, and the logic level and bit width of the signals are fully compatible). Together, they constitute a complete analog circuit function, forming the final analog circuit module under test, which is a complete unit that combines analog functional characteristics and digital timing characteristics.

[0066] The analog function layer of the analog circuit module under test retains continuous signal processing capabilities through behavioral models to support analog function verification, and has standardized top-level ports that can be directly connected to digital circuit modules; the digital timing layer injects delay information to truly reflect the transmission delay and timing constraints of digital control signals, and can support timing verification of digital-analog interaction.

[0067] In summary, this application injects delay information into the digital logic part of the analog circuit module and combines it with a target netlist file containing top-level port information and behavioral model files to form a complete analog circuit module under test that meets the requirements of mixed-signal simulation. This ensures the abstraction of the core functions of the analog module, improves the efficiency of subsequent simulation, ensures the authenticity of timing, and improves the accuracy of timing verification.

[0068] As one possible implementation, constructing a digital-to-analog simulation verification platform based on the analog circuit module under test and a pre-defined digital circuit module under test includes: combining the analog circuit module under test and the digital circuit module under test to obtain a target module under test; and combining the target module under test with pre-defined verification components to construct the digital-to-analog simulation verification platform. For example... Figure 5 As shown, Figure 5 This is a schematic diagram of the structure of a digital simulation verification platform provided in an embodiment of this application.

[0069] In the embodiments of this application, the digital circuit module under test is a module with pure digital logic function as its core. Its functional logic, interface definition, and timing constraints have been preliminarily verified by digital simulation and exist in the form of RTL code.

[0070] Reference Figure 5 The analog circuit module under test (DUT) obtained by abstracting the behavior model and injecting delay information is then logically connected with the digital circuit module under test through code (such as hardware description languages ​​like Verilog and SystemVerilog) according to a predefined standard interface specification, forming the target DUT module (i.e., the design under test).

[0071] The preset verification components include a reference model component, an excitation-driven component, a scoreboard component, an input data sampling component, an output data sampling component, and multiple time series detection modules, among which: The reference model component contains an ideal functional and performance model of the target module under test, which is used to provide reference information such as expected output results; The excitation drive component is used to inject various test excitation signals into the target module under test, simulate the input under actual working scenarios, and drive the target module under test to work. The input / output data sampling component collects the signals input to the target module under test and the signals output by the target module under test, respectively, to provide data support for subsequent verification. The scoring board component is used to receive the actual output data of the target module under test collected by the output data sampling component and the expected data of the reference model component, compare the actual output data and the expected data, and determine whether the function of the target module under test is correct. Timing detection modules are distributed at different locations on the target module under test. They are used to detect whether the timing of the target module under test, both internally and during interaction with the outside, meets the requirements, ensuring that the timing of the digital and analog parts is properly coordinated.

[0072] By integrating the target module under test with the aforementioned preset verification components, a complete digital-analog simulation verification platform is finally constructed, which is used for subsequent timing verification of the interaction signals between the analog circuit module under test and the digital circuit module under test.

[0073] As one possible implementation, after constructing the analog-to-digital circuit verification platform based on the analog circuit module under test (DUT) and a pre-defined digital circuit module under test (DUT), the platform further includes: determining the names of the interaction signals between the analog circuit module under test and the digital circuit module under test; determining the timing constraints of the interaction signals based on the interaction signal names; generating timing verification code based on the timing constraints; and embedding the timing verification code into the analog-to-digital circuit verification platform to verify the timing relationship of the interaction signals between the analog circuit module under test and the digital circuit module under test using the embedded timing verification code. Figure 6 As shown, Figure 6 This is a general flowchart of a signal timing verification method provided in an embodiment of this application.

[0074] In the embodiments of this application, after constructing the analog-to-digital interface simulation verification platform, it is necessary to generate an assertion detection program block (corresponding to the timing verification code of this application) based on the timing constraint relationship of the analog-to-digital interface interaction signals, and embed the assertion detection program block into the analog-to-digital interface simulation verification platform to complete the automated verification and simulation of the timing of the analog-to-digital interface interaction signals.

[0075] Among them, the timing constraint relationship is a timing expectation target determined in advance according to the chip design requirements. In the subsequent actual detection process of the interaction signal, it is used to determine whether the timing relationship of the interaction signal in different application scenarios is consistent with the expectation target.

[0076] Reference Figure 6 After constructing the analog-to-digital simulation verification platform, the first step is to qualitatively analyze the timing relationships of the interface signals to determine the names of the interaction signals between the analog circuit module under test (DUT) and the digital circuit module under test (DUT). This clarifies which signals are interacting. These interaction signals include: clock signal (CLK), write enable signal (WR_EN), address signal (ADDR), read enable signal (RD_EN), read latch signal (RD_LATCH), and read precharge signal (RD_PRE). Based on the interaction signal names, the timing constraints of the interaction signals are collected. For example, when the write enable signal WR_EN equals 1, the address bus ADDR must remain stable to ensure that the write operation can accurately locate the target address and avoid data writing errors.

[0077] In order for timing relationships to be recognized by tools, the timing constraints of interactive signals need to be converted into a quantized form that can be processed by the program.

[0078] Understandably, this application does not restrict the quantization method. To intuitively visualize the potential constraints between signals, facilitate the addition of constraints, and identify easily overlooked timing relationships, this application uses an Excel spreadsheet as an example for quantization, quantizing the timing constraints of the interactive signals into a timing table for quantitative analysis. Figure 7 As shown, Figure 7 This is a schematic diagram of an interactive signal timing table provided in an embodiment of this application.

[0079] Reference Figure 7 A table space represents half a clock space, and dashed lines represent signal timing; the timing relationships of a worksheet represent the usage scenario of a chip.

[0080] Timing constraints include trigger conditions, dependencies, and checks. For example, "trigger condition is CLK, dependency is WR_EN=1, check is ADDR=Stable" means that under the drive of the clock signal CLK, whenever the write enable signal WR_EN=1 (i.e., in an active state), the address signal ADDR must remain stable. This constraint aims to prevent address jumps during write operations from causing data write errors. Additionally, Figure 7 In this context, posedge represents the rising edge, negedge represents the falling edge, and #1 is used to uniquely identify specific timing behaviors (such as signal transitions, constraint triggers, etc.).

[0081] Continue to refer to Figure 6 After quantizing the timing constraints of the interactive signals into a timing table, an assertion detection block (corresponding to the timing verification code in this application) needs to be generated based on the timing table to perform timing verification of the interactive signals using an embedded digital simulation verification platform. The assertion detection block can be generated using a Python script, with the timing table as input. The Python script can automatically generate the assertion detection block by recognizing the information in the timing table. The execution logic of the Python script is as follows: 1) Automatically identify key timing information such as clock edge (rising edge / falling edge) and signal level (high / low) through the dotted lines in the table.

[0082] 2) For constraints marked with special annotations in the table (such as custom timing intervals), generate corresponding assertion logic according to preset timing constraint rules.

[0083] 3) Based on tables, generate all required assertion blocks in batches for multiple scenarios and constraints.

[0084] 4) The script and assertion block can be debugged in a loop until they fully match the timing requirements of the design under test.

[0085] The assertion detection block generated by the script is embedded into the numerical simulation verification platform for regression simulation, allowing the target module under test to run under stimulus. At this time, the embedded assertion block will detect timing constraints in real time.

[0086] If an assertion reports an error, it indicates a timing violation in the digital-analog circuit (such as a signal interval of less than one cycle) or an assertion logic error (such as an incorrect table rule). The circuit design needs to be checked or the assertions adjusted.

[0087] If the assertion does not report an error, iterative optimization can be performed, such as adding qualitative timing analysis of new interaction signals, or increasing the number of regression stimuli (i.e., signals / data input to the target module under test). Then, effective assertion detection program blocks can be repeatedly generated and embedded into the digital-analog simulation verification platform to continue simulation, forming positive feedback and efficiently checking the timing of digital-analog interface interaction signals.

[0088] In summary, this application constructs a digital-analog interface simulation verification platform. Based on the timing constraints of the digital-analog interface interaction signals, it uses scripts to automatically generate timing verification code and embeds it into the digital-analog interface simulation verification platform to perform timing verification of the interaction signals. This process can fully detect the timing of the digital-analog interface interaction signals, thereby effectively improving the completeness of the interface timing verification.

[0089] To implement the above embodiments, this application also provides a signal timing verification device. Figure 8 This is a schematic diagram of a signal timing verification device 800 provided in an embodiment of this application. Figure 8 As shown, the device includes: Real-number modeling unit 810 is used to perform real-number modeling on the first analog circuit module to obtain a target behavior model. The target behavior model includes signals carrying analog electrical information and digital logic information, and the analog electrical information and digital logic information are associated. Extraction unit 820 is used to extract the netlist of the first analog circuit module using a netlist extraction tool to obtain a target netlist file. The target netlist file includes the top-level port information of the first analog circuit module and the behavior model file corresponding to the target behavior model. The construction unit 830 is used to obtain the analog circuit module under test based on the target netlist file, and to construct a digital simulation verification platform based on the analog circuit module under test and the pre-determined digital circuit module under test. The digital simulation verification platform is used to perform timing verification of the interaction signals between the analog circuit module under test and the digital circuit module under test.

[0090] In some embodiments of this application, the real number modeling unit 810 is used to: perform real number modeling on the first analog circuit module to generate an initial behavior model; obtain the delay information of the first analog circuit module through a simulation tool; and annotate the delay information in the initial behavior model to obtain a target behavior model.

[0091] In some embodiments of this application, the extraction unit 820 is used to: extract the netlist of the first analog circuit module using a netlist extraction tool to obtain an initial netlist file, the initial netlist file including the top-level port information of the first analog circuit module; and add the behavior model file corresponding to the target behavior model to the initial netlist file to obtain the target netlist file.

[0092] In some embodiments of this application, the construction unit 830 is used to: obtain delay information of the second analog circuit module from a preset basic unit database, and mark the delay information in the second analog circuit module; combine the second analog circuit module marked with delay information with the target netlist file to obtain the analog circuit module under test.

[0093] In some embodiments of this application, the construction unit 830 is used to: combine the analog circuit module under test and the digital circuit module under test to obtain the target module under test; and combine the target module under test with a preset verification component to construct a digital-analog simulation verification platform.

[0094] In some embodiments of this application, the construction unit 830 is configured to: determine the names of the interaction signals between the analog circuit module under test and the digital circuit module under test; determine the timing constraints of the interaction signals based on the interaction signal names; generate timing verification code according to the timing constraints, and embed the timing verification code into the digital simulation verification platform, so as to use the digital simulation verification platform with embedded timing verification code to verify the timing relationship of the interaction signals between the analog circuit module under test and the digital circuit module under test.

[0095] Since the apparatus provided in this application corresponds to the methods provided in the above-mentioned embodiments, the implementation of the methods is also applicable to the apparatus provided in this embodiment, and will not be described in detail in this embodiment.

[0096] The methods and apparatus provided in the embodiments of this application have been described above. To implement the functions of the methods provided in the embodiments of this application, the electronic device may include a hardware structure and software modules, and may implement the above functions in the form of a hardware structure, software modules, or a hardware structure plus software modules. One of the above functions may be executed in the form of a hardware structure, software modules, or a hardware structure plus software modules.

[0097] Figure 9 This is a block diagram illustrating an electronic device 900 for implementing the above-described signal timing verification method, according to an exemplary embodiment. For example, the electronic device 900 may be a mobile phone, computer, messaging device, game console, tablet device, medical device, fitness equipment, personal digital assistant, etc.

[0098] Reference Figure 9The electronic device 900 may include one or more of the following components: a processing component 902, a memory 904, a power supply component 906, a multimedia component 908, an audio component 910, an input / output (I / O) interface 912, a sensor component 914, and a communication component 916.

[0099] Processing component 902 typically controls the overall operation of electronic device 900, such as operations associated with display, telephone calls, data communication, camera operation, and recording operations. Processing component 902 may include one or more processors 920 to execute instructions to perform all or part of the steps of the methods described above. Furthermore, processing component 902 may include one or more modules to facilitate interaction between processing component 902 and other components. For example, processing component 902 may include a multimedia module to facilitate interaction between multimedia component 908 and processing component 902.

[0100] Memory 904 is configured to store various types of data to support the operation of electronic device 900. Examples of this data include instructions for any application or method operating on electronic device 900, contact data, phonebook data, messages, pictures, videos, etc. Memory 904 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0101] Power supply component 906 provides power to various components of electronic device 900. Power supply component 906 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 900.

[0102] Multimedia component 908 includes a screen that provides an output interface between electronic device 900 and user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may sense not only the boundaries of touch or swipe actions but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 908 includes a front-facing camera and / or a rear-facing camera. When electronic device 900 is in an operating mode, such as a shooting mode or video mode, the front-facing camera and / or rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0103] Audio component 910 is configured to output and / or input audio signals. For example, audio component 910 includes a microphone (MIC) configured to receive external audio signals when electronic device 900 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 904 or transmitted via communication component 916. In some embodiments, audio component 910 also includes a speaker for outputting audio signals.

[0104] I / O interface 912 provides an interface between processing component 902 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0105] Sensor assembly 914 includes one or more sensors for providing state assessments of various aspects of electronic device 900. For example, sensor assembly 914 may detect the on / off state of electronic device 900, the relative positioning of components such as the display and keypad of electronic device 900, changes in position of electronic device 900 or a component of electronic device 900, the presence or absence of user contact with electronic device 900, orientation or acceleration / deceleration of electronic device 900, and temperature changes of electronic device 900. Sensor assembly 914 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 914 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 914 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor.

[0106] Communication component 916 is configured to facilitate wired or wireless communication between electronic device 900 and other devices. Electronic device 900 can access wireless networks based on communication standards, such as WiFi, 2G or 3G, 4G LTE, 5G NR (NewRadio), or combinations thereof. In one exemplary embodiment, communication component 916 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 916 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0107] In an exemplary embodiment, the electronic device 900 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the methods described above.

[0108] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 904 including instructions, which can be executed by a processor 920 of an electronic device 900 to perform the above-described method. For example, the non-transitory computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0109] Embodiments of this application also propose a chip, such as Figure 10 As shown, the chip includes one or more interface circuits 1001 and one or more processors 1002; the interface circuits are used to receive signals from the memory of the electronic device and send signals to the processors, the signals including computer instructions stored in the memory, and when the processor executes the computer instructions, the electronic device executes the signal timing verification method described in the above embodiments of this application.

[0110] Embodiments of this application also propose a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause a computer to execute the signal timing verification method described in the above embodiments of this application.

[0111] Embodiments of this application also propose a computer program product, including a computer program that is executed by a processor using the signal timing verification method described in the above embodiments of this application.

[0112] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0113] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0114] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of the preferred embodiments of the invention includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as will be understood by those skilled in the art to which embodiments of the invention pertain.

[0115] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processing module, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (control method), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic device, and portable optical disc read-only memory (CDROM). Furthermore, computer-readable media can even be paper or other suitable media on which programs can be printed, because programs can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpreting, or otherwise processing as necessary, and then stored in computer memory.

[0116] It should be understood that various parts of the embodiments of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0117] Those skilled in the art will understand that all or part of the steps of the methods described in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

[0118] Furthermore, the functional units in the various embodiments of the present invention can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc.

[0119] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A signal timing verification method, characterized in that, The method includes: Real-number modeling is performed on the first analog circuit module to obtain a target behavior model. The target behavior model includes signals carrying analog electrical information and digital logic information, and the analog electrical information and the digital logic information are associated. The netlist extraction tool is used to extract the netlist from the first analog circuit module to obtain the target netlist file. The target netlist file includes the top-level port information of the first analog circuit module and the behavior model file corresponding to the target behavior model. Based on the target netlist file, an analog circuit module under test is obtained. A digital circuit simulation verification platform is constructed based on the analog circuit module under test and a pre-determined digital circuit module under test. The digital circuit simulation verification platform is used to perform timing verification on the interaction signals between the analog circuit module under test and the digital circuit module under test.

2. The method according to claim 1, characterized in that, The real-number modeling of the first analog circuit module to obtain the target behavior model includes: Perform real-number modeling on the first analog circuit module to generate an initial behavior model; The delay information of the first analog circuit module is obtained using simulation tools; The delay information is annotated in the initial behavior model to obtain the target behavior model.

3. The method according to claim 1, characterized in that, The step of using a netlist extraction tool to extract the netlist from the first analog circuit module to obtain the target netlist file includes: The netlist of the first analog circuit module is extracted using a netlist extraction tool to obtain an initial netlist file, which includes the top-level port information of the first analog circuit module. The behavior model file corresponding to the target behavior model is added to the initial netlist file to obtain the target netlist file.

4. The method according to claim 1, characterized in that, The process of obtaining the analog circuit module under test based on the target netlist file includes: The delay information of the second analog circuit module is obtained from the preset basic unit database, and the delay information is marked in the second analog circuit module; The second analog circuit module with labeled delay information is combined with the target netlist file to obtain the analog circuit module under test.

5. The method according to claim 1, characterized in that, The construction of the digital-to-analog circuit simulation verification platform based on the analog circuit module under test and the pre-set digital circuit module under test includes: The analog circuit module under test and the digital circuit module under test are combined to obtain the target module under test; The target module to be tested is combined with a preset verification component to construct the digital simulation verification platform.

6. The method according to claim 1, characterized in that, The method involves constructing a digital-to-analog simulation verification platform based on the analog circuit module under test and a pre-defined digital circuit module under test. The method then includes: Determine the names of the interaction signals between the analog circuit module under test and the digital circuit module under test; Based on the name of the interaction signal, determine the timing constraint relationship of the interaction signal; Based on the timing constraints, timing verification code is generated and embedded into the digital simulation verification platform to verify the timing relationship of the interaction signals between the analog circuit module under test and the digital circuit module under test.

7. A signal timing verification device, characterized in that, The device includes: A real-number modeling unit is used to perform real-number modeling on the first analog circuit module to obtain a target behavior model. The target behavior model includes signals carrying analog electrical information and digital logic information, and the analog electrical information and the digital logic information are associated. The extraction unit is used to extract the netlist from the first analog circuit module using a netlist extraction tool to obtain a target netlist file. The target netlist file includes the top-level port information of the first analog circuit module and the behavior model file corresponding to the target behavior model. The construction unit is used to obtain the analog circuit module under test based on the target netlist file, and to construct a digital simulation verification platform based on the analog circuit module under test and the predetermined digital circuit module under test. The digital simulation verification platform is used to perform timing verification on the interaction signals between the analog circuit module under test and the digital circuit module under test.

8. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-6.

9. A chip, characterized in that, The device includes one or more interface circuits and one or more processors; the interface circuits are configured to receive signals from the memory of the electronic device and send the signals to the processors, the signals including computer instructions stored in the memory, which, when executed by the processors, cause the electronic device to perform the method of any one of claims 1-6.

10. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the method according to any one of claims 1-6.

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