Design parameter verification method and system of stacked package chip, terminal and medium

Abstract

The invention provides a design parameter verification method and system for a stacked package chip, a terminal and a medium, and belongs to the technical field of stacked package chips, and the method comprises the steps of receiving a design request and extracting multi-dimensional parameter information, and establishing a verification item system. And managing each verification item by adopting a unique identifier, determining the item meeting an innovative verification condition as a target verification item through intelligent matching judgment, and executing a corresponding rule. The system can automatically identify and process a parameter coupling relationship, finally extract a multi-dimensional coupling parameter set and generate a verification result containing synergistic effect analysis and optimization suggestions. Full-dimension automatic verification is realized, and verification efficiency and accuracy are improved; the problem of multi-physics field coupling is effectively solved, and design blind areas are reduced; verification of design requirements such as asymmetric stacking and impedance compensation is supported; and a system-level performance view angle and a quantitative optimization basis are provided, and the design of an iteration period is accelerated.

Description

Technical Field

[0001] This invention belongs to the field of stacked packaged chip technology, specifically relating to a method, system, terminal, and medium for verifying design parameters of stacked packaged chips. Background Technology

[0002] As semiconductor technology advances towards higher integration and smaller dimensions, traditional two-dimensional (2D) packaging technology faces challenges due to its physical limitations. In 2D packaging, chips are laid flat on a substrate and electrically connected via wire bonding or flip-chip bonding. However, with the shrinking chip size and increasing functional complexity, the increased interconnect length leads to signal delay and power consumption, while thermal management efficiency is low. Furthermore, 2D packaging struggles to meet the high bandwidth and low power consumption requirements of fields such as high-performance computing (HPC), artificial intelligence (AI), and 5G communications.

[0003] As a 3D chip stacking packaging technology, 3D stacking achieves high-density integration between chips by vertically stacking multiple chips and utilizing advanced interconnect technologies such as through-silicon vias (TSVs), redistribution layers (RDLs), and microbumps. Compared to 2D packaging, 3D stacking significantly shortens the signal transmission path, reduces latency and power consumption, and improves packaging density through vertical space optimization.

[0004] When performing design verification for stacked packaged chips, design parameters are typically tested based on a uniform stress threshold. This makes the verification process unsuitable for complex design scenarios, such as ultra-thin chips which require stricter stress control, leading to a disconnect between verification results and actual needs. Verification also fails to include innovative parameters such as asymmetric stacking and quantum tunneling effects, resulting in designs that cannot meet high-performance and high-integration requirements. Furthermore, verification results provide only a pass / fail judgment, lacking synergy analysis, and design optimization relies heavily on engineer experience, making it subjective and inefficient. Summary of the Invention

[0005] This invention provides a method for verifying design parameters of stacked packaged chips, which improves the comprehensiveness of verification and avoids omissions caused by parameter coupling; and improves design optimization efficiency through dynamic threshold and synergy effect analysis.

[0006] The methods include: S101: Receive design parameter verification request for stacked packaged chips; S102: The physical structure parameters involved in the design process of stacked packaged chips are used as chip verification items, and a unique verification identifier is assigned to each chip verification item. S103: Determine whether the verification identifier of each chip to be verified matches the stacked package chip design parameters extracted in step S101 under the preset verification conditions. S104: If the judgment result of S103 is yes, then the corresponding chip to be verified item is determined as the target chip verification item, and the verification rules of the target chip verification item are executed. S105: If the judgment result of step S103 is no, then determine whether there are other chip verification items associated with the chip to be verified. Other chip verification items associated with the chip are verification items that have parameter coupling relationship with the current chip to be verified. S106: If the judgment result of step S105 is yes, then the other related chip verification items are taken as new chip verification items and the process returns to step S103. S107: After completing the execution of the verification rules for all target chip verification items, extract the multi-dimensional coupling parameter set and the corresponding target package chip design information from the execution results; S108: Based on the extracted target package chip design information, update the preset chip design verification result template, and use the updated template as design parameters to request the corresponding verification result.

[0007] This application also provides a design parameter verification system for stacked packaged chips, the system comprising: The design request parsing module is used to receive design parameter verification requests for stacked packaged chips. The verification item initialization module is used to take the physical structure parameter verification involved in the stacked package chip design process as the chip verification items and assign a unique verification identifier to each chip verification item. The verification condition matching module is used to determine whether the verification identifier of each chip to be verified matches the extracted stacked package chip design parameters under preset verification conditions. The target verification determination module is used to determine the corresponding chip verification item as the target chip verification item if the judgment result is yes, and to execute the verification rules of the target chip verification item. The associated verification module is used to determine whether there are other associated chip verification items if the judgment result is negative. Other associated chip verification items are verification items that have parameter coupling relationship with the current verification item. The associated verification module is used to treat other associated chip verification items as new chip verification items if the judgment result is yes. The multi-dimensional parameter extraction module is used to extract the multi-dimensional coupling parameter set and the corresponding target package chip design information from the execution results after the execution of the verification rules for all target chip verification items are completed. The verification result integration module is used to update the preset chip design verification result template based on the extracted target package chip design information, and use the updated template as design parameters to request the corresponding verification results.

[0008] According to another embodiment of this application, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of the design parameter verification method for the stacked packaged chip.

[0009] According to another embodiment of this application, a storage medium is also provided, on which a computer program is stored, wherein when the computer program is executed by a processor, the steps of the design parameter verification method for the stacked packaged chip are implemented.

[0010] As can be seen from the above technical solutions, the present invention has the following advantages: The design parameter verification method for stacked packaged chips involved in this application extracts application scenario information, adjusts verification condition thresholds, and updates scenario-based verification templates, enabling customized verification standards for different environments. Verification items are broken down into six dimensions, including physical structure and electrical connections, and are graded to prioritize ensuring key chip design performance; related items are traced to avoid missing coupling parameters during verification, ensuring that verification covers the entire process.

[0011] By identifying the coupling relationships of labeled parameters, multidimensional coupling parameters are extracted, and synergistic effects are analyzed. Coupling correlations reveal that interlayer stress can exceed limits due to poor heat dissipation, allowing for proactive optimization and preventing chip cracking during subsequent use. Abnormal parameters are correlated and traced, providing source-guided adjustment suggestions and correlation parameter-performance predictions to clarify optimization directions. Template thresholds are updated based on measured data, and a version control system records iteration history to ensure that verification standards consistently align with actual technical capabilities. Attached Figure Description

[0012] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the description will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 Flowchart of design parameter verification method for stacked packaged chips; Figure 2 Schematic diagram of a design parameter verification system for stacked packaged chips; Figure 3 This is a schematic diagram of an electronic device. Detailed Implementation

[0014] The following describes in detail the design parameter verification method for stacked packaged chips involved in this application. Specific details such as particular system structures and technologies are presented for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application can also be implemented in other embodiments without these specific details.

[0015] It should be understood that, when used in this specification, terms include indicating the presence of a described feature, integral, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or collections thereof. The terms include, encompass, have, and variations thereof mean including but not limited to, unless otherwise specifically emphasized.

[0016] The statements such as "one embodiment" or "some embodiments" described in this application mean that one or more embodiments of this application include the specific features, structures, or characteristics described in that embodiment. Therefore, the statements such as "in one embodiment," "in some embodiments," "in other embodiments," and "in still other embodiments" in this application do not necessarily refer to the same embodiment, but rather mean one or more, but not all, embodiments, unless otherwise specifically emphasized.

[0017] In embodiments of the present invention, computer program code for performing the operations of this disclosure can be written in one or more programming languages ​​or a combination thereof. These programming languages ​​include, but are not limited to, object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (exemplarily using an Internet service provider for Internet connection).

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] Please see Figure 1The diagram shows a flowchart of a design parameter verification method for stacked packaged chips in a specific embodiment. The method includes: Step S101: Receive the design parameter request for the stacked packaged chip, and extract the physical structure, electrical connection, thermal management, material compatibility, manufacturing process, and reliability design parameters of the stacked packaged chip contained in the request.

[0020] In some embodiments, step S101 receives a stacked package chip design parameter request submitted by the designer. The request may be in the form of a document, a data table, or a parameter file uploaded by the system. The extracted information needs to cover the key dimensions of the entire life cycle of the chip design. The specific sub-parameters are as follows: physical structure information includes 2 to 8 chip layers, interlayer spacing of 5 μm to 50 μm, substrate thickness of 0.1 mm to 0.5 mm, and asymmetric stacking structure layout.

[0021] Electrical connection information includes via diameter, wiring density, and signal transmission rate; thermal management information includes thermal interface material type, pore size and distribution density of heat dissipation channels, and maximum power consumption of the chip; material compatibility information includes the coefficient of thermal expansion of each layer of chip substrate, substrate material, and encapsulating colloid; manufacturing process information includes mounting pressure, reflow temperature profile, and plasma cleaning time.

[0022] In this embodiment, by parsing and extracting contextual information, the verification is made more relevant to actual application scenarios. For example, by deriving the ultraviolet resistance requirements for outdoor scenarios, the anti-aging performance of the encapsulating colloid can be specifically verified. Each verification item provides clear parameter basis, avoiding subjective judgment bias caused by ambiguous parameters in subsequent verification and improving the objectivity of verification.

[0023] Step S102: The physical structure parameters involved in the design process of the stacked packaged chip are used as chip verification items, and a unique verification identifier is assigned to each chip verification item.

[0024] In some embodiments, the items to be verified are physical structure parameter verifications, including whether the interlayer stress under different combinations of the number of layers in an asymmetric stacked structure exceeds the material tolerance value, and the matching between the interlayer spacing and the chip size.

[0025] Optionally, physical structure parameter verification can be performed by extracting physical structure parameters from the design parameter request, including but not limited to: the number of stacked layers and the chip type of each layer, the interlayer spacing and tolerance range, the chip size of each layer, and the substrate thickness. Asymmetric structural features may involve stacking combinations of chips of different sizes and gradient thickness substrate designs. Physical interfaces involve bump distribution density, via location, and diameter.

[0026] Based on pre-defined general design specifications, verify whether the basic parameters meet the minimum requirements. Determine whether the number of stacking layers is within the allowable range of the target application scenario, avoiding a surge in inter-layer alignment difficulty due to excessive layers.

[0027] The method of dimensional tolerance verification is based on checking whether the tolerance of interlayer spacing and chip thickness is within the range allowed by the manufacturing process. For example, if the interlayer spacing tolerance is ≤±1μm, exceeding it may lead to bonding failure.

[0028] Asymmetric structure coverage verification verifies whether the design contains asymmetric stacking features. If it is a symmetric structure, it is necessary to evaluate whether it meets the requirements for heat dissipation or functional integration.

[0029] For asymmetric stacked structures, the overall center of gravity offset is calculated based on the mass and position of each chip layer. Edge alignment errors of chips of different sizes are detected; for example, edge misalignment ≤20μm may lead to uneven encapsulation coverage, affecting moisture resistance. The system also determines whether the asymmetric layout conflicts with other physical features.

[0030] This embodiment can also construct a mechanical model of the physical structure using finite element analysis (FEA) software to simulate stress distribution under temperature cycling and vibration impact. It can also be combined with manufacturing process capabilities to verify the feasibility of the physical structure parameters. It determines whether the interlayer spacing is compatible with the bonding technology. If vertical interconnect vias exist, the ratio of the via diameter to the interlayer spacing needs to be verified.

[0031] If any parameters fail to meet the standards during the verification process, an abnormal situation will be displayed, and a physical structure parameter verification report will be generated to provide quantitative and traceable verification basis for the structural design of stacked packaged chips.

[0032] This embodiment can assign a unique verification identifier, with the identifier encoding rules being scene code, project category code, priority code, and sequence number. Based on the standard that the frequency of two projects simultaneously exhibiting abnormal parameters is ≥30% in historical verification data, six types of projects are labeled and coupled.

[0033] This embodiment clearly defines the scope and specific targets of verification, and quickly distinguishes project attributes through identification codes, thereby improving verification efficiency. The coupled association markers provide a basis for subsequent verification priority ranking and collaborative judgment.

[0034] Step S103: Determine whether the verification identifier of each chip to be verified matches the stacked package chip design parameters extracted in step S101 according to the preset verification conditions. The verification conditions include: physical structure parameters must cover asymmetric stacked structures; electrical connection parameters must include dynamic impedance compensation methods; thermal management parameters must involve interlayer thermal coupling coefficients; material compatibility parameters must cover gradient transition material combinations; manufacturing process parameters must be associated with a dynamic yield model; and reliability parameters must be configured with an accelerated aging factor.

[0035] In some embodiments, the preset verification conditions are refined and adjusted according to specific scenarios: the asymmetric stacking structure coverage configuration condition for physical structure parameters is that it includes at least two different sizes or different functions of chip stacks, and other conditions are that the interlayer spacing error is ≤ ±1μm; the core condition for the dynamic impedance compensation method of electrical connection parameters is that it has a module that automatically adjusts the terminal matching resistor according to the signal frequency, and the secondary condition is that the impedance adjustment response time is ≤10ns; the core condition for the interlayer thermal coupling coefficient of thermal management parameters is that it must include the calculation or test data of the coefficient, and the scenario-specific threshold; the core condition for the gradient transition material combination of material compatibility parameters is that the CTE difference between adjacent materials is ≤5ppm / ℃, and the secondary condition is that the number of transition material layers is ≥2 layers; the core condition for the dynamic yield model of manufacturing process parameters is that the model must correlate the relationship between mounting pressure, reflow temperature and yield, and the secondary condition is that the model prediction yield deviation is ≤ ±3%; the core condition for the accelerated aging factor of reliability parameters is that the factor value is ≥1.2, and the secondary condition is that the aging test cycle is ≤1 / 3 of the conventional test cycle. When making a judgment, the core conditions are verified first. If the core conditions are not met, a mismatch is directly determined. If the core conditions are met, but the secondary conditions are not met or some parameters are missing in the extracted information, information completion is initiated.

[0036] Optionally, default values ​​can be retrieved from the industry standard library, and matching parameters can be retrieved from the historical case library of similar scenarios. After completion, the judgment is made again. Combined with the coupling association mark of S102, if the core conditions of the project to be verified partially match, but the core conditions of the strongly coupled project completely match, it is temporarily set as a match to be completed, rather than directly judging it as a mismatch.

[0037] As can be seen, the scenario-based threshold adjustment in this embodiment makes the verification more closely match actual usage needs, avoiding over-verification caused by a uniform threshold. The primary and secondary hierarchical judgment reduces false positives, allowing for completion before judgment and improving verification accuracy.

[0038] Step S104: If the judgment result of S103 is yes, then the corresponding chip to be verified item is determined as the target chip verification item, and the verification rules of the target chip verification item are executed.

[0039] It should be noted that the physical structure parameter verification rules include simulating the stress distribution of different layer combinations through finite element analysis; the electrical connection parameter verification rules include measuring signal transmission delay using the time-domain reflectometry method and automatically adjusting the terminal matching resistance; the thermal management parameter verification rules include obtaining the three-dimensional temperature field distribution and quantifying the interlayer heat superposition effect through infrared thermal imaging; the material compatibility parameter verification rules include testing the interface bonding strength using a nanoindenter; the manufacturing process parameter verification rules include collecting real-time data through an online monitoring system and realizing closed-loop feedback control; and the reliability parameter verification rules include detecting delamination defects using an acoustic microscope and shortening the test cycle by adjusting the stress amplitude and the number of cycles.

[0040] In some embodiments, specific verification rules for each target item are defined: the verification rules for physical structural parameters are finite element analysis and physical sampling tests. The interlayer stress distribution under different combinations of layers is simulated using finite element software. The stress concentration areas of asymmetric stacking, such as corners, can be simulated in particular, and stress cloud maps are output. At the same time, 3-5 samples are sampled, and the actual interlayer stress is measured using a stress tester. The simulated values ​​are compared with the measured values. If the deviation exceeds the tolerance, the material parameters of the finite element model are corrected.

[0041] The electrical connection parameter verification rules in this embodiment are time-domain reflectometry and impedance adjustment. The signal transmission delay is measured using a TDR tester. If the delay exceeds the tolerance, the dynamic impedance compensation method is activated: the terminal matching resistor is adjusted according to the measured delay value, and the measurement is repeated until the delay meets the standard. The thermal management parameter verification rules are infrared thermal imaging and interlayer thermal coupling coefficient calculation. The three-dimensional temperature field distribution of the chip is obtained using an infrared thermal imager, and the interlayer thermal coupling coefficient is calculated through the temperature field data to determine whether it meets the scene threshold.

[0042] The material compatibility parameter verification rule in this embodiment is nanoindentation test and CTE matching calculation. The interface bonding strength of each layer of material is tested with a nanoindenter, the CTE of each material is measured with a thermal expansion meter, and the CTE difference between adjacent materials is calculated. If the difference exceeds the tolerance, a gradient transition material is recommended.

[0043] The manufacturing process parameter verification rules in this embodiment are online monitoring and yield verification. The online process monitoring system collects the mounting pressure, reflow temperature and plasma cleaning time in real time, inputs the data into the dynamic yield model to predict the yield, and samples 100 samples for mass production simulation. The deviation between the measured yield and the predicted yield must be ≤±2%.

[0044] The reliability parameter verification rules in this embodiment are accelerated aging test and acoustic microscopy inspection. The test conditions are set with an accelerated aging factor of 1.5. After the test, the chip delamination defect is detected using an acoustic microscope. If defects are found, the cause of failure is analyzed and the materials are adjusted. During the execution process, the test data, adjustment process and results of each step are recorded to form a verification log.

[0045] As can be seen, this embodiment focuses on improving resource utilization through verification and avoiding invalid verification of mismatched items; the verification rules based on the combination of simulation and physical objects ensure the reliability of the results and avoid theoretical compliance but actual non-compliance caused by relying solely on simulation, thereby improving design efficiency.

[0046] Step S105: If the judgment result of step S103 is negative, then determine whether there are other chip verification items associated with the chip to be verified. The other chip verification items associated with the chip are verification items that have parameter coupling relationships with the current chip to be verified.

[0047] In some embodiments, the judgment criteria based on other chip verification items are as follows: based on the coupling association mark of S102, if the coupling strength between the item to be verified and a certain item is strong or medium, and the parameter change of the item will directly affect the parameter of the item to be verified, then it is determined to be an associated item; in specific judgment, it is necessary to retrieve the historical verification database and check the abnormal association records of the parameters of the two items.

[0048] In this embodiment, during the judgment process, all coupled and related items of the item to be verified need to be checked one by one to clarify the association type (strong / medium / weak) and the direction of influence.

[0049] For example, the via diameter in the electrical connection parameters and the interlayer spacing in the physical structure parameters are strongly coupled. If the via diameter increases, the interlayer spacing needs to increase synchronously. Therefore, the direction of influence is that the electrical connection affects the physical structure. At the same time, the judgment result of the related items in S103 is recorded to provide a basis for subsequent steps.

[0050] This embodiment clearly defines the correlation and direction of influence, providing a clear path for subsequent adjustments. Knowing that the via diameter affects the interlayer spacing, the interlayer spacing can be optimized by adjusting the via diameter, thus improving the targeting of design optimization.

[0051] Step S106: If the judgment result of step S105 is yes, then the other associated chip verification items are taken as new chip verification items and the process returns to step S103.

[0052] In some embodiments, the new chip verification item is preprocessed: if the associated item has been determined to be a match in S103, the coupling influence data between the item and the original verification item is supplemented as a supplementary basis for re-judgment in S103; if the associated item has not been determined in S103, a new verification identifier is assigned to it.

[0053] Optionally, following the coding rules of S102, the priority is the same as or one level higher than the original item to be verified. For example, if the original item is at level 2, the associated item is set to level 1. Here, the associated item parameters in S101 can be extracted. After returning to S103, the new chip to be verified item is judged first. When judging, the focus is on whether the associated item parameters can be adjusted to make the original item to be verified meet the conditions. For example, if the interlayer stress of the original item to be verified is out of tolerance, and the thermal coupling coefficient of the new associated item meets the standard, and if the thermal coupling coefficient is increased by 0.2W / (m•K) to reduce the interlayer stress to the qualified value, then the original item to be verified is determined to need to be completed and matched, and the parameter adjustment of the associated item is incorporated into the subsequent verification rules. This embodiment records the source of the new item to be verified, forming a verification link to ensure traceability.

[0054] Step S107: After executing the verification rules for all target chip verification items, extract the multi-dimensional coupling parameter set and the corresponding target package chip design information from the execution results.

[0055] In some embodiments, specific extraction criteria and quantification methods for multidimensional coupling parameters are determined. The interlayer thermal conductivity coefficient is calculated by measuring the heat flux density using a heat flow meter and the temperature difference measured by infrared thermography. The electrical signal synchronization deviation is determined by synchronously acquiring the rise time difference of multi-channel signals using an oscilloscope. The mechanical stress distribution field is obtained by extracting the maximum stress value of key areas from the stress cloud map of finite element analysis. The quantum tunneling effect index is calculated by calculating the ratio of tunneling current to forward current using current-voltage testing. The material interface compatibility factor is calculated by multiplying the CTE difference by the interface bonding strength. The power fluctuation tolerance is measured by a power meter to determine the ratio of the power difference between full load and no-load to the rated power. The phonon propagation path integrity is determined by detecting the phonon scattering intensity using a Raman spectrometer.

[0056] During extraction, it is necessary to associate the scene adaptation level and coupling association marker of each parameter; extract the corresponding target package chip design information, including the final determined physical structure, electrical connection scheme, thermal management scheme, material combination, manufacturing process parameters, and reliability test results.

[0057] This embodiment traces the extracted abnormal parameters back to their strongly coupled parameters and identifies the root causes of the anomalies. For parameters that meet the standards, it identifies the criteria for compliance.

[0058] This embodiment extracts tags that reflect chip performance, scene adaptation level, and coupling association, improving the template's relevance and accuracy. It also associates design information so that subsequent verification result templates can directly correspond to specific design schemes, thus enhancing the template's practicality.

[0059] Step S108: Based on the extracted target package chip design information, update the preset chip design verification result template. The template includes the pass threshold for each verification item, the multi-dimensional parameter synergy effect analysis results, and parameter adjustment suggestions. Use the updated template as the verification result corresponding to the design parameter request.

[0060] In some embodiments, this embodiment explicitly defines the initial structure of the preset template, including the following: The scenario information section includes the application scenario, design model, and verification date; The verification project summary column includes the project name, identifier, judgment result, and measured parameters; The qualified threshold section includes general thresholds, scenario thresholds, and threshold basis; The Synergy Analysis section includes a parameter coupling correlation table and a description of synergy effects. The parameter adjustment suggestion section includes abnormal parameters, adjustment plans, and predicted effects after adjustment. The attachments section includes verification logs, test reports, and finite element models.

[0061] During updates, in the "Qualified Threshold" column, the scene thresholds are adjusted based on the design information and scene adaptation level extracted from S107. For parameters that do not meet the standards, traceability guidance suggestions are provided in the "Adjustment Suggestion" column: Abnormal Parameters. After updates, the consistency of template relationships is verified, update records are marked, a template version is generated, and stored in the template library. Template updates are based on actual verification data, improving the accuracy and usability of the templates. Scene-based thresholds and traceability guidance suggestions enable the templates to directly guide the verification and optimization of similar designs.

[0062] In one embodiment of the present invention, based on step S101, the following will provide a possible embodiment and its specific implementation will be described in a non-limiting manner. Step S101 further includes the following steps: Step S1011: When receiving a request for stacked packaged chip design parameters, obtain the context information associated with the request, including the designer's historical operation records, the index of the failure case library of similar products, and the performance fluctuation range of supply chain materials. Transform unstructured text information into structured parameter constraints through dynamic semantic parsing technology.

[0063] Step S1012: When extracting the physical structure parameters from the request, an asymmetric stacking structure feature recognition algorithm is used to detect whether parameters such as the number of layers, spacing, and substrate thickness contain unconventional combinations. For example, a hybrid configuration of odd-numbered layer stacking and gradient thickness substrates is used, and a preliminary structural feasibility assessment report is generated.

[0064] Step S1013: When analyzing electrical connection parameters, a dynamic mapping model of electrical signal synchronization deviation is established. Parameters such as via diameter and wiring density are associated with performance indicators such as signal transmission delay and crosstalk noise. The rationality of the parameters is quantified by the deviation between the measured data and the theoretical model using the time-domain reflection method.

[0065] Step S1014: When processing thermal management parameters, configure the quantum tunneling effect index as a correction factor for the heat conduction path, combine the thermal conductivity of the thermal interface material with the heat dissipation channel layout, construct a three-dimensional heat flux density distribution cloud map, identify local hot spots and calculate the thermal stress concentration factor.

[0066] Step S1015: When integrating material compatibility parameters, construct a multi-dimensional evaluation matrix of material interface compatibility factors, and weight and fuse parameters such as thermal expansion coefficient, elastic modulus, and chemical bonding strength of each layer of material to generate a quantitative score of material cooperative deformation capability.

[0067] Step S101 of this embodiment is based on parameter correlation analysis and multi-dimensional information fusion. It receives design parameter requests and extracts multi-dimensional information such as physical structure, electrical connections, thermal management, and material compatibility. Combining contextual data and a historical experience database, it constructs a nonlinear mapping relationship between parameters. This embodiment uses natural language processing technology to parse unstructured request content; employs feature recognition algorithms to detect unconventional parameter combinations; establishes a dynamic mapping model to associate parameters with performance indicators; configures quantum effect correction factors to improve the accuracy of thermal management parameters; and quantifies material compatibility through a multi-dimensional evaluation matrix.

[0068] In one embodiment of the present invention, based on step S102, the following will provide a possible embodiment and its specific implementation will be described in a non-limiting manner. Step S102 further includes the following steps: Step S1021: Based on nonlinear parameter coupling topology, identify the set of verification items in the stacked package chip design, including physical structure, electrical connection, thermal management, material compatibility, manufacturing process and reliability parameters, and determine the initial set of items to be verified through dynamic correlation matrix, avoiding traditional linear classification methods.

[0069] Step S1022: Generate a quantum entropy random sequence for each initial item to be verified, as the basis for generating a unique verification identifier, ensuring the absolute uniqueness of the identifier, surpassing existing hash or sequence number allocation methods.

[0070] Step S1023: Apply the real-time priority evolution algorithm to adjust the weight of the items to be verified according to the environmental response characteristics of the design parameters, and assign multi-dimensional verification identifiers, including timestamps and context information, to high-weight items.

[0071] Step S1024: Through cross-domain coupling strength analysis, identify the implicit interaction network between the items to be verified, and assign collaborative verification identifier groups to the nodes in the network to support data sharing and redundancy reduction within the group.

[0072] Step S1025: Finally, solidify the list of items to be verified by the chip and their unique verification identifiers, and write the list code into the quantum computing resistant storage medium to ensure the immutability and long-term traceability of the verification process.

[0073] Step S102 in this embodiment is based on nonlinear parameter topology analysis and quantum entropy identifier allocation, implemented by integrating a dynamic correlation engine and a quantum random number generator. Design parameters are analyzed using a nonlinear coupled topology model to identify verification items. A random sequence is generated using a quantum entropy source, and a unique identifier is assigned to each item. This embodiment adjusts priorities in real time based on environmental responses and assigns collaborative identifiers to coupled item groups; the results are stored in quantum-resistant storage.

[0074] In one embodiment of the present invention, based on step S103, the following will provide a possible embodiment and describe its specific implementation in a non-limiting manner. Step S103 further includes the following steps: Step S1031: Introduce dynamic context factors into the preset verification conditions. The factors include the designer's experience level, customer customization requirements, and batch characteristics of supply chain materials. Adjust the verification conditions in real time through a fuzzy logic controller.

[0075] It should be noted that the experience level of designers is related to the number of years of design experience for both novice designers and senior engineers. Levels can be set based on different lengths of experience, such as every 5 years as a level.

[0076] Step S1032: Construct a multimodal verification matrix, and divide the verification conditions into three categories: basic mandatory items, advanced recommended items, and innovative exploration items. Activate the verification of advanced or innovative items according to the design complexity.

[0077] It should be noted that the basic mandatory options can cover asymmetric stacked structures, the advanced recommended options are quantum tunneling effect index monitoring, and the innovative exploration options are phonon propagation path integrity verification, etc. The complexity is set according to the number of layers, such as more than 5 layers, which is more complex and activates the advanced or innovative option verification.

[0078] Step S1033: Identify potential contradictions between preset verification conditions, such as signal integrity conflicts that may be caused by dynamic impedance compensation methods and gradient transition material combinations. Generate parameters to adjust the material combination order or compensation method through constraint satisfaction problem algorithms to ensure the internal consistency of verification conditions.

[0079] Step S1034: Configure the priority sorting of verification conditions. Based on factors such as the impact of parameters on overall performance, historical failure frequency, and manufacturing process sensitivity, assign a dynamic priority to each verification condition to avoid verification omissions due to too many conditions.

[0080] It should be noted that the impact can be the effect of thermal management parameters on heat dissipation efficiency, and the historical failure frequency can be the proportion of electrical connection parameters that have failed in past projects.

[0081] Step S1035: Establish a knowledge graph of verification conditions, store information such as verification conditions, parameter relationships, and historical verification cases in a graph structure, and realize intelligent recommendation of verification conditions through a graph neural network (GNN) model to improve the relevance and coverage of verification conditions.

[0082] The graph neural network (GNN) model here uses graph convolutional network (GCN) to embed the knowledge graph and aggregate node information such as verification conditions and parameter relationships through message passing. It outputs the recommendation probability of verification conditions. For example, when the design contains an asymmetric stacking structure, it recommends the probability of thermal management parameter verification conditions, thus realizing the intelligent association of verification conditions.

[0083] Step S103 of this embodiment is based on context-aware and multimodal verification technology. By integrating design context information, verification condition classification, conflict detection, and priority ranking, it achieves accurate matching between verification conditions and actual design requirements. For example, for design requests submitted by novice designers, the verification conditions can be reduced through a fuzzy logic controller, condition conflicts can be resolved through the CSP algorithm, verification priorities can be determined using historical data, and intelligent recommendations can be achieved with the help of knowledge graphs and GNN models, ensuring that the verification conditions are both comprehensive and adaptable to specific design scenarios.

[0084] In one embodiment of the present invention, based on step S108, the following will provide a possible embodiment and its specific implementation will be described in a non-limiting manner. Step S108 further includes the following steps: Step S1081: When updating the verification result template, configure the threshold adjustment method and adjust the pass threshold of each verification item according to the design complexity. For example, reduce the pass threshold of the mechanical stress distribution field of high-density stacked structure to break through the limitation of fixed threshold in the existing technology.

[0085] This embodiment addresses the actual risk that the design complexity of stacked packaged chips directly affects parameters. Complexity involves the number of layers, wiring density, and chip size ratio. High-density stacked structures, such as 8-layer stacks, have a much higher risk of local stress concentration in the mechanical stress distribution field due to narrow interlayer spaces, more significant signal and stress interference, and narrower interlayer spaces. Therefore, a preset complexity-threshold adjustment rule is used to dynamically adapt the acceptable threshold to the design complexity.

[0086] Step S1082: Topological data analysis (TDA) is used to identify nonlinear coupling relationships between parameters; for example, the potential correlation between the quantum tunneling effect index and the phonon propagation path integrity is used to generate a synergistic effect score, providing a quantitative basis for design optimization.

[0087] In this embodiment, there are many nonlinear and non-explicit coupling relationships among the multidimensional parameters of the stacked packaged chip. Topological data analysis (TDA) maps the parameter data to a point cloud structure in the topological space, extracts topological features such as connectivity and clustering of the point cloud, and identifies hidden nonlinear association patterns. Then, through the association strength-synergy effect scoring mapping rule, the abstract association is transformed into a quantitative score. For example, the synergy effect score of quantum tunneling and phonon path is 9 points, which is judged as a strong nonlinear association.

[0088] Step S1083: Map the chip design parameters to industry practices.

[0089] This embodiment constructs an industry practice knowledge base covering fields such as electronics and communications. The base stores verified design parameters and application effects. The parameters of the current design are matched with the parameters in the knowledge base to map reusable industry practice cases, standard clauses, and potential risk points.

[0090] Step S1084: Establish an adaptive learning method, train machine learning models such as random forests using historical verification data, and predict the direction of parameter adjustment under different design scenarios. For example, predict the optimization ratio of gradient transition material combinations based on material interface compatibility factors to avoid reliance on human experience.

[0091] Step S1085: Configure the global optimization suggestion generator. Based on the results of multi-dimensional parameter synergy effect analysis, use the NSGA-II multi-objective optimization algorithm to balance the conflicts between parameters and generate a design optimization path that includes alternative solutions.

[0092] In this embodiment, the multidimensional parameters of the stacked packaged chips often conflict. NSGA-II uses non-dominated sorting and crowding calculation to find Pareto optimal solutions among multiple conflicting objectives. The global optimization suggestion generator uses the synergy analysis results as algorithm constraints, outputs 3-5 Pareto optimal solutions as alternatives, and labels the parameter values, performance indicators, and applicable scenarios of each solution to form an optimization path.

[0093] Step S108 of this embodiment is based on threshold adjustment, cross-domain knowledge fusion, adaptive learning, and multi-objective optimization techniques. Through multi-dimensional parameter synergy analysis and global optimization suggestion generation, it achieves intelligent updating of the verification result template. The implementation includes: dynamically adjusting the pass threshold according to design complexity; quantifying parameter coupling relationships using topological data analysis; integrating external industry knowledge to enhance the innovation of adjustment suggestions; predicting optimization directions using machine learning models; and balancing parameter conflicts through multi-objective optimization algorithms to form a verification result optimization process.

[0094] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0095] The following are embodiments of the design parameter verification system for stacked packaged chips provided in this disclosure. This system and the design parameter verification methods for stacked packaged chips described above belong to the same inventive concept. Details not fully described in the embodiments of the design parameter verification system for stacked packaged chips can be found in the embodiments of the design parameter verification methods for stacked packaged chips described above. Figure 2 As shown, the system includes: Design request parsing module 201 is used to receive design parameter verification requests for stacked packaged chips; The verification item initialization module 202 is used to take the physical structure parameter verification involved in the stacked package chip design process as the chip verification item and assign a unique verification identifier to each chip verification item. The verification condition matching module 203 is used to determine whether the verification identifier of each chip to be verified matches the extracted stacked package chip design parameters under preset verification conditions. The target verification determination module 204 is used to determine the corresponding chip to be verified as the target chip verification item if the judgment result is yes, and to execute the verification rules of the target chip verification item. The associated verification module 205 is used to determine whether there are other chip verification items associated with the chip verification item if the judgment result is negative. The other chip verification items associated are verification items that have parameter coupling relationship with the current chip verification item. The associated verification module 206 is used to treat other associated chip verification items as new chip verification items if the judgment result is yes. The multidimensional parameter extraction module 207 is used to extract the multidimensional coupling parameter set and the corresponding target package chip design information from the execution result after the execution of the verification rules for all target chip verification items is completed. The verification result integration module 208 is used to update the preset chip design verification result template based on the extracted target package chip design information, and use the updated template as design parameters to request the corresponding verification result.

[0096] like Figure 3 As shown, this application also provides an electronic device, including a display module 103, a memory 102, a processor 101, and a computer program stored in the memory and executable on the processor 101. When the processor 101 executes the program, it implements the steps of a method for verifying design parameters of a stacked packaged chip.

[0097] In embodiments of the present invention, electronic devices include, but are not limited to, laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. Electronic devices may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the embodiments described and / or claimed herein.

[0098] In this embodiment, processor 101 may be implemented using at least one of an application-specific integrated circuit, a programmable logic device, a field-programmable gate array, a processor, a controller, a microcontroller, a microprocessor, or an electronic unit designed to perform the functions described herein. In some cases, such an implementation may be implemented within a controller. For software implementation, implementations such as processes or functions may be implemented with separate software modules that allow the performance of at least one function or operation. Software code may be implemented by a software application (or program) written in any suitable programming language, and the software code may be stored in memory and executed by the controller.

[0099] The display module 103 is used to display information input by the user or information provided to the user. The display module 103 may include a display panel, which may be configured in the form of a liquid crystal display, an organic light-emitting diode, or the like.

[0100] The memory 102 can be used to store software programs and various data. The memory 102 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other volatile solid-state storage device.

[0101] This application also provides a storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the design parameter verification method for the stacked packaged chip.

[0102] The storage medium may be any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example,, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples (a non-exhaustive list) of readable storage media include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0103] In a storage medium, a readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying readable program code. This propagated data signal may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium, capable of sending, propagating, or transmitting a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0104] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for design parameter verification of a stacked package chip, the method comprising: The method comprises: S101: receiving a design parameter verification request of a stacked package chip; S102: verifying the physical structure parameters involved in the design process of the stacked package chip as chip verification items, and assigning a unique verification identifier to each chip verification item; S103: determining whether the verification identifier of each chip verification item matches the preset verification condition of the stacked package chip design parameters extracted in step S101; S104: if the result of step S103 is yes, the corresponding chip verification item is determined as a target chip verification item, and the verification rule of the target chip verification item is executed; S105: if the result of step S103 is no, it is determined whether there is an associated other chip verification item for the chip verification item, and the associated other chip verification item is a verification item having a parameter coupling relationship with the current chip verification item; S106: if the result of step S105 is yes, the associated other chip verification item is taken as a new chip verification item, and step S103 is returned; S107: after completing the verification rule execution of all target chip verification items, a multi-dimensional coupling parameter set and corresponding target package chip design information are extracted from the execution result; S108: according to the extracted target package chip design information, the preset chip design verification result template is updated, and the updated template is taken as the verification result corresponding to the design parameter request.

2. The method of claim 1, wherein the design parameter verification of the stacked package chip is performed by a computer program. Step S101 further comprises the following steps: When receiving the stacked package chip design parameter request, the context information associated with the request is obtained, and the unstructured text information is converted into a structured parameter constraint condition through a semantic analysis technology; When extracting the physical structure parameters in the request, an asymmetric stacked structure feature recognition algorithm is used to detect whether the number of layers, spacing and substrate thickness contain irregular combinations; When analyzing the electrical connection parameters, a dynamic mapping model of electrical signal synchronization deviation is established, the via diameter and wiring density are associated with signal transmission delay and crosstalk noise performance indicators, and the deviation between the measured data and the theoretical model is quantified to measure the rationality of the parameters; When processing the thermal management parameters, the quantum tunneling effect index is configured as a correction factor of the heat conduction path, the thermal conductivity of the thermal interface material and the layout of the heat dissipation channel are combined to construct a three-dimensional heat flow density distribution cloud map, and the local hot spot area is identified and the thermal stress concentration coefficient is calculated; When integrating the material compatibility parameters, a multi-dimensional evaluation matrix of material interface compatibility factors is constructed, the thermal expansion coefficient, elastic modulus and chemical bonding strength of each layer of material are weighted and fused to generate a quantitative score of the material cooperative deformation capability.

3. The method of claim 1, wherein the design parameter verification of the stacked package chip is performed by a computer program. Step S102 further comprises the following steps: Based on the nonlinear parameter coupling topology, the verification item point set in the stacked package chip design is identified, the initial verification item set is determined through a dynamic association matrix, and the traditional linear classification method is avoided; A quantum entropy random sequence is generated for each initial verification item as the basis for generating a unique verification identifier; An real-time priority evolution algorithm is applied to adjust the weight of the verification item according to the environmental response characteristics of the design parameters, and a multi-dimensional verification identifier is assigned to the high-weight item, including a timestamp and context information; By cross-domain coupling strength analysis, the implicit interaction network between the to-be-verified items is identified, and a collaborative verification identification group is assigned to the nodes in the network; Finally, the to-be-chip-verified item list and its unique verification identification are solidified, and the list code is written into the anti-quantum computing storage medium.

4. The method of claim 1, wherein the design parameter verification of the stacked package chip is performed by a computer program. Step S103 further includes the following steps: Introduce a dynamic context factor into the preset verification condition; Construct a multi-modal verification matrix, divide the verification conditions into three categories: basic mandatory items, advanced recommended items, and innovative exploration items, and activate the advanced or innovative item verification according to the design complexity; Identify potential contradictions between the preset verification conditions, generate adjustment material combination order or compensation mode parameters through constraint satisfaction problem algorithm, and ensure the internal consistency of the verification conditions.

5. The method of claim 4, wherein the design parameter verification of the stacked package chip is performed by a computer program. After ensuring the internal consistency of the verification conditions, the following steps are further included: Configure the verification condition priority order, assign a dynamic priority to each verification condition according to the impact of the parameter on the overall performance, the historical failure frequency, and the manufacturing process sensitivity; Establish a verification condition knowledge graph and realize intelligent recommendation of the verification condition through a graph neural network model.

6. The method of claim 1, wherein the design parameter verification of the stacked package chip is performed by a computer program. Step S108 further includes the following steps: When updating the verification result template, configure the threshold adjustment method, and adjust the qualified threshold of each verification item according to the design complexity; Identify the nonlinear coupling relationship between parameters through topological data analysis; Map the chip design parameters to the industry practice; Establish an adaptive learning method, train a machine learning model such as random forest through historical verification data, and predict the parameter adjustment direction in different design scenarios; Configure a global optimization suggestion generator, balance the conflicts between parameters based on the multi-dimensional parameter collaborative effect analysis results, and generate a design optimization path containing alternative solutions using NSGA-II multi-objective optimization algorithm.

7. The method of claim 1, wherein the design parameter verification of the stacked package chip is performed by a computer program. The physical structure parameter verification rules in step S104 include simulating stress distribution of different layer combinations through finite element analysis, the electrical connection parameter verification rules include measuring signal transmission delay and automatically adjusting terminal matching resistance using time domain reflectometry, the thermal management parameter verification rules include obtaining three-dimensional temperature field distribution through infrared thermal imaging and quantifying interlayer heat superposition effect, the material compatibility parameter verification rules include testing interface bonding strength using a nanoindenter, the manufacturing process parameter verification rules include collecting real-time data through an online monitoring system and implementing closed-loop feedback control, and the reliability parameter verification rules include detecting delamination defects using an acoustic microscope and shortening the test period by adjusting stress amplitude and cycle number.

8. A system for design parameter verification of a stacked package chip, the system comprising: The system is used to implement the design parameter verification method of the stacked package chip as claimed in any one of claims 1 to 7; The system includes: A design request analysis module for receiving a design parameter verification request of a stacked package chip; A verification item initialization module for taking the physical structure parameter verification involved in the design process of the stacked package chip as a to-be-chip-verified item and assigning a unique verification identification to each to-be-chip-verified item; A verification condition matching module for judging whether the verification identification of each to-be-chip-verified item matches the extracted stacked package chip design parameters with the preset verification condition; The target verification determination module is configured to determine the corresponding to-be-chip-verified item as a target chip verification item and execute a verification rule of the target chip verification item if the determination result is yes. The associated verification introduction module is configured to determine whether the to-be-chip-verified item has an associated other chip verification item if the determination result is no, the associated other chip verification item being a verification item having a parameter coupling relationship with the current to-be-verified item. The associated verification introduction module is configured to take the associated other chip verification item as a new to-be-chip-verified item if the determination result is yes. The multi-dimensional parameter extraction module is configured to extract a multi-dimensional coupling parameter set and corresponding target package chip design information from an execution result after the verification rules of all target chip verification items are executed. The verification result integration module is configured to update a preset chip design verification result template according to the extracted target package chip design information, and take the updated template as a design parameter request corresponding verification result.

9. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor executes the program to implement the steps of the design parameter verification method of the stacked package chip according to any one of claims 1 to 7.

10. A storage medium having stored thereon a computer program, characterized in that The computer program is executed by the processor to implement the steps of the design parameter verification method of the stacked package chip according to any one of claims 1 to 7.

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