Method and device for generating target pin table

Abstract

The invention provides a method and a device for generating a target pin table, and relates to the technical field of circuits, the method comprises the following steps: analyzing a schematic diagram to obtain the type of a device contained in the schematic diagram; based on the type of the device, screening out a target chip from the device; extracting basic information of a target pin of the target chip from the schematic diagram; wherein the basic information comprises one or more of a pin name, a pin number, a network name and an element tag; based on the basic information of the target pin and a preset chip database, determining circuit information and electrical information of the target pin; wherein basic information and electrical information of chip pins are stored in the chip database; and generating a target pin table based on the basic information, the circuit information and the electrical information of the target pin.

Description

Technical Field

[0001] This application relates to the field of circuit technology, and in particular to a method and apparatus for generating a target pin table. Background Technology

[0002] In electronic circuit design, pins are external interfaces for chips such as MCUs (Microcontroller Units) and SoCs (System-on-Chips), used to connect to external devices or circuits. For example, General Purpose Input / Output (GPIO) pins are crucial interfaces for interaction between MCUs, SoCs, and other programmable processing core devices and peripheral circuits; their proper configuration directly determines the circuit's functionality and operational stability. To support design verification and software development, engineers need to generate structured tables containing target pin information, such as GPIO pin tables.

[0003] However, the generation of target pin tables in related technologies often relies on manual operation. During the manual extraction process, problems such as data omission, input errors, or inconsistencies in information are prone to occur. Therefore, there is an urgent need for a method that can automatically parse multi-source data, accurately integrate the inherent attributes of the chip and circuit design information, and then generate a complete and accurate target pin table to meet the needs of electronic circuit design for efficient, accurate, and structured data management. Summary of the Invention

[0004] This application provides a method and apparatus for generating a target pin table, which can generate the target pin table efficiently and accurately.

[0005] In a first aspect, embodiments of this application provide a method for generating a target pin table, comprising: Analyze the schematic diagram to determine the types of devices contained in the schematic diagram; Based on the type of the device, target chips are selected from the devices; Extract basic information of the target pins of the target chip from the schematic diagram; wherein, the basic information includes one or more of the following: pin name, pin number, network name, and component label; Based on the basic information of the target pin and a preset chip database, the circuit information and electrical information of the target pin are determined; wherein, the chip database stores the basic information and electrical information of the chip pin; A target pin table is generated based on the basic information, circuit information, and electrical information of the target pin.

[0006] Secondly, embodiments of this application provide an apparatus for generating a target pin table, comprising: The parsing module is configured to parse the schematic diagram and obtain the types of devices contained in the schematic diagram; The extraction module is configured to filter target chips from the devices based on the device type; and extract basic information of target pins of the target chips from the schematic diagram; wherein the basic information includes one or more of the following: pin name, pin number, network name, and component label; The determination module is configured to determine the circuit information and electrical information of the target pin based on the basic information of the target pin and a preset chip database; wherein, the chip database stores the basic information and electrical information of the chip pin; The generation module is configured to generate a target pin table based on the basic information, circuit information, and electrical information of the target pin.

[0007] Thirdly, embodiments of this application provide an electronic device, including a memory and a processor, wherein the memory stores an executable program, and the processor executes the executable program to perform the steps of the method as described in any of the preceding claims. Attached Figure Description

[0008] Figure 1 A flowchart illustrating a method for generating a target pin table according to an embodiment of this application; Figure 2 A flowchart for determining driving capability is provided as an embodiment of this application; Figure 3 A flowchart for generating different types of files is provided as an embodiment of this application; Figure 4 A flowchart of a verification multiplexing function is provided as an embodiment of this application; Figure 5 A schematic diagram of a target pin table generation apparatus provided for one embodiment of this application; Figure 6 This is a schematic diagram of the structure of an electronic device provided in one embodiment of this application. Detailed Implementation

[0009] Various embodiments and features of this application are described herein with reference to the accompanying drawings.

[0010] It should be understood that various modifications can be made to the embodiments described herein. Therefore, the above description should not be considered as limiting, but merely as an example of embodiments. Other modifications within the scope and spirit of this application will be apparent to those skilled in the art.

[0011] The accompanying drawings, which are included in and form part of this specification, illustrate embodiments of the present application and, together with the general description of the present application given above and the detailed description of the embodiments given below, serve to explain the principles of the present application.

[0012] These and other features of this application will become apparent from the following description of preferred forms of embodiments given as non-limiting examples, with reference to the accompanying drawings.

[0013] It should also be understood that although this application has been described with reference to some specific examples, those skilled in the art can certainly implement many other equivalent forms of this application.

[0014] The above and other aspects, features and advantages of this application will become more apparent when taken in conjunction with the accompanying drawings and in view of the following detailed description.

[0015] Specific embodiments of this application are described thereafter with reference to the accompanying drawings; however, it should be understood that the claimed embodiments are merely examples of this application, which can be implemented in various ways. Well-known and / or repeated functions and structures are not described in detail to avoid unnecessary or redundant details that could obscure the application. Therefore, the specific structural and functional details claimed herein are not intended to be limiting, but merely serve as the basis and representative basis for the claims to teach those skilled in the art to use this application in a variety of substantially any suitable detailed structures.

[0016] This specification may use the phrases “in one embodiment,” “in another embodiment,” “in yet another embodiment,” or “in other embodiments,” all of which may refer to one or more of the same or different embodiments according to this application.

[0017] The processing method of this application will be described in detail below with reference to the accompanying drawings.

[0018] like Figure 1 As shown in the figure, this application embodiment provides a method for generating a target pin table, including: Step 101: Analyze the schematic diagram to obtain the types of devices contained in the schematic diagram.

[0019] Specifically, the EDA (Electronic Design Automation) tool Copilot can be used to analyze schematic diagrams to extract and classify data from the input schematic. This includes reading the component library index, package type, and device identification tags from the schematic, and using semantic recognition algorithms to classify the devices, such as chip types (MCU, SoC), component types (resistors, capacitors), peripheral types (sensors, connectors), etc.

[0020] Step 102: Based on the type of device, select the target chip from the devices.

[0021] Based on the classification results output in step 101, the core devices for which pin tables need to be generated are selected, such as the target chip MCU or SoC.

[0022] Step 103: Extract basic information of the target pins of the target chip from the schematic diagram; the basic information includes one or more of the following: pin name, pin number, network name and component label.

[0023] Extract basic information about all pins from the schematic diagram, specifically including: Read the pin labels (such as "PA9" or "GPH6") of the target chip in the schematic diagram to obtain the pin names; Read the chip package pin number corresponding to the pin (such as Pin23, Pin45) to obtain the pin number; Read the network label (such as "EC_LA3_INT_R_N", "EC_KB_BKL_EN") of the pin connection to obtain the network name; Read the component label associated with the pin (e.g., “U22:ID6 / GPH6”, “PB1_KEY”) to obtain the component label.

[0024] Since the target chip may have multiple pins, step 103 can extract only the basic information of the target pin that needs to be of interest, for example, the target pin is a GPIO pin.

[0025] Step 104: Based on the basic information of the target pin and the preset chip database, determine the circuit information and electrical information of the target pin; wherein, the chip database stores the basic information and electrical information of the chip pin.

[0026] Using the extracted basic information as an index, such as pin name PA9 and chip model STM32F4, the preset chip database is called to match and obtain the electrical information of the pin, such as level standard, drive mode (e.g., push-pull output / open-drain output), drive strength, interrupt capability (e.g., support for rising edge / falling edge interrupt), and resistance matching range.

[0027] The data in the chip database can be obtained from the chip datasheet. The chip database can establish a three-level index of chip model, pin name, and electrical information to ensure fast matching.

[0028] The circuit information of the target pin can be determined by parameters such as the network name obtained through parsing.

[0029] Step 105: Generate a target pin table based on the basic information, circuit information, and electrical information of the target pins.

[0030] Specifically, the target pin table may include fields such as: pin name, pin number, network name, function direction, level standard, drive mode, pull-up / pull-down status, etc.

[0031] For example, for 100 pins, the target pin table generated through the embodiments of this application can be shortened to less than 5 minutes, with an error rate of less than 3% and a reuse rate of 85%. Compared with the manual generation method, it is faster, has a lower error rate, and a higher reuse rate.

[0032] The entire generation process is automated, eliminating the need for manual switching between schematics, chip datasheets, and Excel, significantly reducing pin processing time. This embodiment automates data extraction, avoiding inevitable errors and omissions caused by manual copying, pasting, and inputting large amounts of data. The system programmatically matches data, ensuring a high degree of consistency between the target pin table and the schematic and chip datasheet. In this embodiment, the chip database stores only basic and electrical information; circuit information can be derived from the schematic, eliminating the need to update the database for each project (circuit information for the same chip may differ in different projects). This reduces storage resource consumption and database maintenance workload. Pre-setting professional knowledge such as chip electrical parameters in the chip database allows even less experienced engineers to generate compliant, professional tables containing key electrical information.

[0033] In one embodiment of this application, the circuit information and electrical information of the target pin are determined based on the basic information of the target pin and a preset chip database, including: Based on the basic information of the target pin, determine the circuit information of the target pin; Based on the basic and circuit information of the target pin, as well as a pre-defined chip database, the electrical information of the target pin is determined.

[0034] Circuit information refers to the connection status, functional positioning, and external association characteristics of the target pin in the current schematic diagram. For example, the functional direction of the pin, whether it is connected to a pull-up / pull-down resistor, and the type of associated peripheral device. It reflects the interaction between the pin and the external circuit.

[0035] Dynamic derivation of circuit information is achieved through schematic semantic parsing and circuit topology analysis, without relying on a chip database. Specifically, natural language processing algorithms are used to parse keywords in the basic information and establish a mapping relationship between keywords and functional directions. For example, "LED", "EN", and "CTRL" correspond to output directions, "KEY", "INT", and "DET" correspond to input directions, and "USART" and "SPI" correspond to bidirectional communication. If the network name in the basic information is "EC_LED_EN", the function direction of that pin is deduced to be output; if the component label is "PB1_KEY", it is deduced to be input.

[0036] Based on the network connection relationships in the basic information, the connection logic between the pins and peripheral devices is analyzed through a traversal algorithm to determine whether there are pull-up / pull-down resistors, whether power / ground is connected, etc. For example, if the basic information shows "PA9 pin is connected to resistor R197, and the other end of R197 is connected to the +3.3V network", then the circuit information is deduced to be "PA9 pin is connected to an external 10KΩ pull-up resistor (R197)". If the pin is directly connected to the GND network, then it is deduced to be "pin grounded".

[0037] If there are conflicting keywords in the basic information of the same pin, such as the network name "EC_LED_KEY" which contains both "LED" and "KEY", then mark it as "Functional direction to be confirmed" to avoid subsequent electrical information matching deviations.

[0038] For each target pin, structured circuit information can be generated, such as functional direction (input / output / bidirectional), peripheral connection characteristics (pull-up / pull-down / no pull-up / grounded / power supply connected), and associated peripheral component types.

[0039] Electrical information refers to the inherent electrical characteristic parameters of a target pin that are related to the chip's hardware design. Examples include pin level standards (1.8V / 3.3V / 5V), drive mode (push-pull output / open-drain output), drive strength (20mA / 50MHz), interrupt capability (supports rising edge / falling edge / double-edge triggering), and level tolerance range (such as maximum input voltage 5.5V). Essentially, these are hardware attributes fixed at the chip's factory and do not change with the application scenario; they are only related to the chip model.

[0040] In determining electrical information, basic information serves as an index to the chip database, providing matching keywords (such as pin name "PA9" and chip model "S911-16") to ensure accurate pin location from the database. Circuit information acts as a constraint for filtering electrical parameters, selecting parameters suitable for the current circuit scenario from multiple sets of selectable electrical parameters in the chip database. For example, if the circuit information indicates an output direction, the output drive parameters for that pin in the chip database are selected. The chip database stores the mapping relationship between "chip model - pin name - electrical parameter" and is the core data source for electrical information.

[0041] Without circuit information constraints, directly matching electrical information based on basic information can easily lead to parameter mismatch issues. For example, matching the open-drain output mode of PA9 pin to an LED control scenario can cause the LED to fail to light up properly because open-drain output requires an external pull-up resistor, which may not be designed for the LED scenario.

[0042] This application's embodiments employ a step-by-step logic of first deriving circuit information and then matching electrical information. The circuit information serves as a filtering constraint for electrical parameters, ensuring that the matched electrical information is fully compatible with the current circuit scenario. For example, if the circuit information is derived as "PA9 pin has no external pull-up resistor," the chip database will only match push-pull output mode, excluding open-drain output, as open-drain output requires a pull-up resistor, thus avoiding design errors caused by mode mismatch with the circuit.

[0043] In one embodiment of this application, determining the circuit information of the target pin based on its basic information includes: Determine the network connection of the target pin based on its network name; Based on the network connections of the target pin, determine the pull-up resistors, pull-down resistors, and external components of the target pin; wherein, one end of the pull-up resistor is connected to the target pin and the other end is connected to the power supply, and one end of the pull-down resistor is connected to the target pin and the other end is grounded; The functional orientation of the target pin is determined based on the labels of the peripheral components.

[0044] The netlist file generated from the schematic stores the mapping between network name, device pin, and node. The EDACopilot tool can read the netlist file and locate all circuit nodes within the network based on the network name of the target pin. The tool converts the node relationships in the netlist file into a topology diagram, clearly showing the connection paths between the target pin and other devices, power / ground, etc. It excludes non-functional nodes such as test points and empty connector pins, retaining only active device pins, passive component pins, and power / ground nodes directly associated with the target pin, ensuring that network connection information focuses on the core links.

[0045] For the target pin, generate a network connection list, which includes at least the associated device model and pin, the connected power / ground nodes, and the network signal flow, laying the foundation for subsequent identification of resistors and peripheral components.

[0046] Extract all associated devices from the network connection list and determine the device type based on the component label, package type, and parameter identifier. For example, a label starting with "R" indicates a resistor, "D" indicates a diode / LED, "S" indicates a sensor, and "C" indicates a capacitor.

[0047] For the resistors initially screened out, check the connection nodes at both ends. If one end is connected to the target pin and the other end is connected to the power supply node, it is determined to be a pull-up resistor and the resistance parameters are recorded. If one end is connected to the target pin and the other end is connected to GND, it is determined to be a pull-down resistor. If neither end is connected to the power supply / ground, it is classified as a current limiting / voltage dividing resistor and included in the external components.

[0048] By using a keyword matching algorithm derived from natural language processing, functional attribute keywords are extracted from the labels of peripheral components, and the functional direction is determined based on these keywords. For example, LED and RELAY correspond to output, KEY to input, and SPI to bidirectional operation.

[0049] If the target pin is connected to multiple peripheral components, the signal flow direction will be used as the primary indicator. If the flow direction cannot be determined, the function direction will be marked as pending confirmation, and all possible direction options will be output for manual verification.

[0050] The embodiments of this application transform circuit information extraction into standardized steps, eliminating the need to rely on human experience and greatly improving information extraction efficiency.

[0051] In one embodiment of this application, the circuit information includes network connectivity, and the electrical information includes the drive capability of the target pin, such as... Figure 2 As shown, at this point, based on the basic information of the target pin and the preset chip database, the circuit information and electrical information of the target pin are determined, including: Step 201: Determine the circuit information of the target pin based on the basic information of the target pin.

[0052] Step 202: Determine the circuit topology type based on the network connections of the target pins.

[0053] Specifically, peripheral components directly associated with the target pin are extracted from the network connection list and categorized into three types based on load characteristics: active loads: components that require a driving current from the pin to operate (such as LEDs, relays, and small motors); passive trigger loads: components that do not require a driving current from the pin and transmit signals only through level changes (such as buttons and sensor outputs); and no loads: peripheral components with no direct association to the pin or only connected to a filter capacitor.

[0054] Based on the preset correspondence between load type and circuit topology type, the circuit topology type of the target pin is determined. For example, an active load corresponds to an active load drive topology.

[0055] Step 203: Based on the basic information of the target pin, obtain the current output range of the target pin from the chip database.

[0056] The chip database can employ a three-level index structure: chip model → pin name → electrical parameters. The chip model serves as the first-level index, locating the parameter set for the corresponding chip; the pin name serves as the second-level index, extracting the current output range field for that pin. If the chip database does not contain the current output range for a given pin, it is marked as needing to be added, and the default range for chips in the same series is output.

[0057] Step 204: Determine the driving capability of the target pin based on the circuit topology type; wherein, the driving capability of the target pin is used to characterize whether the current required to be output by the target pin is within its current output range.

[0058] Drive capability refers to whether the target pin can provide the current required by the external load under the current circuit topology, that is, whether the load current is within the current output range specified in the chip database.

[0059] Specifically, based on the circuit topology and the parameters of the peripheral components, the required load current to be output at the target pin is calculated. Taking an active load drive topology as an example, the PA9 pin level is 3.3V, the LED forward voltage drop Vf = 2.0V, and the series resistance R = 10KΩ. Therefore, the load current I = (3.3 - 2.0) / 10000 = 0.13mA. The load current is compared with the current output range obtained from the chip database. If the load current is within the range, the drive is considered qualified; if the load current exceeds the upper limit of the range, the drive is considered overloaded; and if the load current is below the lower limit of the range, the drive is considered insufficient.

[0060] The driving capability and other parameters in the embodiments of this application are automatically calculated based on the component parameters in the network connection, without the need for manual input, which can reduce the calculation error rate.

[0061] In one embodiment of this application, the method further includes: extracting the power label of the target pin from the schematic diagram; Based on the basic, circuit, and electrical information of the target pins, a target pin table is generated, including: Based on the basic information of the target pin, the voltage level range of the target pin is queried from the chip database; Determine if the value corresponding to the power tag is within the level range; if not, generate a conflict flag for the power tag. A target pin table is generated based on the target pin's basic information, circuit information, electrical information, and conflict markers of the power supply tag.

[0062] Using the chip model as the primary index, the parameter set of the corresponding chip is located. Then, using the pin name as the secondary index, the voltage level range field of that pin is extracted. The power supply label is converted into a specific voltage value (e.g., "+3VS" → 3.3V). The converted power supply voltage value is compared with the voltage level range. If the voltage value is within the range, there is no conflict, and no flag is generated. If the voltage value exceeds the upper limit of the range, a high-risk conflict is identified, and an overload warning is generated. If the voltage value is below the lower limit of the range, a medium-risk conflict is identified, and an insufficient voltage warning is generated. If multiple power supply labels exist, each is compared with the voltage level range. If any label exceeds the range, a corresponding conflict flag is generated.

[0063] The embodiments of this application automatically extract power tags, query level ranges, and compare conflicts without manual intervention, enabling timely detection of conflicts in the early stages of design.

[0064] In one embodiment of this application, such as Figure 3 As shown, the method also includes: Step 301: Extract the corresponding fields from the target pin table according to the preset multiple file types.

[0065] Multiple file types refer to file formats commonly used by different roles throughout the hardware design process. For example, there are code header files for software programming, silkscreen files for PCB production, and JSON metadata for data management. Corresponding fields refer to essential information fields for each file type that are strongly related to its function. For example, code header files require pin numbers and register configurations, while silkscreen files require pin physical locations and identifiers.

[0066] Step 302: Generate files of various file types based on fields of various file types; among them, multiple file types include at least two of the following: code header files, printed circuit board silkscreen files, and JSON metadata.

[0067] For each target file type, required fields, optional fields, and field format requirements can be predefined to form a mapping relationship. Based on this mapping relationship, all fields in the target pin table are filtered as needed. For example, when generating the code header file, only fields related to software initialization, such as pin number, function direction, and drive mode, are extracted, while irrelevant information such as PCB silkscreen coordinates is excluded. The filtered fields are then formatted to ensure they conform to the syntax or specifications of the target file type. For example, for code header file fields, the pin name PA9 is converted to a C language macro definition (e.g., #define GPIO_PA9_PIN 9).

[0068] Load the standard template for the corresponding file type from the template library, and fill the processed fields into the corresponding standard template to obtain different types of files.

[0069] This application embodiment automatically extracts fields from each file from a unified table, eliminating the need for manual filtering and significantly saving engineers' repetitive work time.

[0070] In one embodiment of this application, such as Figure 4 As shown, a target pin table is generated based on the basic information, circuit information, and electrical information of the target pins, including: Step 401: Based on the basic information of the target pin, obtain the multiplexing function information of the target pin from the chip database.

[0071] Using the chip model as the primary index, the system locates the set of multiplexed function parameters for the corresponding chip. Then, using the pin name as the secondary index, it extracts the complete list of multiplexed functions for that pin. The extracted list of multiplexed functions is then divided into three categories: default functions, optional multiplexed functions, and mutually exclusive function groups. The mutually exclusive function groups are the core basis for subsequent conflict verification. If the chip database does not contain multiplexed function information for that pin, the default multiplexing rules for chips in the same series are output.

[0072] Step 402: Based on the multiplexing function information and the circuit information of the target pin, verify whether the target pin is configured as multiple mutually exclusive multiplexing functions at the same time. If so, proceed to step 403; otherwise, terminate the current process.

[0073] Multiplexing function conflict refers to a situation where a target pin is simultaneously configured for two or more functions in a mutually exclusive function group in the chip database during the current circuit design. Such conflicts can lead to pin function disorder and are a typical hidden danger in hardware design.

[0074] The actual functional configuration of the target pin is parsed from the circuit information. Based on the network name keywords, peripheral component type, and drive mode, the currently configured function of the pin is determined. For example, if the circuit information shows "PA9 connects to the RX pin of the UART chip, network name is USART1_TX", then the current configured function is "USART1_TX"; if the register configuration identifier "TIM1_CH2" also exists, then the current configured function is "USART1_TX+TIM1_CH2".

[0075] The currently configured function is matched with the mutual exclusion function group in the chip database. If none of the currently configured functions are in the same mutual exclusion group, it is determined that there is no conflict and no flag is generated. If the currently configured functions are in the same mutual exclusion group, it is determined that there is a high-risk conflict and a conflict flag is generated, clearly indicating the mutual exclusion function combination and risk consequences. If the currently configured function is not included in the multiplexed function list, it is determined that the function configuration is invalid and a medium-risk flag is generated, such as invalid configuration: PA9 does not support CAN1_RX multiplexing function.

[0076] Step 403: Generate conflict markers for reused functions.

[0077] Step 404: Generate a target pin table based on the target pin's basic information, circuit information, electrical information, and conflict flags for multiplexing functions.

[0078] This application's embodiments add multiplexing function-related fields and conflict flag fields, integrating basic information, circuit information, electrical information, and multiplexing function conflict flags into a complete table. This ensures that the table includes both design parameters and conflict warning capabilities. By associating multiplexing function parameters with the chip database and combining them with circuit information from the schematic diagram, automatic verification and conflict flagging of mutually exclusive functions are achieved, solving the problems of difficult manual troubleshooting and delayed risk detection in traditional solutions.

[0079] In one embodiment of this application, a target pin table is generated based on the basic information, circuit information, and electrical information of the target pins, including: Based on the circuit information of the target pin, determine whether the circuit where the target pin is located is an analog circuit; if so, determine the type of analog circuit. A target pin table is generated based on the target pin's basic information, circuit information, analog circuit type, and electrical information.

[0080] Specifically, a circuit is classified as an analog circuit if it meets any of the following conditions: the circuit contains at least one analog-specific component, such as an operational amplifier; the network name contains analog keywords and the signal path is a continuous analog link; the topology is an analog signal acquisition / processing configuration, such as sensor → conditioning resistor → analog chip input. If the conditions are not met, the circuit is classified as a digital circuit and no further classification is required.

[0081] For analog circuits, the analog circuit type is determined based on the component type. For example, if the circuit contains an operational amplifier and the target pin is the input / output pin of the operational amplifier, then the analog circuit type is an operational amplifier circuit; if the circuit contains an analog sensor and the target pin is used to receive the analog signal output by the sensor, then the analog circuit type is an analog sensor acquisition circuit.

[0082] This application's embodiments achieve digital / analog differentiation by accurately identifying analog circuit characteristics, thus solving the problem of the lack of analog characteristics in traditional solutions.

[0083] like Figure 5 As shown, this application embodiment provides a target pin table generation apparatus, including: The parsing module 501 is configured to parse the schematic diagram and obtain the types of devices contained in the schematic diagram; Extraction module 502 is configured to filter target chips from devices based on device type; it extracts basic information of target pins of the target chip from the schematic diagram; wherein, the basic information includes one or more of the following: pin name, pin number, network name and component label; The determination module 503 is configured to determine the circuit information and electrical information of the target pin based on the basic information of the target pin and a preset chip database; wherein, the chip database stores the basic information and electrical information of the chip pin; The generation module 504 is configured to generate a target pin table based on the basic information, circuit information and electrical information of the target pins.

[0084] In one embodiment of this application, the determining module 503 is configured to determine the circuit information of the target pin based on the basic information of the target pin; and to determine the electrical information of the target pin based on the basic information and circuit information of the target pin, as well as a preset chip database.

[0085] In one embodiment of this application, the determination module 503 is configured to determine the network connection of the target pin based on the network name of the target pin; and to determine the pull-up resistor, pull-down resistor and peripheral components of the target pin based on the network connection of the target pin; wherein, one end of the pull-up resistor is connected to the target pin and the other end is connected to the power supply, one end of the pull-down resistor is connected to the target pin and the other end is grounded; and to determine the functional direction of the target pin based on the label of the peripheral component.

[0086] In one embodiment of this application, the circuit information includes network connectivity, and the electrical information includes the driving capability of the target pin; the determining module 503 is configured to determine the circuit topology type based on the network connectivity of the target pin; based on the basic information of the target pin, the current output range of the target pin is obtained from the chip database; based on the circuit topology type, the driving capability of the target pin is determined; wherein, the driving capability of the target pin is used to characterize whether the current that the target pin needs to output is within its current output range.

[0087] In one embodiment of this application, the extraction module 502 is configured to extract the power supply tag of the target pin from the schematic diagram; the generation module 504 is configured to query the level range of the target pin from the chip database based on the basic information of the target pin; determine whether the value corresponding to the power supply tag is within the level range, and if not, generate a conflict mark for the power supply tag; and generate a target pin table based on the basic information, circuit information, electrical information and conflict mark of the power supply tag of the target pin.

[0088] In one embodiment of this application, the generation module 504 is configured to extract corresponding fields from the target pin table according to a variety of preset file types; and generate files of various file types based on the fields of various file types; wherein, the various file types include at least two of the following: code header files, printed circuit board silkscreen files, and JSON metadata.

[0089] In one embodiment of this application, the generation module 504 is configured to obtain the multiplexing function information of the target pin from the chip database based on the basic information of the target pin; based on the multiplexing function information and the circuit information of the target pin, verify whether the target pin is simultaneously configured as multiple mutually exclusive multiplexing functions; if so, generate a conflict flag for the multiplexing function; and generate a target pin table based on the basic information, circuit information, electrical information and conflict flag of the multiplexing function of the target pin.

[0090] In one embodiment of this application, the generation module 504 is configured to determine whether the circuit where the target pin is located is an analog circuit based on the circuit information of the target pin, and if so, determine the type of analog circuit; and generate a target pin table based on the basic information of the target pin, the circuit information, the type of analog circuit and the electrical information.

[0091] This application provides an electronic device, such as... Figure 6 As shown, it includes a memory and a processor. The memory stores an executable program, and the processor executes the executable program to perform the method steps as described in any of the above embodiments.

[0092] This application also provides a storage medium that carries one or more computer programs, which, when executed by a processor, implement the steps of the method described above.

[0093] The electronic device in this application embodiment can be a terminal or other devices besides a terminal. For example, the electronic device can be a tablet computer, laptop computer, handheld computer, in-vehicle electronic device, mobile internet device (MID), augmented reality (AR) / virtual reality (VR) device, robot, wearable device, ultra-mobile personal computer (UMPC), netbook, or personal digital assistant (PDA), etc. It can also be a server, network attached storage (NAS), personal computer (PC), television (TV), ATM, or self-service machine, etc. The embodiments disclosed in this disclosure do not specifically limit the scope.

[0094] The processors mentioned above can be general-purpose processors, including CPUs, NPs (Network Processors), etc.; they can also be DSPs (Digital Signal Processors), ASICs (Application Specific Integrated Circuits), FPGAs (Field Programmable Gate Arrays), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0095] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state drive), etc.

[0096] The above embodiments are merely exemplary embodiments of this application and are not intended to limit this application. The scope of protection of this application is defined by the claims. Those skilled in the art can make various modifications or equivalent substitutions to this application within its substance and scope of protection, and such modifications or equivalent substitutions should also be considered to fall within the scope of protection of this application.

Claims

1. A method for generating a target pin table, comprising: Analyze the schematic diagram to determine the types of devices contained in the schematic diagram; Based on the type of the device, target chips are selected from the devices; Extract basic information of the target pins of the target chip from the schematic diagram; wherein, the basic information includes one or more of the following: pin name, pin number, network name, and component label; Based on the basic information of the target pin and a preset chip database, the circuit information and electrical information of the target pin are determined; wherein, the chip database stores the basic information and electrical information of the chip pin; A target pin table is generated based on the basic information, circuit information, and electrical information of the target pin.

2. The method according to claim 1, Based on the basic information of the target pin and a preset chip database, the circuit information and electrical information of the target pin are determined, including: Based on the basic information of the target pin, determine the circuit information of the target pin; Based on the basic and circuit information of the target pin, as well as a preset chip database, the electrical information of the target pin is determined.

3. The method according to claim 2, Based on the basic information of the target pin, the circuit information of the target pin is determined, including: Based on the network name of the target pin, determine the network connection of the target pin; Based on the network connection of the target pin, the pull-up resistor, pull-down resistor, and peripheral components of the target pin are determined; wherein, one end of the pull-up resistor is connected to the target pin and the other end is connected to the power supply, and one end of the pull-down resistor is connected to the target pin and the other end is grounded; The functional orientation of the target pin is determined based on the label of the peripheral component.

4. The method according to claim 2, in, The circuit information includes network connectivity, and the electrical information includes the drive capability of the target pin. Based on the basic and circuit information of the target pin, and a pre-defined chip database, the electrical information of the target pin is determined, including: Based on the network connections of the target pins, determine the circuit topology type; Based on the basic information of the target pin, the current output range of the target pin is obtained from the chip database; Based on the circuit topology, the driving capability of the target pin is determined; wherein, the driving capability of the target pin is used to characterize whether the current required to be output by the target pin is within its current output range.

5. The method of claim 1, further comprising: Extract the power label of the target pin from the schematic diagram; Based on the basic information, circuit information, and electrical information of the target pins, a target pin table is generated, including: Based on the basic information of the target pin, the voltage level range of the target pin is queried from the chip database; Determine whether the value corresponding to the power tag is within the specified level range; if not, generate a conflict flag for the power tag. The target pin table is generated based on the basic information, circuit information, electrical information, and conflict markers of the power supply tag of the target pin.

6. The method of claim 1, further comprising: According to the preset multiple file types, the corresponding fields are extracted from the target pin table respectively; Based on the fields of the various file types, generate files of various file types; wherein the various file types include at least two of the following: code header files, printed circuit board silkscreen files, and JSON metadata.

7. The method according to claim 1, Based on the basic information, circuit information, and electrical information of the target pins, a target pin table is generated, including: Based on the basic information of the target pin, the multiplexing function information of the target pin is obtained from the chip database; Based on the multiplexing function information and the circuit information of the target pin, it is verified whether the target pin is simultaneously configured as multiple mutually exclusive multiplexing functions. If so, a conflict flag for the multiplexing function is generated. The target pin table is generated based on the basic information, circuit information, electrical information, and conflict flags of the multiplexing function of the target pin.

8. The method according to claim 1, Based on the basic information, circuit information, and electrical information of the target pins, a target pin table is generated, including: Based on the circuit information of the target pin, determine whether the circuit where the target pin is located is an analog circuit; if so, determine the type of the analog circuit. The target pin table is generated based on the basic information, circuit information, analog circuit type, and electrical information of the target pin.

9. An apparatus for generating a target pin table, comprising: The parsing module is configured to parse the schematic diagram and obtain the types of devices contained in the schematic diagram; The extraction module is configured to filter out target chips from the devices based on the type of the devices; Extract basic information of the target pins of the target chip from the schematic diagram; wherein, the basic information includes one or more of the following: pin name, pin number, network name, and component label; The determination module is configured to determine the circuit information and electrical information of the target pin based on the basic information of the target pin and a preset chip database; wherein, the chip database stores the basic information and electrical information of the chip pin; The generation module is configured to generate a target pin table based on the basic information, circuit information, and electrical information of the target pin.

10. An electronic device, comprising a memory and a processor, wherein the memory stores an executable program, and the processor executes the executable program to: parse a schematic diagram to obtain the types of devices contained in the schematic diagram; Based on the type of the device, target chips are selected from the devices; Extract the basic information of the target pins of the target chip from the schematic diagram; wherein... The basic information includes one or more of the following: pin name, pin number, network name, and component label; Based on the basic information of the target pin and a preset chip database, the circuit information and electrical information of the target pin are determined; wherein, the chip database stores the basic information and electrical information of the chip pin; A target pin table is generated based on the basic information, circuit information, and electrical information of the target pin.

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