A high-power laser chip with dual thermal drift suppression and its fabrication process

Abstract

This invention provides a high-power laser chip with dual thermal drift suppression and its fabrication process, relating to the field of laser chip technology. The chip utilizes a negative Poisson's ratio strain reversal structure symmetrically arranged on both sides below a P-type ohmic contact layer, connected by folded-back microbeams. This structure employs a thermal expansion-driven physical compensation mechanism to convert the longitudinal expansion caused by heating into lateral tensile strain on the active region, thereby broadening the energy band and offsetting the bandgap reduction caused by temperature rise, achieving near-zero redshift lasing output. Simultaneously, a gradient phonon crystal heat flow guiding layer is embedded between the active region and the ohmic contact layer. The spatial gradient distribution of nanopore density enables directional deflection of heat flow to the chip's sides. Combined with the high thermal conductivity channels on the sides to eliminate the thermal lensing effect, this invention solves the problems of severe wavelength drift and heat accumulation leading to beam quality deterioration in traditional laser chips under high-power continuous operation, significantly improving the upper limit of output power and stability.

Description

Technical Field

[0001] This invention relates to the field of laser chip technology, specifically to a high-power laser chip with dual thermal drift suppression and its fabrication process. Background Technology

[0002] According to Chinese Patent No. CN105790071A, a novel high-power semiconductor laser and its fabrication method can effectively solve the problems of low laser yield, complex process, poor bonding quality, and low reliability in existing structural designs, promoting the development of conduction-cooled high-power semiconductor lasers towards higher power. This high-power semiconductor laser includes a heat sink and a chipset module composed of several laser chips and their substrates. The bottom of the substrate is bonded to the heat sink with solder, and the main body of the substrate is an insulating thermally conductive block. Corresponding to the bonding area of ​​the laser chips on the substrate, conductive thermally conductive layers are provided on both the front and back sides of the insulating thermally conductive block. The conductive thermally conductive layers on the front and back sides are electrically connected through conductive materials that penetrate the surface and / or interior of the insulating thermally conductive block.

[0003] According to Chinese Patent No. CN116742466A, a double-sided cooling laser chip packaging structure and its fabrication method are disclosed. This invention embeds the laser chip into a ceramic substrate, resulting in a double-sided cooling packaging design for the laser chip. The double-sided cooling packaging structure designed in this invention can diffuse the heat generated by the laser chip through the contacting double-sided substrate chip to the heat sink, significantly enhancing the heat dissipation capacity of the laser chip. Furthermore, this wire-free bonding structure allows for laser emission without wire bonding, eliminating the fatigue effect caused by wire bonding processes and thus improving packaging reliability.

[0004] The aforementioned patent documents and prior art have the following technical problems when used:

[0005] Problem 1: When traditional laser chips operate continuously, the temperature of the active region increases, which causes the band gap of the semiconductor material to narrow. The lasing wavelength inevitably drifts towards longer wavelengths (redshift), which limits its performance in applications requiring precision spectroscopy, optical communication, and high pump efficiency.

[0006] Question 2: The heat transfer inside a conventional chip follows a random diffusion law (isotropic scattering of phonons), which leads to the most severe heat accumulation in the central region of the ridge waveguide, forming a severe thermal lensing effect, resulting in output power saturation and beam quality deterioration. Summary of the Invention

[0007] To address the shortcomings of existing technologies, this invention provides a high-power laser chip with dual thermal drift suppression and its fabrication process, solving the technical problems existing in the prior art.

[0008] To achieve the above objectives, the present invention provides the following technical solution: a high-power laser chip with dual thermal drift suppression and its fabrication process. The laser chip includes a substrate, on the upper surface of which are sequentially disposed an N-type Bragg reflector layer, a multi-quantum-well self-gain active region, a stress buffer layer, a P-type ohmic contact layer, and an N-type back electrode. Symmetrical negative Poisson's ratio strain reversal structures are disposed on both sides below the P-type ohmic contact layer. These structures are connected by folded-back microbeams to convert the longitudinal expansion of the chip due to heat into lateral tensile strain on the multi-quantum-well self-gain active region. A gradient phonon crystal heat flow guiding layer is embedded between the P-type ohmic contact layer and the multi-quantum-well self-gain active region. The gradient phonon crystal heat flow guiding layer alters the phonon mean free path through the spatial gradient distribution of nanopore density, achieving directional deflection of heat flow to the chip's sides.

[0009] Preferably, the negative Poisson's ratio strain reversal structure is composed of a micron-scale double funnel unit array with a negative Poisson's ratio effect, and the thermal expansion coefficient of its material is greater than that of the material of the multi-quantum-well self-gain active region.

[0010] Preferably, the diameter of the nanopores in the gradient phonon crystal heat flow guiding layer is 50 nanometers to 200 nanometers, and the pore duty cycle gradually decreases from the center of the waveguide to both sides, forming a phonon refractive index gradient.

[0011] Preferably, the sidewalls of the negative Poisson's ratio strain reversal structure are wrapped with a transverse phonon rapid extraction channel, which is made of carbon-12 isotope purified diamond material.

[0012] Preferably, an elastic modulus matching layer is provided between the multi-quantum well self-gain active region and the negative Poisson's ratio strain inversion structure to transfer stress and prevent interface dislocations.

[0013] Preferably, an in-situ thermoelectric feedback adjustment electrode is provided above the P-type ohmic contact layer, and the in-situ thermoelectric feedback adjustment electrode adjusts the local current injection in real time according to the wavelength signal fed back from the chip end face.

[0014] Preferably, the preparation process includes the following steps:

[0015] Sp1: An N-type Bragg reflector underlayer and a multi-quantum-well self-gain active region are deposited on the substrate using an epitaxial growth process;

[0016] Sp2: Micro- and nano-grooves with negative Poisson's ratio structures are fabricated in the two regions above the self-gain active region of a multi-quantum well using focused ion beam etching or nanoimprint technology.

[0017] Sp3: High expansion coefficient material is filled in micro-nano slots using selective region epitaxy to form a negative Poisson's ratio strain inversion structure;

[0018] Sp4: During the growth of the upper cladding layer, a gradient-distributed nanopore array is manufactured through a block copolymer self-assembly process to form a gradient phonon crystal heat flow guiding layer;

[0019] Sp5: Using plasma-enhanced chemical vapor deposition, isotope-purified diamond films are deposited on the chip sidewalls to construct a lateral phonon rapid extraction channel.

[0020] Sp6: Fabrication of a P-type ohmic contact layer and an in-situ thermoelectric feedback regulating electrode;

[0021] Sp7: Thinning is performed on the back side of the substrate to fabricate an N-type back electrode.

[0022] Preferably, the micro-nano grooves in Sp2 penetrate the stress buffer layer and terminate 100 nanometers above the upper surface of the multi-quantum-well self-gain active region, and the gradient distribution in Sp4 controls the formation location and diameter of the pores by changing the ratio of hydrophilic groups in the copolymer.

[0023] Preferably, the high expansion coefficient material filled in the Sp3 is zinc oxide or indium antimonide. During the filling process, the deposition rate is precisely controlled to ensure that there are no air bubbles inside the micro-nano trench, thereby achieving linear transmission of strain.

[0024] Preferably, hydrogen plasma surface treatment is required before depositing the diamond film in Sp5 to improve the interfacial thermal conductivity between the transverse phonon rapid extraction channel and the negative Poisson's ratio strain inversion structure.

[0025] This invention provides a high-power laser chip with dual thermal drift suppression and its fabrication process. It offers the following advantages:

[0026] 1. This invention achieves physical compensation driven by thermal expansion by introducing a negative Poisson's ratio strain reversal structure. When the chip is heated and undergoes longitudinal expansion, the metamaterial structure will spontaneously generate lateral contraction, thereby applying precisely controlled tensile stress to the active region. According to the deformation potential theory, this lateral stretching will cause the band structure to shift upward, thereby offsetting the reduction in band gap caused by temperature rise. This physical dynamic hedging mechanism enables the lasing wavelength to maintain extremely high stability over a wide temperature range, achieving lasing output with near-zero redshift.

[0027] 2. This invention employs an integrated gradient phonon crystal heat flow guiding layer. By spatially modulating the phonon density of states, it imparts directionality to heat transfer. Utilizing the phonon bandgap effect, it designs the thermal path in the same way as designing an optical path, converging and refracting the heat that would otherwise diffuse randomly in all directions into the high thermal conductivity channels on the side wings. This heat flow lensing technology greatly reduces the peak temperature in the waveguide center region, eliminates the thermal lensing effect, and significantly improves the upper limit of the chip's linear output power and the stability of the far-field beam. Attached Figure Description

[0028] Figure 1 This is a core structural diagram of the laser chip of the present invention;

[0029] Figure 2 This is a flowchart illustrating the fabrication process steps of the laser chip of the present invention;

[0030] Figure 3 This is a front cross-sectional view of the laser chip of the present invention;

[0031] Figure 4 This is a top cross-sectional view of the laser chip of the present invention.

[0032] The structure includes: 1. Substrate; 2. N-type Bragg reflector bottom layer; 3. Multi-quantum well self-gain active region; 4. Negative Poisson's ratio strain inversion structure; 5. Gradient phonon crystal heat flow guiding layer; 6. Stress buffer layer; 7. Lateral phonon fast extraction channel; 8. In-situ thermoelectric feedback regulating electrode; 9. P-type ohmic contact layer; 10. N-type back electrode. Detailed Implementation

[0033] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Specific Implementation Example 1:

[0035] like Figures 1 to 4As shown, a high-power laser chip with dual thermal drift suppression is disclosed. The laser chip includes a substrate 1. On the upper surface of the substrate 1, an N-type Bragg reflector layer 2, a multi-quantum-well self-gain active region 3, a stress buffer layer 6, a P-type ohmic contact layer 9, and an N-type back electrode 10 are sequentially disposed. Symmetrically arranged negative Poisson's ratio strain reversal structures 4 are positioned on both sides below the P-type ohmic contact layer 9. The negative Poisson's ratio strain reversal structures 4 are connected by folded-back microbeams to convert the longitudinal expansion caused by chip heating into lateral tensile strain on the multi-quantum-well self-gain active region 3. A gradient phonon crystal heat flow guiding layer 5 is embedded between the P-type ohmic contact layer 9 and the multi-quantum-well self-gain active region 3. The gradient phonon crystal heat flow guiding layer 5 changes the phonon mean free path through the spatial gradient distribution of nanopore density, achieving directional deflection of heat flow to the chip's sides. The negative Poisson's ratio strain reversal structure 4 consists of... The waveguide is composed of a micron-scale dual-funnel array with a negative Poisson's ratio effect. The thermal expansion coefficient of the material is greater than that of the material of the multi-quantum-well self-gain active region 3. The nanopores in the gradient phonon crystal heat flow guiding layer 5 have a diameter of 50 nm to 200 nm, and the duty cycle of the pores gradually decreases from the center of the waveguide to both sides, forming a phonon refractive index gradient. The sidewall of the negative Poisson's ratio strain inversion structure 4 is wrapped with a transverse phonon fast extraction channel 7, which is made of diamond material purified by carbon-12 isotope. An elastic modulus matching layer is provided between the multi-quantum-well self-gain active region 3 and the negative Poisson's ratio strain inversion structure 4 to transfer stress and prevent interface dislocations. An in-situ thermoelectric feedback adjustment electrode 8 is provided above the P-type ohmic contact layer 9. The in-situ thermoelectric feedback adjustment electrode 8 adjusts the local current injection in real time according to the wavelength signal fed back from the chip end face.

[0036] In-depth analysis of chip structure and causal logic:

[0037] The N-type back electrode 10 is located at the bottom of the chip, serving as the physical starting point of the device's electrical circuit. It employs a multilayer composite alloy structure of gold-germanium-nickel (AuGeNi) and gold (Au). Its depth design is driven by the rapid thermal annealing process, which allows germanium atoms to penetrate the substrate lattice, forming extremely low-resistance ohmic contacts. This reduces interfacial Joule heating caused by high current injection at the source. The electrode thickness is set between 300nm and 400nm. It not only performs current injection but also serves as the final interface for bonding the chip to the external heat sink. Its excellent flatness and metal wettability ensure that internal waste heat can be unimpededly conducted to the external cooling environment, minimizing the thermal resistance path. The substrate 1 sits above the N-type back electrode 10 and is made of highly doped single-element n-GaAs (gallium arsenide) material, with its internal doping concentration controlled within a certain range. To ensure vertical conductivity, the substrate was precisely thinned to approximately 110µm from a thermodynamic equilibrium perspective. The causal logic behind this thickness selection is that it provides sufficient mechanical strength to resist thermal stress caused by non-uniform thermal expansion under high-power operation, preventing cleavage damage to the crystal, while minimizing the physical path of vertical heat conduction, allowing heat from the core area to be conducted to the heat dissipation bottom surface with the shortest distance. The N-type Bragg reflector layer 2 is deposited on the upper surface of the substrate 1 and consists of dozens of pairs of periodically alternating aluminum gallium arsenide and gallium arsenide layers. Its primary function is to form a high-reflectivity interface using the principle of coherent interference, confining photons within the active region to improve stimulated gain and preventing coherent light leakage to the substrate, which would cause non-radiative absorption heating. In terms of thermal management, this layer, by finely adjusting the concentration gradient of the aluminum composition, makes its thermal expansion coefficient distributed in a stepped manner in the vertical direction, playing a preliminary role in thermal strain regulation. It can moderately guide and spread the vertically downward thermal stress in the horizontal direction, effectively reducing the local hot spot concentration phenomenon at the bottom of the chip.

[0038] The multi-quantum-well self-gain active region 3 is located above the N-type Bragg reflector layer 2. As the light-emitting center and main heat source of the chip, it is composed of an indium gallium arsenide (inGaAs) well layer and an aluminum gallium arsenide (AlGaAs) barrier layer. This structure adopts a strain compensation design, using the opposite stress vectors between the well and barrier layers to offset the lattice mismatch, achieving extremely high internal quantum efficiency and reducing the waste heat released by non-radiative recombination. Since it is the source of thermal drift, its physical state directly determines the stability of the output wavelength. Therefore, it is set at the geometric center of the entire chip management system, cooperating with the surrounding mechanical and thermal structures to sense and counteract the bandgap contraction effect caused by temperature rise in real time. The stress buffer layer 6 is closely attached to the upper surface of the multi-quantum-well self-gain active region 3. The material selected is indium gallium phosphide (inGaP) or low-aluminum AlGaAs. The existence of this layer has a deep process protection and mechanical conduction causality: on the one hand, it serves as a physical termination point for the complex micro-nano processing flow above, preventing dry etching. Plasma damage and surface dislocations during the process directly erode the sensitive active region, ensuring the long lifespan of the device. On the other hand, it acts as a strain distributor, ensuring that the mechanical tension generated by the negative Poisson's ratio strain reversal structure 4 can be smoothly, linearly and losslessly coupled to the quantum well lattice, realizing the high-fidelity transmission of the stress hedging mechanism. The gradient phonon crystal heat flow guiding layer 5 is embedded in the cladding above the stress buffer layer 6. The recommended material is in-situ P-AIGaAs etched holes. This structure achieves its effect by directly creating periodic vacuum holes or filling them with low thermal conductivity oxides in the cladding material. The principle is as follows: the phonon bandgap mechanism is used to block the longitudinal diffusion of heat flow. A very high density of holes is set in the waveguide center region to greatly shorten the phonon mean free path, forming a longitudinal high thermal resistance region, thereby flattening the "central heat island". As the hole density decreases towards the flanks, the phonon refractive gradient formed forces the heat flow to be directionally deflected to the low resistance sides, realizing the transformation of the heat flow vector from longitudinal accumulation to transverse conduction.

[0039] The negative Poisson's ratio strain inversion structure is symmetrically embedded on both sides of the ridge. The recommended core filler is zinc oxide (ZnO) or indium antimonide (InSb). It is essential to select a material with a significantly higher coefficient of thermal expansion (TEC) than GaAs (ZnO's TEC is approximately...). / K (higher than GaAs), the principle is as follows: when the chip is heated, the filler rapidly expands and squeezes the folded microbeams. The concave geometry of the structure triggers the negative Poisson's ratio effect (lateral expansion under pressure), converting longitudinal thermal expansion into lateral tensile strain. This lateral tension acts on the multi-quantum-well self-gain active region 3, causing the quantum well lattice to be stretched, resulting in bandgap widening. This precisely offsets the bandgap contraction caused by temperature rise, achieving suppression of wavelength thermal drift in situ from a physical perspective. The elastic modulus matching layer is specially set at the mechanical connection between the multi-quantum-well self-gain active region 3 and the negative Poisson's ratio strain reversal structure 4. The recommended material is aluminum nitride (AIN). AIN has extremely high hardness (modulus matching) and good thermal conductivity. As a rigid transfer medium between the active region and the compensation structure, AIN can transfer the mechanical stress generated by the negative Poisson's ratio strain reversal structure 4. The tensile force is transferred to the active region almost without loss, avoiding plastic dissipation of stress at the soft interface. At the same time, its high thermal conductivity assists the lateral diffusion of heat flow and effectively prevents dislocation accumulation at the interface of heterogeneous materials, improving the sensitivity of the compensation mechanism. The lateral phonon fast extraction channel 7 is wrapped around the sidewall of the negative Poisson ratio strain inversion structure 4 and distributed along the vertical edge of the chip. The recommended material is carbon-12 isotope purified diamond. Natural diamond contains about 1.1% carbon-13, which will cause severe phonon isotope scattering. The purified carbon-12 diamond eliminates this scattering, and its thermal conductivity can reach more than 3300 W / m·K. As the receiving terminal of the gradient phonon crystal heat flow guiding layer 5, it can instantly absorb the deflected lateral heat flow and guide it to the heat sink at the bottom at an extremely high speed, solving the power saturation problem caused by heat accumulation at the center of the high-power laser.

[0040] The top layer of the 9-position dry-ridge waveguide with P-type ohmic contact layer uses highly doped P-type arsenide material. Its design function is to establish a current injection window with an extremely low barrier, thereby reducing contact resistance by improving hole injection efficiency. Its physical significance is that, under high-power conditions with high current injection, the extremely low resistivity of this layer can significantly suppress the additional ohmic heat generated at the interface. This not only ensures that no secondary heat source is formed on the top of the chip, but also provides a stable electrical operating background for the in-situ thermoelectric feedback adjustment electrode 8 above. The in-situ thermoelectric feedback adjustment electrode 8 is located above the P-type ohmic contact layer 9 and is a micro-array composed of highly stable metals such as platinum (Pt). Its technical logic is to provide an active feedback control method: combined with the spectral signal fed back from the chip, the electrode applies a small bias current to generate localized controlled temperature stress. This, together with the physical compensation mechanism of the negative Poisson's ratio strain reversal structure 4, forms a "coarse adjustment + fine adjustment" combination to correct the small drift residue under extreme nonlinear environments and achieve sub-nanometer wavelength locking accuracy.

[0041] Physical linkage logic: This chip achieves thermal drift suppression through the deep linkage of two major systems: phonon directional transduction and strain dynamic compensation.

[0042] Heat flow driven stage: When waste heat is generated in the multi-quantum well self-gain active region 3, the gradient phononic crystal heat flow guiding layer 5 immediately acts as a heat barrier, blocking the heat from flowing vertically upward to the top of the ridge, and the heat flow is forced to refract laterally to both sides.

[0043] Strain-triggered stage: As the temperature rises, the filling material inside the negative Poisson's ratio strain reversal structure 4 expands. Since its thermal expansion coefficient is much higher than that of the matrix, it drives the folded microbeam to undergo geometric deformation, resulting in lateral stretching. This stress is linearly transmitted to the multi-quantum well self-gain active region 3 through the elastic modulus matching layer and stress buffer layer 6, stretching the lattice and broadening the energy band, thus offsetting the redshift caused by the temperature rise in situ.

[0044] Heat extraction stage: The lateral heat flow deflected by the gradient phonon crystal heat flow guiding layer 5 reaches the edge of the chip and is immediately captured by the superconductor lateral phonon rapid extraction channel 7. The heat flow is rapidly guided along the side of the chip to the N-type back electrode 10 below and the external heat sink, maintaining the low temperature gradient inside the chip.

[0045] Closed-loop fine-tuning stage: For the slight residual heat drift caused by the nonlinear fluctuation of the current, the in-situ thermoelectric feedback regulating electrode 8 actively fine-tunes according to the spectral feedback to ensure that the laser wavelength is always locked at the target frequency.

[0046] This coordinated process achieves a closed loop from heat source blocking to heat flow guidance, and then to the transformation of heat damage (into stress compensation), completely solving the wavelength stability problem of high-power lasers. Specific Implementation Example 2:

[0048] like Figures 1 to 4 As shown, based on the content of the above specific embodiments, the following content is further disclosed:

[0049] The preparation process includes the following steps:

[0050] Sp1: An N-type Bragg reflector substrate 2 and a multi-quantum-well self-gain active region 3 are deposited on substrate 1 by epitaxial growth process;

[0051] Sp2: Micro-nano slots with negative Poisson's ratio structures are fabricated on both sides of the multi-quantum-well self-gain active region 3 using focused ion beam etching or nanoimprint technology.

[0052] Sp3: Using selective region epitaxy to fill high expansion coefficient materials in micro-nano slots to form a negative Poisson's ratio strain inversion structure 4;

[0053] Sp4: During the growth of the upper cladding layer, a gradient distribution of nanopore arrays is manufactured through a block copolymer self-assembly process to form a gradient phonon crystal heat flow guiding layer 5;

[0054] Sp5: A transverse phonon rapid extraction channel 7 is constructed by depositing isotopically purified diamond films on the chip side using plasma-enhanced chemical vapor deposition.

[0055] Sp6: Fabrication of P-type ohmic contact layer 9 and in-situ thermoelectric feedback regulating electrode 8;

[0056] Sp7: Thinning is performed on the back side of the substrate to prepare an N-type back electrode 10.

[0057] The following is a detailed flowchart and operational details of the chip fabrication process:

[0058] Sp1: Precision epitaxial growth and interface control:

[0059] This step is performed in a metal-organic chemical vapor deposition (MOCVD) system. First, on an n-GaAs substrate 1 that has been chemically cleaned and had its native oxide layer removed, high-purity hydrogen is used as the carrier gas to introduce trimethylgallium (TMGa) and arsine (...). A buffer layer is grown, and then an N-type Bragg reflection bottom layer with alternating refractive indices is grown by precisely switching the flow rate of trimethylaluminum (TMAI). The growth of the core active region needs to enter the superlattice mode. The indium composition is precisely controlled in the multi-quantum well self-gain active region 3 by adjusting the molar flow rate ratio of trimethylindium (TMIn).

[0060] Operating requirements: Growth pressure must be maintained between 50 and 100 Torr, and temperature fluctuations must be strictly controlled. At 0.1 degrees Celsius, the growth rate should be maintained at around 1 nm / s;

[0061] Implementation logic: This extremely high-precision temperature control is to ensure that the thickness fluctuation of the quantum well is less than a single atomic layer, thereby ensuring the consistency of the gain spectrum;

[0062] Judgment scheme: The growth rate curve is monitored by in-situ light reflection. If the reflectance amplitude deviates from the preset value by 1%, it is judged as an epitaxial abnormality.

[0063] Sp2: High-precision directional etching of micro-nano trenches:

[0064] Using a dual-beam scanning electron microscope (SEM) to locate both sides of the ridge region in real time, a silicon dioxide hard mask was deposited on top of the multi-quantum-well self-gain active region 3, and then etched using focused ion beam (FIB) etching technology.

[0065] Operational details: The slot is designed with a folded geometry, and the ion beam current is set between 10 and 50 picoamperes to reduce ion implantation damage. The etching path is set with a complex folded geometry.

[0066] Depth control is achieved: the etching depth must penetrate the stress buffer layer 6. To achieve this precision, the equipment needs to detect the secondary ion mass spectrometry signal in real time. When a sudden change in the intensity of the aluminum or phosphorus signal is detected, it is determined that the ion beam has reached the edge of the buffer layer.

[0067] Judgment requirements: The remaining thickness of the bottom of the slot from the upper surface of the multi-quantum-well self-gain active region 3 must be measured by laser scanning confocal microscopy and determined to be within a deviation range of 100 nanometers.

[0068] Sp3: Selective region epitaxial filling and strain source construction:

[0069] The wafer with micro-nano trenches is sent back to the epitaxial furnace, the reaction chamber pressure is adjusted to a low pressure (about 50 mbar), and zinc oxide (ZnO) or indium antimonide (InSb) is deposited in the trenches using selective region epitaxy (SAE) technology.

[0070] Operational requirements: To ensure bubble-free filling, a pulsed growth method must be used, which involves alternately introducing precursors to allow atoms sufficient time to migrate at the bottom of the tank, preventing premature sealing that could lead to voids. This stepwise deposition method provides atoms with ample surface diffusion time, allowing them to preferentially fill the bottom corners of the micro / nano tank, thereby completely eliminating suspended bubbles.

[0071] Achieved effect: The dense, bubble-free filling ensures that when the filling material expands, the stress can be linearly transferred to the underlying elastic modulus matching layer through a continuous solid medium;

[0072] Data processing: Monitoring the density of the filling interface through real-time light reflection analysis;

[0073] Judgment method: After filling is completed, cross-section transmission electron microscopy is performed to determine that the filling rate must reach more than 99.9% to ensure the linear transmission of strain.

[0074] Sp4: Block copolymer self-assembly of gradient phononic crystals:

[0075] During the growth of the confinement layer, spin-coating of block copolymers, namely polystyrene-block-polymethyl methacrylate (PS-b-PMMA), allows for the spontaneous formation of periodically arranged nanospheres by adjusting the ratio of hydrophilic to hydrophobic groups in the copolymer (e.g., changing the relative molecular mass ratio of A-block to B-block).

[0076] Operational details: Solvent annealing or thermal annealing is used to induce molecular self-assembly. By applying non-uniform chemical modification or temperature field gradient on the wafer surface, the spatial distribution of hydrophilic groups in the copolymer is changed.

[0077] Implementation logic: The change in molecular weight ratio directly determines the diameter of the formed nanospheres or nanopillars. By applying a strong chemical confinement force at the center of the waveguide, a high-density arrangement is forced, thus obtaining the pore duty cycle with a high center and low sides.

[0078] Output data: The duty cycle distribution of the holes was obtained by scanning electron microscopy (SEM) to verify whether the duty cycle decreased in a gradient.

[0079] Sp5: Conformal deposition of isotopic diamond channels:

[0080] A transverse phonon fast extraction channel 7 was constructed on the chip side using plasma-enhanced chemical vapor deposition (PECVD);

[0081] Operating procedure: Before deposition, perform in-situ cleaning for 5 minutes in a hydrogen-containing plasma atmosphere;

[0082] In-depth explanation: Hydrogen treatment saturates the dangling bonds on the sidewalls, forming CH bond energy levels. This significantly reduces the phonon mismatch between the diamond and semiconductor interfaces. Introducing hydrogen pulses into the reaction chamber and using plasma to remove the sidewall oxide layer and hydrogen-terminate the surface, thereby reducing the interfacial thermal resistance (TBR) by more than 50%.

[0083] The exclusion of carbon-13 is to eliminate phonon aharmonic scattering caused by mass disorder;

[0084] Operational requirements: The substrate temperature should be maintained between 600°C and 800°C. Due to isotope purification requirements, the purity of carbon-12 in methane must be higher than 99.99%.

[0085] Achieved effect: A tightly wrapped superconducting thermal layer is formed on the sidewall of the chip.

[0086] Sp6: Electrode fabrication and PID feedback closed-loop system:

[0087] A P-type ohmic contact layer 9 was prepared using a lift-off process, and a platinum metal wire was sputtered on it as an in-situ thermoelectric feedback regulating electrode 8.

[0088] Method control logic: The chip integrates a wavelength monitoring unit. The input signal is the real-time lasing wavelength of the chip, and the output signal is the feedback current of the in-situ thermoelectric feedback regulating electrode 8.

[0089] Operational details: The proportional-integral-derivative (PID) control algorithm is adopted. When the wavelength deviation target value is detected, the controller output is calculated and the current injected into the in-situ thermoelectric feedback regulating electrode 8 is dynamically adjusted to lock the wavelength through local thermal strain.

[0090] Sp7: Substrate thinning and final ohmicization:

[0091] The back side of substrate 1 was physically thinned using chemical mechanical polishing (CMP) to uniformly reduce its thickness to 110 micrometers;

[0092] Operational requirements: The surface roughness Ra after polishing must be less than 0.5 nanometers;

[0093] The operation was completed by vacuum evaporation of a gold-germanium-nickel alloy followed by rapid thermal annealing at 420 degrees Celsius to complete the fabrication of the N-type back electrode 10. Specific Implementation Example 3:

[0095] like Figures 1 to 4 As shown, based on the content of the above specific embodiments, the following content is further disclosed:

[0096] The following details the actual operational steps involved in forming a dual thermal drift suppression laser chip from a single n-GaAs wafer:

[0097] Phase 1: Growth of Functional Epitaxial Layer (Construction of Chip Substrate):

[0098] Step 1 (Sp1): Epitaxy of the Substrate and Core Light-Emitting Layer: In the MOCVD reaction chamber, the cleaned n-GaAs substrate 1 is heated to 700°C. First, TMGa and... A GaAs buffer layer was grown, followed by programmed control of the Al component flow rate to form an N-type Bragg reflector substrate 2, which was then grown. trap layer and 3. Self-gaining active region of multiple quantum wells in the barrier layer;

[0099] Cause-and-effect logic: The growth rate is acquired in real time using an in-situ reflectivity monitor to ensure that the optical thickness error of each pair of DBR layers is controlled within a certain range. Within 0.5%, thereby maximizing coherent reflectivity and reducing waste heat generated by energy loss at the source.

[0100] Step 2: Fabrication of the mechanical coupling interface (elastic modulus matching layer): An aluminum nitride (AIN) layer with a thickness of 80 nm is deposited above the multi-quantum well self-gain active region 3;

[0101] Physical mechanism: The use of AlN is based on its extremely high Young's modulus (about 300 GPa) as a rigid conductive medium. This layer serves as a "hard connection" between the subsequent negative Poisson's ratio structure and the active region, ensuring the lossless transfer of micromechanical deformation energy.

[0102] Phase Two: Forming of Thermal and Mechanical Functional Structures (Micro / Nano Fabrication):

[0103] Step 3 (Sp2): Negative Poisson's ratio micro-nano trench directional etching: Electron beam lithography (EBL) is used to define a folded concave geometry on both sides of the ridge waveguide, and focused ion beam (FIB) is used for deep etching;

[0104] Control requirements: The etching depth must penetrate the AIN layer and terminate precisely at a position 100 nm above the upper surface of the multi-quantum-well self-gain active region 3;

[0105] Judgment scheme: Real-time monitoring of the In element signal in secondary ion mass spectrometry (SIMS). Once the signal intensity reaches 10% of the background value (judged as close to the edge of the active region), etching is stopped immediately. This step ensures that the strain compensation force can effectively act on the lattice without damaging the trap layer structure.

[0106] Step 4 (Sp3): Selective filling of strain compensation source: The wafer is sent back to the MOCVD reaction chamber and zinc oxide (ZnO) is filled into the tank using selective region epitaxy (SAE).

[0107] Operational details: Pulsed atomic layer deposition logic is adopted (2s of gas supply, 3s of gas supply interruption);

[0108] Implementation logic: This slow pulse mode gives atoms sufficient time to migrate on the surface, allowing them to grow from the bottom of the tank upwards and eliminating microbubbles (Voids);

[0109] Judgment criteria: Samples are extracted and observed by cross-section TEM (transmission electron microscopy). The judgment criterion is that there are no voids larger than 2nm at the interface to ensure the linear coupling of thermal expansion stress.

[0110] Step 5 (Sp4): Preparation of gradient phonon crystal heat flow guiding layer: During the growth of P-Cladding, the block copolymer (BCP) is spin-coated, and the molecular chain self-assembly is induced by applying a transverse temperature field gradient;

[0111] Implementation principle: Utilizing the difference in hydrophobicity of functional groups to form a nanopore array with dense centers and sparse edges;

[0112] Function: To form a phonon transport channel with high longitudinal thermal resistance and low lateral thermal resistance, and to force the heat flow of the central heat island to the flanks.

[0113] Phase 3: Superconducting thermal integration and electrode fabrication:

[0114] Step 6 (Sp5): Integration of transverse phonon fast extraction channel: The ridge is masked, and a 1µm thick carbon-12 purified diamond film, i.e., transverse phonon fast extraction channel 7, is deposited on the side using PECVD.

[0115] Key details: Two 5-minute plasma treatments were performed prior to deposition to remove dangling bonds on the surface;

[0116] Cause and effect explanation: The isotope purification material is selected to eliminate phonon scattering caused by carbon-13, and together with the heat flow deflected in step five, the heat extraction effect is achieved.

[0117] Step 7 (Sp6): Preparation of P / N ohmic contact and feedback regulation system: P-type ohmic contact layer 9 is formed by vapor deposition of Ti / Pt / Au, and in-situ thermoelectric feedback regulation electrode 8 is prepared in a specific area of ​​the ridge edge by peeling process;

[0118] Operational details: The adjusting electrode uses a platinum (Pt) thin film, and its resistance must be strictly matched to the output dynamic range of the control circuit.

[0119] Phase Four: Post-processing and Independent Chip Formation

[0120] Step 8 (Sp7): Substrate thinning and backside metallization: Chemical mechanical polishing (CMP) is performed on substrate 1 to reduce its thickness to 110 mm. 2μm;

[0121] Results achieved: The extremely thin substrate 1 significantly shortens the physical distance for heat to reach the heat sink, followed by the deposition of AuGeNi / Au to form an N-type back electrode 10, which is then rapidly annealed at 420°C.

[0122] Step 9: Cleavage and Cavity Surface Treatment: Using an automated cleavage machine, the wafer is cut into strips (Bar) along the crystal plane. An antireflective coating (AR) is deposited on the front cavity surface, and a high reflective coating (HR) is deposited on the back cavity surface.

[0123] Judgment criteria: Observe the flatness of the cleavage surface. If there are cleavage steps, it will cause mode instability, and the chip in that area must be scrapped.

[0124] Step 10: Chip Segmentation and Testing

[0125] Operation: Divide the bar into individual chips and perform LIV testing on the integrating sphere test bench;

[0126] Data processing: Record lasing spectra at different temperatures (25°C, 45°C, 65°C);

[0127] Judgment scheme: If the wavelength drift coefficient d with temperature / dT<0.02nm / K, indicating that the dual suppression structure is functioning normally.

[0128] Through these 10 steps, a smart, independent chip with an internally integrated heat flow deflector (phononic crystal) and mechanical compensator (negative Poisson's ratio structure) was realized. Specific Implementation Example 4:

[0130] like Figures 1 to 4As shown, based on the content of the above specific embodiments, the following content is further disclosed:

[0131] To verify the superior performance of the dual thermal drift suppression structure and its fabrication process proposed in this application, the following comparative experiment was designed. By comparing the chip of this application (experimental group) with the conventional structure chip (control group) in multiple dimensions, the wavelength locking capability and thermal management advantages under high power operation were demonstrated.

[0132] Three sets of samples will be prepared, each based on the same n-GaAs substrate 1 and multi-quantum-well self-gain active region 3, distinguished only by thermal management and stress compensation structures:

[0133] Control group A (conventional structure): manufactured using traditional processes, with no phonon crystals, no negative Poisson's ratio structure, and conventional AlGaAs cladding on the flanks;

[0134] Control group B (single heat dissipation optimization): only integrates transverse phonon fast extraction channel 7 (isotope diamond) on the side wing, but does not have negative Poisson's ratio and phonon crystal structure;

[0135] Experimental group C (full structure of this application): The preparation process is completely in accordance with the application, including gradient phonon crystal heat flow guiding layer 5, negative Poisson's ratio strain inversion structure 4 and transverse phonon rapid extraction channel 7.

[0136] Detailed experimental steps:

[0137] Step 1: Static thermal drift coefficient test ( / dT):

[0138] Operation: Install three sets of chips on a precision temperature-controlled thermoelectric cooler (TEC), and slowly raise the TEC temperature from 20°C to 80°C under extremely low current (only maintaining lasing to reduce self-heating interference);

[0139] Measurement: The amount of shift in the center wavelength is recorded using a spectrometer;

[0140] Objective: To verify the accuracy of physical compensation for ambient temperature fluctuations by negative Poisson's ratio structures.

[0141] Step 2: High-power dynamic wavelength stability test:

[0142] Operation: At a constant ambient temperature (25°C), linearly increase the injected current from 1A (low power) to 15A (ultra-high power);

[0143] Measurement: Real-time monitoring of the wavelength redshift caused by increasing injection current;

[0144] Objective: To verify the transient thermal extraction capability of the phonon plate layer and diamond channel under high Joule heat load.

[0145] Step 3: Thermal resistance ( ) and junction temperature monitoring:

[0146] Operation procedure: The active region junction temperature is inverted using the wavelength shift method under full power operation. Calculate the internal thermal resistance of the chip;

[0147] Objective: To quantify the flattening effect of gradient phononic crystals on the central heat island.

[0148] Step 4: Far-field spot (FFP) deformation test:

[0149] Operation procedure: Use a far-field analyzer to capture the slow-axis beam pattern under high power conditions;

[0150] Objective: To observe whether spot splitting or waist widening occurs due to the thermal lensing effect.

[0151] Table 1: Performance Comparison of Laser Chips in the Experimental and Control Groups of this Application

[0152] ;

[0153] Physical locking of wavelength thermal drift: Control groups A and B both showed obvious wavelength redshift, which is an inevitable physical process of the band gap of semiconductor materials shrinking with temperature rise. However, the drift coefficient of experimental group C is close to zero. This strongly proves that the transverse tensile stress generated by the negative Poisson's ratio strain inversion structure 4 accurately cancels the thermal shrinkage of the lattice, achieving in-situ wavelength locking from the physical source, rather than simply relying on external cooling.

[0154] High efficiency of heat flow management: Although diamond was introduced in control group B, the reduction in thermal resistance was limited. The thermal resistance of experimental group C decreased significantly. Due to the central heat island phenomenon, heat is difficult to transfer laterally in traditional structures. This application blocked the longitudinal accumulation of heat by using the gradient phonon crystal heat flow guiding layer 5, and achieved lateral forced suction in conjunction with the diamond channel, thus verifying the effectiveness of the phonon bandgap design.

[0155] Beam quality and mode stability: At high power, the beam of control group A showed significant distortion and linewidth broadening due to the thermal lensing effect, while experimental group C maintained an extremely narrow linewidth and a stable beam shape. This stability comes from a dual suppression mechanism: the heat flow is no longer concentrated below the ridge, and the refractive index distribution remains flat, thereby eliminating the thermal lensing effect and achieving high brightness output.

[0156] The experimental results fully support the technical solution in the application. Through deep coupling of mechanical strain compensation and phonon gradient guidance, the laser chip manufactured by this process breaks the industry norm that the wavelength of high-power lasers inevitably drifts with power, and provides a core light source with overwhelming advantages for high-precision spectral analysis, fiber laser pumping and other fields. Specific Implementation Example 5:

[0158] like Figures 1 to 4 As shown, based on the content of the above specific embodiments, the following content is further disclosed:

[0159] To further verify the feasibility of the technical solution in this application, the following case study is provided:

[0160] Case Study 1: Ultra-High Precision Gas Detection LiDAR System

[0161] Application scenario: In chemical plant environmental monitoring, laser absorption spectroscopy is used to detect methane (C) concentration. Methane has an extremely narrow absorption peak (sub-nanometer level), requiring the laser wavelength to be absolutely stable under different ambient temperatures.

[0162] The challenge is that when traditional lasers switch between high summer temperatures (around 45°C) and low winter temperatures (around -20°C) in the field, the lasing wavelength will drift, causing the laser frequency to jump out of the methane absorption spectrum, thus causing the monitoring system to fail.

[0163] The linkage process of this solution:

[0164] When the ambient temperature rises to 45°C, the negative Poisson's ratio strain reversal structure 4 inside the chip senses the temperature rise, and the ZnO filled inside expands, driving the microbeam to expand to both sides. The tensile stress is applied to the multi-quantum well self-gain active region 3 through the elastic modulus matching layer 11. At this time, the bandgap contraction (red shift) caused by the temperature rise is physically offset by the bandgap widening (blue shift) caused by the lattice stretching.

[0165] Actual results: Experimental monitoring shows that even when the ambient temperature difference reaches 65℃, the lasing wavelength remains locked at around 1653.7nm with a fluctuation of less than 0.05nm. The system does not require a bulky constant temperature control box, the equipment size is reduced by 60%, and the detection accuracy is improved by 10 times.

[0166] Case Study 2: High-Power Fiber Laser Pump Source (Industrial Cutting Application):

[0167] Application scenario: Industrial 10,000-watt fiber lasers require dozens of pump source chips to work together. In order to ensure efficient energy coupling into the fiber, the wavelengths of all chips must be highly consistent and the light spot must not be distorted.

[0168] Challenges: When the chip injection current increases to more than 15A, heat buildup at the chip center creates a strong "thermal lensing effect," which increases the beam divergence angle, reduces fiber coupling efficiency from 85% to below 50%, and makes the chip prone to burnout.

[0169] The linkage process of this solution:

[0170] The gradient phonon crystal heat flow guiding layer 5 acts as a thermal barrier, blocking the vertical upward conduction of heat and protecting the refractive index stability of the ridge waveguide. The heat flow is forcibly guided to the 12°C transverse phonon rapid extraction channels 7 on both sides. The channels with a thermal conductivity of up to 3300W / m·K instantly dissipate the heat. The in-situ thermoelectric feedback regulating electrode 8 finely adjusts the edge temperature field according to real-time power feedback to compensate for nonlinear fluctuations under high current.

[0171] Actual results: Under continuous 15A operation, the thermal resistance decreased from 6.5K / W to 2.2K / W, the far-field spot maintained perfect symmetry, the fiber coupling efficiency remained stable at over 88%, and the chip lifespan was extended by 3 times.

[0172] Case Study 3: 5G / 6G High-Frequency Optical Communication Backbone Transmission

[0173] Application scenario: In ultra-long-distance coherent optical communication, lasers are used as carrier signal sources, requiring extremely narrow spectral linewidths and that the center frequency must not shift during long-term continuous operation;

[0174] Challenges: Under high-speed continuous modulation, traditional chips generate transient temperature pulses due to frequent electron-hole recombination and heat release. This "thermal chirp" leads to spectral broadening (coarser linewidth) and increases the transmission error rate.

[0175] The linkage process of this solution:

[0176] The stress buffer layer 6 absorbs the transient mechanical oscillations generated by high-speed modulation, protecting the integrity of the quantum well. The periodic vacuum hole array of the gradient phonon crystal heat flow guiding layer 5 strongly scatters high-frequency phonons, mitigating the interference of thermal stress on the optical field. The aluminum composition gradient distribution of the N-type Bragg reflector bottom layer 2 ensures that the bottom heat does not flow back to the substrate, maintaining excellent spectral purity.

[0177] Actual results: The chip maintains a spectral linewidth of less than 1MHz at high frequency (compared to 4-5MHz for traditional chips). In transmission tests over thousands of kilometers, the bit error rate was reduced by two orders of magnitude, significantly improving communication capacity.

[0178] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising a reference structure" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0179] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A high-power laser chip with dual thermal drift suppression, characterized in that: The laser chip includes a substrate (1). The upper surface of the substrate (1) is sequentially provided with an N-type Bragg reflection bottom layer (2), a multi-quantum well self-gain active region (3), a stress buffer layer (6), a P-type ohmic contact layer (9), and an N-type back electrode (10). A negative Poisson's ratio strain reversal structure (4) is symmetrically provided on both sides below the P-type ohmic contact layer (9). The negative Poisson's ratio strain reversal structure (4) is connected by a folded microbeam to convert the longitudinal expansion of the chip caused by heat into the lateral tensile strain of the multi-quantum well self-gain active region (3). A gradient phonon crystal heat flow guiding layer (5) is embedded between the P-type ohmic contact layer (9) and the multi-quantum well self-gain active region (3). The gradient phonon crystal heat flow guiding layer (5) changes the mean free path of phonons through the spatial gradient distribution of nanopore density, thereby achieving the directional deflection of heat flow to the side of the chip.

2. The high-power laser chip with dual thermal drift suppression according to claim 1, characterized in that: The negative Poisson's ratio strain reversal structure (4) is composed of a micron-scale double funnel unit array with negative Poisson's ratio effect, and the thermal expansion coefficient of its material is greater than that of the material of the multi-quantum well self-gain active region (3).

3. A high-power laser chip with dual thermal drift suppression according to claim 1, characterized in that: The diameter of the nanopores in the gradient phonon crystal heat flow guiding layer (5) is 50 nanometers to 200 nanometers, and the pore duty cycle gradually decreases from the center of the waveguide to both sides, forming a phonon refractive index gradient.

4. A high-power laser chip with dual thermal drift suppression according to claim 1, characterized in that: The sidewall of the negative Poisson ratio strain inversion structure (4) is wrapped with a transverse phonon rapid extraction channel (7), which is made of diamond material purified by carbon-12 isotope.

5. A high-power laser chip with dual thermal drift suppression according to claim 1, characterized in that: An elastic modulus matching layer is provided between the multi-quantum well self-gain active region (3) and the negative Poisson's ratio strain inversion structure (4) to transfer stress and prevent interface dislocations.

6. A high-power laser chip with dual thermal drift suppression according to claim 1, characterized in that: An in-situ thermoelectric feedback regulating electrode (8) is provided above the P-type ohmic contact layer (9). The in-situ thermoelectric feedback regulating electrode (8) adjusts the local current injection in real time according to the wavelength signal fed back from the chip end face.

7. The fabrication process of a high-power laser chip with dual thermal drift suppression according to any one of claims 1-6, characterized in that: The preparation process includes the following steps: Sp1: An N-type Bragg reflector substrate (2) and a multi-quantum well self-gain active region (3) are deposited on a substrate (1) by an epitaxial growth process. Sp2: Micro-nano slots with negative Poisson's ratio structures are fabricated on both sides of the multi-quantum-well self-gain active region (3) using focused ion beam etching or nanoimprinting techniques; Sp3: High expansion coefficient material is filled in micro-nano slots using selective region epitaxy to form a negative Poisson's ratio strain inversion structure (4). Sp4: During the growth of the upper cladding layer, a gradient distribution of nanopore arrays is manufactured by block copolymer self-assembly process to form a gradient phonon crystal heat flow guiding layer (5). Sp5: A transverse phonon rapid extraction channel was constructed by depositing isotopically purified diamond thin films on the chip side using plasma-enhanced chemical vapor deposition (7). Sp6: Prepare a P-type ohmic contact layer (9) and an in-situ thermoelectric feedback regulating electrode (8); Sp7: Thinning the back side of the substrate and fabricating an N-type back electrode (10).

8. The high-power laser chip with dual thermal drift suppression and its fabrication process according to claim 7, characterized in that: The micro-nano slots in Sp2 penetrate the stress buffer layer (6) and terminate 100 nanometers above the upper surface of the multi-quantum well self-gain active region (3). The gradient distribution in Sp4 controls the formation position and diameter of the pores by changing the ratio of hydrophilic groups in the copolymer.

9. A high-power laser chip with dual thermal drift suppression and its fabrication process according to claim 7, characterized in that: The high expansion coefficient material filled in the Sp3 is zinc oxide or indium antimonide. During the filling process, the deposition rate is precisely controlled to ensure that there are no air bubbles inside the micro-nano trenches, thus achieving linear transmission of strain.

10. A high-power laser chip with dual thermal drift suppression and its fabrication process according to claim 7, characterized in that: Before depositing the diamond film in Sp5, hydrogen plasma surface treatment is required to improve the interfacial thermal conductivity between the transverse phonon rapid extraction channel (7) and the negative Poisson's ratio strain reversal structure (4).

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