A multi-super-capacity branch layered decoupling equalization control method of a static synchronous compensator

Abstract

The application provides a multi-super-capacitor branch layered decoupling equalization control method of a static synchronous compensator, relates to the fields of power electronic technology and flexible DC power transmission technology, and comprises the following steps: collecting voltage information of each super-capacitor unit in a super-capacitor branch, and determining a voltage reference value for equalization control; based on the determined voltage reference value, discharging equalization control is performed on each super-capacitor unit, so that the voltage of all super-capacitor units in the super-capacitor branch is equalized; on the basis of completing the voltage equalization of all super-capacitor units, the DC port voltage of the super-capacitor branch is detected, and the deviation of the DC port voltage from a preset target voltage is calculated; according to the calculated deviation, the number of super-capacitor half-bridge sub-modules required to be put into operation to maintain the stability of the port voltage is calculated through closed-loop adjustment. The application can realize full-level voltage equalization and collaborative stability control among super-capacitor units, super-capacitor clusters and branches.

Description

Technical Field

[0001] This invention relates to the fields of power electronics technology and flexible DC transmission technology, and in particular to a hierarchical decoupling equalization control method for multiple supercapacitor branches of a static synchronous condenser. Background Technology

[0002] Static synchronous condensers (SSCs), with grid-mode (GFM) control at their core, have become crucial devices for ensuring grid voltage stability, providing active power support, and offering inertial response in scenarios such as renewable energy-friendly grid integration, grid peak-valley regulation, and distributed power generation absorption. A typical topology includes a front-end modular multilevel converter (MMC) and a downstream DC bus-connected supercapacitor energy storage system. The downstream system utilizes multiple supercapacitor branches connected in parallel to achieve large-scale energy storage, providing the SSC with flexible active power regulation capabilities. This makes it a key execution unit for fulfilling its grid support role.

[0003] In the actual operation of SSC multi-supercapacitor branches, the large-scale integration of supercapacitors faces the following technical bottlenecks: existing equalization control technologies only focus on supercapacitor cluster-level voltage equalization, without covering the most basic energy storage unit—the individual supercapacitor. Individual supercapacitors have inherent deviations in parameters such as capacity, internal resistance, and leakage current, directly leading to voltage imbalances among individual supercapacitors. This deficiency causes the following problems: localized overheating due to individual voltage imbalance accelerates capacitor aging, reduces operational reliability and lifespan, and limits large-scale applications; moreover, individual imbalance gradually amplifies inter-cluster voltage deviations, and coupled with the asynchronous timing of multi-branch modulation commands and drive signals, it easily induces inter-branch circulating currents, worsens cluster-level equalization effects, and may even cause DC field circuit breakers to trip erroneously, weakening the SSC grid support capacity and threatening grid security.

[0004] Existing equalization control schemes either only design fixed module switching strategies for supercapacitor clusters, failing to address voltage imbalances caused by inconsistencies between individual cells at their root; or they do not consider synchronous coordination among multiple branches, making it difficult to effectively suppress circulating current risks. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a hierarchical decoupling equalization control method for multiple supercapacitor branches of a static synchronous condenser, which can realize full-level voltage equalization and coordinated stability control among supercapacitor cells, supercapacitor clusters and branches.

[0006] To solve the above-mentioned technical problems, the technical solution of the present invention is as follows:

[0007] A hierarchical decoupling equalization control method for multiple overcapacity branches of a stationary synchronous phase converter, the method comprising:

[0008] Collect voltage information of each overcapacitor cell in the overcapacitor branch and determine the voltage reference value used for equalization control;

[0009] Based on a determined voltage reference value, discharge equalization control is performed on each supercapacitor cell to achieve voltage equalization of all supercapacitor cells in the supercapacitor branch.

[0010] After balancing the voltage of all supercapacitor cells, the DC port voltage of the supercapacitor branch is detected, and the deviation between the DC port voltage and the preset target voltage is calculated. Based on the calculated deviation, the number of supercapacitor half-bridge sub-modules required to be put into operation to maintain the stability of the port voltage is calculated through closed-loop regulation.

[0011] Based on the calculated number of supercapacitive half-bridge sub-modules and the detected real-time current direction of the supercapacitive branch, all available supercapacitive half-bridge sub-modules are sorted and selectively switched to achieve voltage balance among the supercapacitive clusters within the supercapacitive branch and complete cluster-level balance control.

[0012] Based on the completion of cluster-level equalization control, the main controller generates a unified modulation wave command and synchronously sends it to the branch management unit corresponding to each overcapacity branch; it coordinates the branch management units to generate and latch synchronous drive commands at the same time based on the unified modulation wave command.

[0013] Each branch management unit will issue and execute synchronous drive commands to control the overcapacity half-bridge submodules in all overcapacity branches to perform unified operation, so as to suppress the circulating current between branches and realize the coordinated and stable operation of the multiple overcapacity branches.

[0014] Furthermore, the voltage information of each overcapacitor cell in the overcapacitor branch is collected, and the voltage reference value used for equalization control is determined, including:

[0015] The real-time voltage of the supercapacitor cell to which the management unit belongs is collected through the management unit corresponding to each supercapacitor module;

[0016] The real-time voltages of all overcapacitive cells within the overcapacitive branch are collected, and the average and minimum voltage values ​​of the overcapacitive branch are calculated.

[0017] The real-time current magnitude of the overcapacity branch is detected, and the real-time current magnitude is compared with a preset current threshold to obtain the comparison result;

[0018] Based on the comparison between the real-time current magnitude and the preset current threshold, one of the calculated average voltage value and the minimum voltage value is dynamically selected as the voltage reference value for discharge equalization control.

[0019] Furthermore, based on a determined voltage reference value, discharge equalization control is performed on each supercapacitor cell to achieve voltage equalization of all supercapacitor cells within the supercapacitor branch, including:

[0020] Obtain a defined voltage reference value, and compare the real-time voltage of each supercapacitor cell with the voltage reference value to obtain the real-time voltage difference corresponding to each supercapacitor cell;

[0021] The real-time voltage difference corresponding to each supercapacitor cell is compared with the first set threshold.

[0022] When the real-time voltage difference corresponding to a certain supercapacitor cell is greater than the first set threshold, the discharge circuit connected in parallel with the supercapacitor cell is turned on so that the supercapacitor cell discharges through the equalization resistor.

[0023] During the discharge process, the real-time voltage difference of the supercapacitor cell is continuously monitored. When the real-time voltage difference drops below the second set threshold, the discharge circuit is shut off to complete the discharge equalization control of the supercapacitor cell.

[0024] For each supercapacitor cell in the supercapacitor branch, the operations of obtaining the corresponding real-time voltage difference, performing threshold comparison, and controlling the conduction and shutdown of the discharge circuit are repeatedly executed until the real-time voltage difference of all supercapacitor cells is maintained within the second set threshold, thereby achieving voltage balance of all supercapacitor cells in the supercapacitor branch.

[0025] Furthermore, after achieving voltage balancing for all overcapacitor cells, the DC port voltage of the overcapacitor branch is detected, and the deviation between the DC port voltage and the preset target voltage is calculated. Based on the calculated deviation, the number of overcapacitor half-bridge submodules required to maintain stable port voltage is calculated through closed-loop regulation, including:

[0026] After the supercapacitor branch completes voltage balancing of all supercapacitor cells, the real-time DC port voltage of the supercapacitor branch is detected.

[0027] The detected real-time DC port voltage is compared with the preset target voltage value to calculate the real-time voltage deviation value.

[0028] The real-time voltage deviation value is input to the closed-loop regulator;

[0029] The real-time voltage deviation value is processed by a closed-loop regulator to calculate the target number of overcapacitance half-bridge submodules that need to be put into operation to maintain the stability of the DC port voltage.

[0030] Furthermore, the real-time voltage deviation value is processed by a closed-loop regulator to calculate in real time the target number of overcapacitance half-bridge submodules that need to be put into operation to maintain DC port voltage stability, including:

[0031] Based on the real-time voltage deviation value, the proportional term output is obtained by calculating through the proportional element of the closed-loop regulator;

[0032] Based on the real-time voltage deviation value, the integral term output is obtained by calculating through the integral element of the closed-loop regulator.

[0033] The total controlled output value of the closed-loop controller is obtained by summing the proportional term output and the integral term output.

[0034] Based on the total regulation output value of the closed-loop regulator, determine and output the integer target number of overcapacitance half-bridge submodules that need to be put into operation to maintain the stability of the DC port voltage.

[0035] Furthermore, based on the calculated number of overcapacitive half-bridge submodules and the detected real-time current direction of the overcapacitive branch, all available overcapacitive half-bridge submodules are sorted and selectively switched to achieve voltage balance among the overcapacitive clusters within the overcapacitive branch, thus completing cluster-level equalization control, including:

[0036] Obtain the calculated integer target number of the overcapacitance half-bridge submodule, and simultaneously detect the real-time current direction of the overcapacitance branch;

[0037] The sorting rules are determined based on the detected real-time current direction, and the capacitor voltage values ​​of all available supercapacitor half-bridge submodules in the supercapacitor branch are sorted according to the determined sorting rules to obtain an ordered submodule sequence.

[0038] Based on the number of integer targets obtained, select a corresponding number of preceding submodules from the obtained ordered submodule sequence;

[0039] The selected preceding submodule is put into working state, and the remaining submodules in the ordered submodule sequence are kept in bypass state, thereby realizing voltage balancing among the supercapacitive clusters within the supercapacitive branch and completing cluster-level balancing control.

[0040] Furthermore, based on the completion of cluster-level equalization control, the main controller generates a unified modulation wave command and synchronously sends it to the branch management unit corresponding to each overcapacity branch; it coordinates each branch management unit to generate and latch synchronous drive commands at the same time based on the unified modulation wave command, including:

[0041] After completing the cluster-level equalization control of each overcapacity branch, the main controller generates a unified modulation wave command based on the active and reactive power support requirements of the power grid.

[0042] Through the synchronous communication link between the main controller and each branch management unit, the unified modulation wave command is synchronously sent to the branch management unit corresponding to all overcapacity branches.

[0043] Based on the received unified modulation wave command and the electrical state of the overcapacity branch corresponding to each branch management unit, each branch management unit generates an initial drive command for the overcapacity branch.

[0044] Coordination is achieved through high-frequency synchronization signals between branch management units, enabling all branch management units to perform latching operations on their generated initial drive commands at the same time, thereby obtaining and maintaining synchronized final drive commands.

[0045] Furthermore, each branch management unit will issue and execute synchronized drive commands to control the overcapacity half-bridge submodules in all overcapacity branches to perform unified operation, thereby suppressing circulating currents between branches and achieving coordinated and stable operation of the multiple overcapacity branches, including:

[0046] Each branch management unit receives the final drive command for synchronization;

[0047] Each branch management unit will receive the final synchronous drive command and then send it to the cluster management unit under its jurisdiction through the communication link between the branch management unit and the cluster management unit.

[0048] Each cluster management unit parses and generates a corresponding power semiconductor switch control signal according to the received drive command, so as to control one or more supercapacitive half-bridge sub-modules under each cluster management unit to perform a unified switching operation of the enabled, bypassed or locked state.

[0049] All overcapacity half-bridge submodules in the overcapacity branches, based on the synchronized final drive command, perform unified switching operations for activation, bypass, or lockout states within the same control cycle, thereby suppressing inter-branch circulating currents caused by differences in action timing and achieving coordinated and stable operation of the multiple overcapacity branches.

[0050] The above-described solution of the present invention has at least the following beneficial effects:

[0051] Because it employs technologies such as supercapacitor cell voltage acquisition and dynamic reference selection, and discharge equalization control, it overcomes the voltage imbalance problem caused by the lack of coverage of the supercapacitor cell level in existing technologies, thereby ensuring the operational reliability of supercapacitor cells and extending their service life. Because it adopts closed-loop regulation based on port voltage deviation and supercapacitor half-bridge submodule sequencing and switching technology, it overcomes the problem that cluster-level fixed module control cannot adapt to the active power demand of the grid side, thereby achieving voltage equalization and flexible active power support between supercapacitor clusters. Because it adopts a collaborative control technology of unified modulation wave distribution by the main controller and synchronous latching of drive commands by the branch management unit, it overcomes the circulating current problem caused by asynchronous timing of multiple branches, thereby effectively suppressing inter-branch circulating current, improving the collaborative stable operation capability of multiple supercapacitor branches, and effectively ensuring the voltage stability and active power support effect of the static synchronous condenser on the power grid. Attached Figure Description

[0052] Figure 1This is a flowchart illustrating a multi-overcapacity branch hierarchical decoupling equalization control method for a static synchronous condenser provided in an embodiment of the present invention. Detailed Implementation

[0053] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0054] like Figure 1 As shown, an embodiment of the present invention proposes a hierarchical decoupling equalization control method for multiple overcapacity branches of a stationary synchronous condenser, the method comprising the following steps:

[0055] Step 1: Collect the voltage information of each supercapacitor cell in the supercapacitor branch and determine the voltage reference value used for equalization control.

[0056] Step 2: Based on the determined voltage reference value, discharge equalization control is performed on each supercapacitor cell to achieve voltage equalization of all supercapacitor cells in the supercapacitor branch.

[0057] Step 3: After completing the voltage balancing of all supercapacitor cells, detect the DC port voltage of the supercapacitor branch and calculate the deviation between the DC port voltage and the preset target voltage. Based on the calculated deviation, calculate the number of supercapacitor half-bridge sub-modules required to maintain stable port voltage through closed-loop regulation.

[0058] Step 4: Based on the calculated number of supercapacitive half-bridge sub-modules and the detected real-time current direction of the supercapacitive branch, sort and selectively switch all available supercapacitive half-bridge sub-modules to achieve voltage balance among the supercapacitive clusters within the supercapacitive branch and complete cluster-level balance control.

[0059] Step 5: Based on the completion of cluster-level equalization control, the main controller generates a unified modulation wave command and synchronously sends it to the branch management unit corresponding to each overcapacity branch; coordinates each branch management unit to generate and latch synchronous drive commands at the same time based on the unified modulation wave command.

[0060] Step 6: Each branch management unit will issue and execute synchronous drive commands to control the overcapacity half-bridge submodules in all overcapacity branches to perform unified operation, so as to suppress the circulating current between branches and realize the coordinated and stable operation of the multiple overcapacity branches.

[0061] In this embodiment of the invention, full-level balanced control between supercapacitor cells, supercapacitor clusters, and branches is achieved, ensuring consistent voltage across supercapacitor cells, effectively reducing local overheating and capacitor aging, and extending the lifespan of supercapacitors. The adaptive switching of the supercapacitor cluster half-bridge submodule can accurately match the active power demand on the grid side without requiring additional capacitor values, thus reducing operating costs. Through unified command issuance by the main controller and synchronous coordination with the branch management unit, circulating currents between branches are effectively suppressed, preventing false tripping of DC circuit breakers. Overall, the stability and reliability of the static synchronous condenser operation are improved, enhancing its voltage stability support and inertial response capability for the power grid, and providing a guarantee for the safe operation of the new power system.

[0062] In a preferred embodiment of the present invention, step 1 above may include:

[0063] Step 1.1: Collect the real-time voltage of the supercapacitor cell to which the management unit belongs through the management unit corresponding to each supercapacitor module. Specifically, this includes: each supercapacitor module is configured with an independent supercapacitor module management unit (Cell Management Unit). The independent supercapacitor module management unit (CMU) incorporates high-precision voltage and temperature sensors. It synchronously acquires the real-time voltage (Vcell) and temperature of each supercapacitor cell within its supercapacitor module at a fixed period of 100μs. The acquired raw analog signal first passes through a second-order RC low-pass filter circuit to remove high-frequency interference from the power grid and sensor noise. Then, it is converted into a digital signal by a built-in 16-bit analog-to-digital converter (ADC) module, ensuring data acquisition accuracy at the millivolt level. Subsequently, the CMU establishes a bidirectional communication link with the supercapacitor cluster management unit (CCMU) via a ring topology daisy-chain communication architecture. This ring topology daisy-chain communication architecture supports bidirectional data transmission. If a communication failure occurs at a certain node, data can automatically switch to the reverse link for transmission, ensuring that the acquired voltage and temperature digital signals are transmitted to the CCMU in real-time and without loss, providing highly reliable raw data for the formulation of equalization control strategies.

[0064] Step 1.2: Collect the real-time voltages of all supercapacitor cells within the supercapacitor branch and calculate the average and minimum voltage values ​​of the supercapacitor branch. Specifically, the Cluster Control and Management Unit (CCMU) receives the digital voltage data of the supercapacitor cells transmitted by each CMU through a daisy-chain loop, with a timing sequence of 100μs, which is completely synchronized with the CMU's acquisition cycle. First, the MCCMU verifies the validity of each set of voltage data, removing overvoltage and undervoltage abnormal data that exceed ±10% of the rated voltage of the supercapacitor cell to avoid abnormal data affecting subsequent calculation results. After verification, data processing is performed according to the logic of cluster first, then branch: For each supercapacitor cluster, the arithmetic mean of the voltages of all valid supercapacitor cells within the cluster is calculated to obtain the cluster average voltage Vavg. 1. Simultaneously, the minimum voltage Vmin1 within the cluster is selected; then, the effective voltage data of all supercapacitor clusters are summarized, and the arithmetic mean Vavg and minimum Vmin of the voltage of all supercapacitor cells in the entire supercapacitor branch are calculated; at the same time, the MCCMU obtains the real-time current ibrn of the branch through the current acquisition module at the back end of the smoothing reactor of the supercapacitor branch, and encapsulates the calculated Vavg, Vmin, Vavg1, Vmin1 and the acquired ibrn into standard UDP data frames, and updates the data to the supercapacitor cluster management unit terminal (Master Cluster Control and Management Unit, abbreviated as MCCMU) every 200μs according to the preset industrial Ethernet communication protocol, to ensure that the reference value selection can dynamically adapt to the changes in the operating status of the supercapacitor branch.

[0065] Step 1.3: Detect the real-time current magnitude of the overcapacitance branch and compare it with a preset current threshold to obtain the comparison result. Specifically, this includes: After the overcapacitance cluster management unit (CCMU) receives the UDP data frame transmitted by the MCCMU, it first extracts the overcapacitance branch current ibrn data. This current data has been processed by the low-pass filter built into the current acquisition module to remove high-frequency ripple interference and ensure the stability of current detection; the CCMU's built-in high-speed comparator module compares the extracted real-time branch current ibrn with a preset 10A current threshold. This threshold is based on a combination of the rated discharge current of the overcapacitance cell, ... The rated power of the equalizing resistor and the dynamic response speed requirements of the system are determined to avoid resistor overload damage during the equalization process and ensure the response efficiency of the equalization control. The comparison process is synchronized with the voltage data update cycle and is executed every 200μs to ensure a high degree of matching between the current state judgment and the voltage state. After the comparison, two clear operating condition judgment results are output: when ibrn > 10A, it is judged as a dynamic high current operating condition, in which case the equalization speed must be prioritized; when ibrn ≤ 10A, it is judged as a steady-state low current operating condition, in which case the equalization accuracy must be emphasized. The results of the two operating conditions directly trigger the corresponding reference value selection logic.

[0066] Step 1.4, according to the comparison result between the real-time current magnitude and the preset current threshold, dynamically select one of the calculated average voltage value and the minimum voltage value as the voltage reference value for discharging equalization control, which specifically includes: the voltage deviation caused by the inherent differences in parameters such as the capacitance and internal resistance of the supercapacitor monomers can be accurately quantified by the formula Precisely quantified, where in the formula d 1. d 2 is the capacitance deviation rate between any two supercapacitor monomers, u is the rated voltage of the supercapacitor, Δ u is the voltage deviation between the two monomers, and this deviation will cause the supercapacitor monomers to heat up and shorten their lifespan. Therefore, it is necessary to select the reference value针对性 to offset the deviation; First, the CCMU detects the mechanical bypass state of the current supercapacitor cluster in real time through the status feedback pin of the supercapacitor cluster half-bridge power sub-module. When the feedback signal is at a high level, it indicates that the cluster is in the bypass state, and when it is at a low level, it indicates that it is not bypassed; If it is determined that the dynamic large current condition ibrn > 10A, then select the minimum value reference to achieve fast equalization: When the current supercapacitor cluster is bypassed, use the minimum voltage Vmin1 within the cluster as the reference, and set the reference threshold to Vth3 to adapt to the need for fast overvoltage suppression under large current; When it is not bypassed, use the minimum voltage Vmin of the branch as the reference, and the threshold is also Vth3; If it is determined that the steady-state small current condition ibrn ≤ 10A, then select the average value reference to achieve precise equalization: When the current supercapacitor cluster is bypassed, use the average voltage Vavg1 within the cluster as the reference, and set the threshold to Vth1; When it is not bypassed, use the average voltage Vavg of the branch as the reference, and the threshold is also Vth1; Among them, the reference voltage difference strictly follows the relationship of Vth2 < Vth1 = Vth4 < Vth3. Vth2 is used as the cut-off threshold for the completion of the average value reference equalization, and Vth4 is used as the cut-off threshold for the completion of the minimum value reference equalization, ensuring that a fast start and precise cut-off equalization effect can be achieved under different working conditions, and the reference value is updated every 200 μs with the newly collected data to dynamically adapt to the changes in the operating state of the supercapacitor branch.

[0067] In the embodiment of the present invention, the supercapacitor module management unit accurately collects the real-time voltages of each supercapacitor monomer, ensuring the accuracy and integrity of the original data; After summarization and calculation, the average voltage value and the minimum voltage value of the branch are obtained, providing key parameter support for the selection of the equalization reference; By combining the comparison of the real-time branch current and the preset threshold to distinguish the operating conditions, the voltage reference value can dynamically adapt to different scenarios of large and small currents, avoiding the problems of insufficient equalization accuracy or low efficiency caused by a fixed reference; Finally, by dynamically selecting the appropriate voltage reference value, a reasonable and reliable basis is provided for the discharging equalization control of the supercapacitor monomers, effectively improving the pertinence and effectiveness of the voltage equalization of the supercapacitor monomers, laying a foundation for the full-level equalization control between the supercapacitor clusters and branches, and further ensuring the stability and reliability of the operation of the static synchronous compensator with multiple supercapacitor branches.

[0068] In a preferred embodiment of the present invention, step 2 above may include:

[0069] Step 2.1: Obtain the determined voltage reference value and compare the real-time voltage of each supercapacitor cell with the voltage reference value to obtain the real-time voltage difference corresponding to each supercapacitor cell. Specifically, this includes: first, completing the self-check of the supercapacitor cell fault and the status verification of the equalization circuit, confirming that there are no over- or under-voltage faults and no short circuit or open circuit abnormalities in the equalization circuit, and then activating the equalization control process; extracting the determined voltage reference value from the real-time updated operating condition data, which is Vmin or Vmin1 under the dynamic high current condition ibrn>10A, and Vavg or Vavg1 under the steady-state low current condition ibrn≤10A. This reference value is updated synchronously every 200μs with the changes in the supercapacitor branch current and the supercapacitor cluster bypass status to ensure real-time matching with the operating status; synchronously receiving the real-time voltage Vcell of each supercapacitor cell uploaded by the CMU of each supercapacitor module through a ring topology daisy link, performing CRC-16 verification on the data during the receiving process, discarding abnormal data that fails the verification, and retaining only the valid Vcell for calculation; performing difference calculation on each valid Vcell and the corresponding reference value to obtain the real-time voltage difference Δ. u This voltage difference is directly caused by the capacity deviation of the overcapacitor cells, and its quantification relationship strictly follows the formula. In the formula d 1. d 2 represents the capacity deviation rate between any two supercapacitor cells. u The rated voltage of the supercapacitor, Δ u It intuitively reflects the degree of deviation between the current unit voltage and the reference value, providing a quantitative basis for equalization control.

[0070] Step 2.2, compare the real-time voltage difference corresponding to each ultracapacitor monomer with the first set threshold, which specifically includes: matching the corresponding first set threshold according to the working condition determination result. All thresholds strictly follow the fixed relationship of Vth2 < Vth1 = Vth4 < Vth3, and the setting basis fully combines the characteristics of ultracapacitor monomers, industry standards, circuit parameters and working condition requirements to ensure the safety and effectiveness of the balancing control; under the dynamic large current condition ibrn > 10A, the first set threshold is Vth3, and the setting of this threshold is mainly based on three aspects: first, referring to the requirement in the technical specification of the active balancing circuit of capacitor-type batteries that the maximum allowable voltage difference between adjacent monomers does not exceed 800mV, and combining the rated voltage of the ultracapacitor monomer, such as 2.7V, taking 5% to 8% of the rated voltage as the overvoltage trigger reference to avoid local overheating caused by excessive voltage difference; second, adapting to the Joule heat effect generated by the equivalent series resistance ESR of the ultracapacitor monomer under large current. Referring to the data in the white paper of the International Energy Storage Conference, the life of the unbalanced ultracapacitor group is shortened by up to 40% under the large current condition. Therefore, Vth3 needs to be set higher than the steady-state threshold to ensure rapid start of balancing to suppress temperature rise; third, matching the rated power of the balancing resistor. According to Ohm's law , (where U is voltage and R is resistance) when the resistance value of the balancing resistor is fixed, Vth3 needs to be controlled within the voltage range corresponding to the safe power of the resistor to avoid damage to the resistor due to overload during the discharge process.

[0071] Under the steady-state small current condition ibrn ≤ 10A, the first set threshold is Vth1, and its setting basis also takes into account both accuracy and reliability: first, follow the industry general balancing threshold standard, refer to the recommended starting threshold range of 30mV to 50mV in the technical specification of the active balancing circuit of capacitor-type batteries, and combine the voltage consistency requirement of the ultracapacitor monomer to select the intermediate value of 40mV as the basic threshold to ensure the balancing accuracy; second, combine the cycle performance requirement of the ultracapacitor monomer. According to the CESA group standard, the capacity of the electric double layer supercapacitor after cycling needs to be not less than 90% of the initial value. The setting of Vth1 needs to avoid the ineffective energy loss caused by frequent start and stop of balancing and extend the service life of the ultracapacitor monomer; finally, consider the influence of temperature on the threshold. Referring to the BMS temperature detection design logic, the temperature of the ultracapacitor module is real-time fed back through the NTC sensor. When the temperature is higher than 60°C, Vth1 is automatically reduced by 5mV, and when it is lower than -20°C, it is increased by 5mV to adapt to the balancing requirements in the wide temperature environment.

[0072] All threshold parameters have been pre-stored in the ultracapacitor cluster management unit CCMU, and online fine-tuning through the industrial bus is supported to adapt to the parameter deviation of different batches of ultracapacitor monomers; at a frequency of once every 100 μs, compare the real-time voltage difference Δ u of each ultracapacitor monomer with the first set threshold corresponding to the current working condition one by one. When comparing, the overvoltage priority principle is adopted, and Δ uFor overcapacitated cells that significantly exceed the threshold, ensure rapid regulation of cells with high overpressure; simultaneously, record the comparison results for each cell, marking the cell ID that requires equilibration and its corresponding Δ. u The numerical values ​​are used to form a balanced task list, providing a clear basis for subsequent discharge loop control.

[0073] Step 2.3: When the real-time voltage difference corresponding to a certain supercapacitor cell is greater than the first set threshold, control the discharge circuit connected in parallel with the supercapacitor cell to be turned on, so that the supercapacitor cell discharges through the balancing resistor. Specifically, this includes: when the real-time voltage difference Δ of a certain supercapacitor cell is detected from the balancing task list... u When the current operating condition exceeds the first set threshold, the equalization circuit corresponding to the unit is pre-tested to confirm that the equalization resistor is free from overload and short-circuit abnormalities, and the power MOSFET is fault-free. Then, a high-level drive signal with the unit ID code is generated. This drive signal is transmitted to the CMU of the corresponding supercapacitor unit via a daisy-chain loop at a set rate, such as 1 Mbps. Differential signaling is used during transmission to resist electromagnetic interference. After receiving the drive signal, the CMU controls the power MOSFET switch connected in parallel with the supercapacitor unit to turn on according to a preset timing sequence (within 5 μs after signal reception), forming a closed discharge circuit with the supercapacitor unit, equalization resistor, and MOSFET. The power rating of the equalization resistor is matched to the rated voltage and maximum allowable discharge current of the supercapacitor unit to ensure that the resistor temperature rise is controlled within a safe range during discharge. Simultaneously, the discharge circuit has a built-in current-limiting structure to prevent excessive current surges that could damage components during turn-on. Excess energy accumulated in the supercapacitor unit due to capacity deviation is dissipated in a controllable manner through the equalization resistor, causing the voltage to gradually decrease. The voltage difference Δ u It then shrinks synchronously until it approaches the first set threshold.

[0074] Step 2.4: During the discharge process, the real-time voltage difference of the supercapacitor cell is continuously monitored. When the real-time voltage difference drops below the second set threshold, the discharge circuit is shut off to complete the discharge equalization control of the supercapacitor cell. Specifically, during the discharge process, the CMU continuously collects the real-time voltage Vcell of the supercapacitor cell every 100μs. The collected data is first processed by a second-order RC filter to filter out the high-frequency noise generated by the equalization resistor and MOSFET switching in the discharge circuit, and then synchronously transmitted to the CCMU. The CCMU updates the voltage difference Δ in real time based on the voltage reference value corresponding to the cell. u The calculation results should be taken into account, and the MOSFET on-state voltage drop needs to be compensated during the calculation, typically by 0.1 to 0.2V, to avoid the voltage drop causing Δ uCalculate the deviation; match the corresponding second set threshold according to the current working condition: under the dynamic large current condition where ibrn > 10A, it is Vth4, and this threshold is equal to Vth1, that is, Vth1 = Vth4. Based on the steady-state balance accuracy setting of the minimum value reference, ensure that the single-cell voltage deviation after balancing is controllable under the large current condition; under the steady-state small current condition where ibrn ≤ 10A, it is Vth2, and this threshold is the minimum value among all reference pressure differences, Vth2 < Vth1 = Vth4 < Vth3, aiming to achieve high-precision consistency of the over-capacity single-cell voltage.

[0075] Monitor Δ in real time u The relationship with the second set threshold. When Δ u If it is lower than the second set threshold for two consecutive acquisition cycles (200 μs), the CCMU immediately generates a low-level turn-off signal with an acknowledgment code. The signal is transmitted to the CMU through the ring-shaped daisy chain. The CMU completes the MOSFET turn-off within 3 μs after receiving the signal, compensating for the turn-off delay of the switching tube, about 1 to 2 μs, to ensure accurate turn-off timing; after turn-off, enter a 50 μs buffer monitoring period. During this period, continuously collect the single-cell voltage. If the voltage rebounds and causes Δ u Exceeds the second set threshold again and lasts for one acquisition cycle, the discharge control will be restarted; if the voltage fluctuation amplitude is controlled within ±2 mV, it is determined that the balance is stable, record the balance completion status of this single cell and remove its ID from the balance task list; at the same time, the CCMU monitors the temperature rise data of the balance resistor in real time, collected through the NTC sensor. If the temperature rise exceeds 40 °C, pause the balance of this loop and resume it after the temperature drops to the safe range to avoid damage to the resistor due to overload.

[0076] Step 2.5, for each over-capacity single cell in the over-capacity branch, repeat the operations of obtaining the corresponding real-time voltage difference, comparing with the threshold, and controlling the conduction and turn-off of the discharge loop until the real-time voltage differences of all over-capacity single cells in the over-capacity branch are maintained within the second set threshold, so as to achieve the voltage balance of all over-capacity single cells in the over-capacity branch. Specifically, it includes: performing operations according to the principle of batch balance + polling scheduling. Among them, batch balance is to divide all over-capacity single cells in the over-capacity branch into several batches according to the computing power of the over-capacity cluster management unit CCMU and the communication bandwidth of the ring-shaped daisy chain. The number of each batch is adapted to the processing capacity within a 100 μs acquisition cycle to avoid communication congestion or calculation delay caused by starting too many discharge loops at the same time; polling scheduling is to cycle through each batch of single cells in order of batches to execute the balance process, ensure that no single cell is omitted, and the balance opportunities for each batch are equal; synchronously receive the real-time voltage data of all over-capacity single cells. For the single cells that have not completed the balance, maintain high-frequency monitoring and control once every 100 μs, and strictly execute the voltage difference Δ according to the timing uCalculation, threshold comparison, and discharge circuit on / off control; for cells that have been equalized, the monitoring period is adjusted to 500μs. If voltage fluctuations exceeding ±3mV are detected, high-frequency monitoring is immediately restored to prevent voltage drift.

[0077] During the cyclic execution, for Δ after 5 consecutive equilibrations u Individual cells that still exceed the second set threshold are marked as abnormal fault cells. Fault information is reported to the overcapacity cluster management unit terminal MCCMU via CCMU, and equalization operations on that cell are suspended to avoid unnecessary energy loss and component damage. The percentage of cells within the branch that have completed equalization is calculated in real time. When the percentage reaches 100%, the overall equalization effect of the branch is further determined: the ΔE ratio of all overcapacity cells... u All values ​​remain within the corresponding second set threshold, with no fluctuations for three consecutive data acquisition cycles (300μs); the standard deviation of the voltage of all overcapacitor cells in the branch is less than 5mV; the voltage fluctuation range of the overcapacitor branch port does not exceed ±0.5% of the rated voltage; after meeting the above conditions, it is determined that all overcapacitor cells in the overcapacitor branch have achieved voltage equalization, and the CCMU sends an equalization completion signal to the subsequent cluster-level equalization control module. The signal contains statistical data such as the average voltage of the branch after equalization and the maximum and minimum individual cell voltage difference, providing an accurate initial state reference for cluster-level equalization control.

[0078] In this embodiment of the invention, by acquiring the voltage reference value of the dynamically adapted operating condition, the real-time voltage difference between each supercapacitor cell and the reference value is accurately calculated. Targeted comparisons are then performed using a tiered threshold. Excess energy in the supercapacitor cells is consumed through precise on / off control of the discharge circuit. Furthermore, a balancing operation is cyclically performed on all supercapacitor cells within the branch until the voltage difference between all cells is maintained within the set threshold. This effectively overcomes the voltage imbalance problem caused by the lack of coverage of the supercapacitor cell level in existing technologies, avoids potential hazards such as localized overheating and accelerated aging caused by cell voltage imbalance, effectively improves the voltage consistency and operational reliability of supercapacitor cells, extends the service life of supercapacitors, and provides a stable cell voltage foundation for supercapacitor cluster-level balancing and inter-branch collaborative balancing, further ensuring the overall operational stability of the static synchronous condenser multi-supercapacitor branch system.

[0079] In a preferred embodiment of the present invention, step 3 above may include:

[0080] Step 3.1: After the supercapacitor branch completes voltage equalization of all supercapacitor cells, the real-time DC port voltage of the supercapacitor branch is detected. Specifically, this includes: After the supercapacitor branch completes voltage equalization of all supercapacitor cells, the supercapacitor cluster management unit terminal (MCCMU) receives an equalization completion signal from the supercapacitor cluster management unit (CCMU). This signal contains core verification data such as the average voltage of the equalized branch, the maximum and minimum individual cell voltage difference must be ≤5mV, and the standard deviation of all individual cell voltages must be <5mV. The MCCMU verifies these data one by one, and only after confirming that the individual cell equalization judgment conditions are fully met does it start the supercapacitor branch DC port voltage detection process. The voltage acquisition point is selected between the DC output terminal of the supercapacitor branch and the smoothing reactor. This location can accurately reflect the actual output voltage of the supercapacitor branch. The configured high-precision voltage sensor must meet the requirement that the measurement range covers the rated voltage of the supercapacitor branch. U dc0 The accuracy is 0.8 to 1.2 times that of the standard, reaching ±0.1%FS, and it has a shielded structure to resist electromagnetic interference. The acquired raw analog signal first passes through a second-order RC low-pass filter circuit with a cutoff frequency of 1kHz to filter out ripple above 20kHz generated by the high-frequency operation of the switching devices and 50Hz power frequency interference from the power grid. Then it is input to a 16-bit successive approximation ADC module to complete analog-to-digital conversion at a sampling rate of 2MHz. The converted digital signal is checked by CRC-16, and the check range covers the frame header, voltage data, and frame tail to ensure that there are no data transmission errors. Then it is transmitted to the buffer unit of the MCCMU for storage at a frequency of once every 100μs, where the real-time DC port voltage is stored. U dc The equivalent overcapacitance branch port voltage in the corresponding disclosure document provides an accurate data source for subsequent deviation calculations.

[0081] Step 3.2: Compare the detected real-time DC port voltage with the preset target voltage value to calculate the real-time voltage deviation value, specifically including: the preset target voltage value. U dcref The rated port voltage of the overcapacitance branch is set strictly according to the formula. In the formula This is the switching state of the overcapacity half-bridge submodule. For the voltage of a single supercapacitive cluster, k The total number of overcapacitance half-bridge submodules is determined by considering the rated voltage of individual overcapacitance units, the number of overcapacitance clusters connected in series, and the voltage requirements of the grid for active power support of the SSC. It also supports the main controller PCP based on grid-side active power demand, according to the formula: (in the formula) for MMC angular frequency, The rated angular frequency, K 1 is the response coefficient. The online fine-tuning step size (for the rated voltage of the overcapacitance branch) is set to 0.1% of the rated voltage to avoid voltage fluctuations affecting system stability; the MCCMU extracts preset values ​​from the non-volatile memory. U dcref The real-time DC port voltage after collection and verification U dc and U dcref Perform difference calculation to obtain the real-time voltage deviation value. In the formula Δ U It intuitively reflects the degree of deviation between the current port voltage and the target value.

[0082] After the calculation is completed, for Δ U Perform amplitude limiting preprocessing, with the limiting range set to ±10%. U dc0 To prevent excessive switching of subsequent submodules due to extreme deviations; and to determine validity, if Δ U If the voltage deviation exceeds the limit and fails to recover for three consecutive 300μs acquisition cycles, immediately send a port voltage deviation abnormality fault signal to the PCP via the communication network, along with real-time data. U dc , U dcref And deviation values, to ensure that subsequent adjustments are based on valid data.

[0083] Step 3.3: Input the real-time voltage deviation value to the closed-loop controller. Specifically, the closed-loop controller uses a PI (proportional and integral) controller, hereinafter referred to as a PI controller, whose proportional coefficient... K p and integral coefficient K i The tuning strictly combines the dynamic characteristics of the overcapacity branch, the virtual inertia requirement, and the system stability requirements: K p Based on the capacitance value of the supercapacitive branch C sm The branch current response speed is set to ensure that the adjustment amount can be output quickly when voltage deviation occurs, avoiding response lag; K i The setting is based on the charge / discharge rate and static deviation requirements of the overcapacitance half-bridge submodule, used to compensate for steady-state voltage deviation, and K i The value is dynamically corrected according to the temperature change of the overcapacity branch. For every 10°C increase in temperature, K i Reduced by 5% to adapt to operation in a wide temperature range.

[0084] The obtained effective real-time voltage deviation value Δ U First, input the limiting module; the limiting range corresponds to the rated number of overcapacity half-bridge sub-modules.N sc0 ±20%, meaning the upper limit of the adjustment should not exceed 0.2%. N sc0 The lower limit is not lower than -0.2. N sc0 To avoid voltage oscillations caused by frequent switching of submodules, a first-order inertial filter with a time constant of 50μs is applied to remove high-frequency noise interference, resulting in a smoothed optimized deviation signal. This optimized deviation signal is then input to a PI controller, which operates according to the formula: Calculate the adjusted output value, where Δ U opt The optimized deviation signal, To optimize the integral term of the voltage deviation signal, i.e., for Δ U opt The cumulative calculation over time is used to eliminate static deviations in the system, such as drift of parameters of overcapacitor cells and steady-state voltage drop caused by circuit losses, to ensure that the port voltage remains stable at the target value in the long term. This is the switching adjustment value for the overcapacity half-bridge submodule; this adjustment output value will be related to the rated number of overcapacity half-bridge submodules in operation. N sc0 The superposition serves as the core basis for subsequent calculations of the target switching quantity, enabling precise mapping of voltage deviation, adjustment amount, and submodule switching. This aligns with the core logic of constant voltage control spontaneously adjusting the number of overcapacity clusters to maintain terminal voltage stability, while simultaneously ensuring that the SSC possesses virtual inertia response characteristics similar to a synchronous generator.

[0085] Step 3.4 involves processing the real-time voltage deviation value using a closed-loop regulator to calculate the target number of overcapacitance half-bridge submodules required to maintain DC port voltage stability. This includes:

[0086] In this embodiment of the invention, based on the premise of voltage balancing of individual supercapacitor branch units, a reliable data foundation is established by accurately detecting the real-time voltage of the DC port. The voltage deviation is quantified by comparing it with the target voltage value, and then the deviation is dynamically converted into the target number of supercapacitor half-bridge submodules by a closed-loop regulator. This not only responds quickly to voltage fluctuations and eliminates steady-state deviations through the proportional and integral characteristics of closed-loop control, ensuring that the DC port voltage is stable within the preset range, but also optimizes the number of submodules to be switched in real time according to the voltage deviation, avoiding switching losses and voltage oscillations caused by excessive switching. At the same time, it adapts to the dynamic operating conditions and active power demand of the power grid, significantly improving the voltage source characteristics and transient support capability of the static synchronous condenser (SSC). This provides a solid guarantee for the coordinated control of supercapacitor clusters and the stable operation of the entire power system, effectively extending the service life of the supercapacitor energy storage system and submodules, and taking into account control accuracy, operating efficiency and system reliability.

[0087] In a preferred embodiment of the present invention, step 3.4 above may include:

[0088] Step 3.41: Based on the real-time voltage deviation value, the proportional term output is obtained by calculating the proportional term through the proportional element of the closed-loop regulator. Specifically, the proportional element calculation is based on the optimized real-time voltage deviation signal Δ. U opt Using formula Perform the calculation, in the formula K p Δ is the proportional gain of the PI regulator. Its value is set according to the dynamic response characteristics of the overcapacitance branch, the charging and discharging rate of the overcapacitance half-bridge submodule, and the system phase margin requirements. It is recommended that the phase margin be ≥45° to ensure that the regulation amount can be output quickly when voltage deviation occurs; U opt The effective voltage deviation after limiting and first-order inertial filtering directly reflects the degree of deviation between the DC port voltage of the overcapacitive branch and the target value; Δ is confirmed before calculation. U opt Within the preset effective range, ±10% of the rated voltage, to avoid abnormal deviations causing excessive proportional term output, the calculation process is synchronized with the 100μs data acquisition cycle, resulting in the proportional term output. P This is the initial adjustment amount for the number of submodules to be switched on. Its physical meaning is to quickly suppress port voltage fluctuations by adjusting the force proportional to the deviation.

[0089] Step 3.42: Based on the real-time voltage deviation value, the integral term output is obtained by calculating through the integral element of the closed-loop regulator. Specifically, the integral element calculation uses a discretized integral formula: In the formula K i The integral coefficient is tuned according to the static deviation requirements of the overcapacity branch and the integral saturation suppression requirements; its value is related to... K p Matching, usually , This is the system's inertial time constant, used to accumulate and offset steady-state voltage deviations; For the first n Optimized voltage deviation for each acquisition cycle T s The data acquisition period is 100μs. k This is the current acquisition cycle number; an anti-saturation mechanism is introduced during integration calculation, and the integral term is output. I The amplitude is limited to ±0.1. N sc0 , N sc0 To determine the rated number of overcapacity half-bridge submodules to avoid long-term deviations leading to integral overflow, an integral separation strategy is adopted. The integral accumulation is paused at certain times, and only proportional control is retained to prevent overshoot from worsening. The final integral term output is obtained. I The compensation adjustment amount is used to eliminate steady-state deviation.

[0090] Step 3.43: Summing the proportional term output and the integral term output yields the total controlled output value of the closed-loop controller. This specifically includes: according to the formula... Output the proportional term P Output of integral term I Summation, in the formula N sc_adj This represents the total regulating output value of the PI controller, i.e., the total change in the number of overcapacitated half-bridge submodules switched; before summing, first adjust... P and I Perform unit consistency checks to ensure that both are based on the number of submodules, avoiding calculation errors; after summing, check... N sc_adj A second amplitude limiting process is applied, with a limitation range of ±20%. N sc0 To prevent excessive total regulation from causing frequent switching of submodules, leading to voltage oscillations or increased switching losses; if the total regulation output value exceeds the limit range, the number of times the limit is exceeded is recorded. When the limit is exceeded for three consecutive cycles, a regulation saturation warning is fed back to the main controller PCP to ensure that the total regulation output value meets both the voltage stability requirements and the system hardware operation constraints.

[0091] Step 3.44: Based on the total regulation output value of the closed-loop regulator, determine and output the integer target number of overcapacitance half-bridge submodules that need to be put into operation to maintain DC port voltage stability. Specifically, this includes: first, according to the formula... Calculate the target number of submodules, where The integer target number of overcapacity half-bridge submodules that need to be put into operation. The number of sub-modules to be deployed is the rated quantity. This is the total control output value. round (·) is a rounding function to ensure that the target quantity is an integer, which meets the actual switching requirements of the project; after rounding, the integer value is... Perform boundary checks to ensure it is within 0 to... N sc_max If the total number of overcapacity half-bridge submodules is less than 0, it will be forcibly set to 0; if it is greater than 0, it will be set to 0. N sc_max Then force set to N sc_maxTo avoid invalid switching commands, the system then combines the status monitoring data of the overcapacity submodules, prioritizing submodules with good voltage consistency and no fault records for inclusion in the switching list, while removing submodules with faults or abnormal voltage. Finally, it outputs a definite integer target number and a list of corresponding submodule IDs, providing precise commands for subsequent submodule switching control and ensuring that the DC port voltage remains stable within the preset range.

[0092] In this embodiment of the invention, the calculation process of the closed-loop regulation and the target number of submodules is broken down into stages. The proportional stage uses an adjustment amount adapted to the voltage deviation to achieve a rapid response to the voltage fluctuation of the DC port of the overcapacitance branch and timely suppress transient voltage deviation. The integral stage combines anti-saturation and integral separation strategies to effectively offset the steady-state voltage deviation, ensure the long-term stability accuracy of the port voltage, and avoid the risk of regulation overshoot caused by integral overflow. The summation and amplitude limiting of the proportional and integral terms balance the speed of regulation and the stability of system operation, avoiding the frequent switching losses of submodules caused by excessive regulation. Finally, through the design of rounding, boundary verification and priority switching of healthy submodules, the target number is made to meet the integer switching requirements of engineering practice and ensure the reliability of the operational submodules. This series of operations not only achieves precise and stable control of the DC port voltage of the overcapacitance branch, but also improves the operating efficiency and service life of the overcapacitance half-bridge submodules, laying a solid control foundation for the voltage source characteristics of the static synchronous condenser and the transient support capability of the power grid.

[0093] In a preferred embodiment of the present invention, step 4 above may include:

[0094] Step 4.1: Obtain the calculated integer target number of the supercapacitive half-bridge submodules, and simultaneously detect the real-time current direction of the supercapacitive branch. Specifically, this includes: extracting the output integer target number of the supercapacitive half-bridge submodules from the non-volatile memory unit of the supercapacitive cluster management unit terminal MCCMU. N sc_target The preliminary list of corresponding submodules to be switched is extracted, and frame header verification, data length verification, and CRC-16 dual verification are used during the extraction process to ensure that the target quantity is between 0 and the total number of submodules. N sc_max The effective range is determined, and a data retransmission mechanism is triggered if the verification fails; simultaneously, the real-time branch current is detected by a Hall closed-loop current sensor (such as CSNK591) connected in series with the overcapacitance branch. i brnThe sensor has a measurement range of ±1200A, a linear accuracy of 0.1%, and a response speed of less than 1μs, enabling it to accurately capture dynamic changes under high current conditions. The acquired analog current signal is first amplified by an instrumentation amplifier to the ADC's adaptation range, then passed through a 5th-order Butterworth low-pass filter circuit with a cutoff frequency of 1kHz to filter out electromagnetic interference generated by high-frequency switching devices. Subsequently, it is input to a 16-bit ADC module for analog-to-digital conversion at a 2MHz sampling rate. The converted digital signal is then verified and transmitted to the MCCMU. According to the formula... i brn A value less than 0 indicates an overcapacity branch discharge state, resulting in active power output to the grid. i brn A value greater than 0 indicates a charging state, where active power is absorbed from the grid. i brn When the current direction is 0, the current direction determination result of the previous cycle is maintained. This determination result will directly determine the sorting logic of subsequent sub-modules and provide a directional basis for cluster-level equalization.

[0095] Step 4.2: Determine the sorting rules based on the detected real-time current direction, and sort the capacitor voltage values ​​of all available overcapacitance half-bridge submodules in the overcapacitance branch according to the determined sorting rules to obtain an ordered submodule sequence. Specifically, this includes: firstly, filtering all available overcapacitance half-bridge submodules in the overcapacitance branch according to preset conditions. The usability criteria include: no overvoltage in the submodule. U smc ≤1.1 U smc_rated undervoltage U smc ≥0.8 U smc_rated There are alarm records for faults such as short circuits, and no drive faults are found in the half-bridge switches T1 and T2. U smc For the voltage of a single supercapacitive cluster, U smc_rated The rated voltage of the overcapacitive cluster is used; the real-time capacitor voltage of each available submodule is collected by the overcapacitive cluster management unit (CCMU) at a period of 100μs. The collected data is processed by second-order RC filtering to remove abnormal values ​​with voltage fluctuations exceeding ±2mV for two consecutive cycles, ensuring voltage sampling accuracy; the bubble sorting rule is determined according to the current direction in step 4.1: charging state i brn When >0, press U smc Arrange in ascending order from smallest to largest, prioritizing the activation of sub-modules with lower voltage; discharge state. i brn When <0, press U smcThe submodules are sorted in descending order of voltage, with priority given to those with higher voltage to suppress the increase in voltage difference during discharge. The sorting process is executed by comparing adjacent submodules pairwise and swapping their positions if the voltage does not meet the sorting rules. The sorting results are updated synchronously with the data acquisition cycle, ultimately forming an ordered sequence of submodules containing submodule ID, real-time capacitor voltage value, and health status score, ensuring the real-time performance and reliability of the sorting results.

[0096] Step 4.3: Based on the obtained integer target quantity, select a corresponding number of preceding submodules from the obtained ordered submodule sequence. Specifically, this includes: selecting the obtained integer target quantity... N sc_target The total number of available submodules in the ordered submodule sequence N avail Conduct precise comparisons to clarify the actual selection strategy: If N sc_target ≥ N avail If the target number exceeds the available range, then all available submodules are selected, and a secondary alarm message indicating that the target number exceeds the available range is fed back to the main controller PCP via the industrial Ethernet. Simultaneously, the current number of available submodules and the ID of the faulty submodule are recorded. If 0 < N sc_target < N avail Then select the first from the ordered submodule sequence. N sc_target Each submodule serves as a preceding submodule. During the selection process, a submodule health status weighting coefficient is introduced, with the weight calculated as: weight = (1 - standard deviation of voltage fluctuation over the last 100 cycles / rated voltage) × (1 - number of fault records / total operating cycles). Submodules with higher weighting values ​​are selected first to ensure the stability of the commissioned submodules. N sc_target If the value is ≤0, the number of selected modules is 0, and all submodules remain in the initial bypass state. After selection, a detailed submodule switching list is generated. The list clearly indicates the ID of the preceding submodule, the switching instruction type (on or off), the expected switching time, and the corresponding capacitor voltage value. It is synchronously stored in the switching control unit of the MCCMU and sent to the corresponding CCMU for pre-preparation.

[0097] Step 4.4: Control the selected preceding submodule to enter the working state, and control the remaining submodules in the ordered submodule sequence to be in the bypass state. This achieves voltage balancing among the supercapacitor clusters within the supercapacitor branch, completing cluster-level balancing control. Specifically, the MCCMU sends a high-level input signal to the CCMU corresponding to the selected preceding submodule according to the switching list. The signal uses differential transmission to resist electromagnetic interference, with a transmission rate of 1Mbps. After receiving the signal, the CCMU drives the half-bridge switches T1 and T2 to conduct within 3μs, enabling the submodule to connect to the supercapacitor branch main circuit and enter the working state. After input, the capacitance of the submodule is monitored in real time. Voltage change rate is controlled within ≤5V / ms and branch current fluctuation to avoid current surges damaging switching devices. For the remaining submodules in the ordered submodule sequence, a low-level bypass signal is sent, employing a thyristor fast bypass + mechanical switch locking collaborative mechanism: first, the thyristor is triggered to conduct rapidly within 10μs, short-circuiting the submodule to achieve instantaneous bypass; after 50μs, the mechanical switch is controlled to close, taking over the bypass function to reduce long-term bypass losses. During the bypass process, the submodule status is continuously monitored; if a thyristor conduction fault occurs, a lockout command is immediately triggered and fault information is fed back. After switching is completed, the standard deviation of the capacitor voltage of each overcapacitor cluster is calculated in real time, combined with the formula: (in the formula) m sw This indicates the submodule switching status. k To verify the stability of branch port voltage (total number of submodules), when the standard deviation of the capacitor voltage of all overcapacitance clusters is less than 3mV, the voltage difference between the maximum and minimum overcapacitance clusters in the branch is less than 15V, and the voltage remains stable for three consecutive data acquisition cycles of 300μs, it is determined that the cluster-level voltage equalization within the overcapacitance branch is completed. The MCCMU sends a cluster-level equalization end signal to the PCP. The signal contains the equalized branch port voltage, the number of submodules put into operation, the voltage value of each overcapacitance cluster, and the circulating current monitoring data, providing an accurate status reference for subsequent synchronous and coordinated equalization control between overcapacitance branches.

[0098] In this embodiment of the invention, by accurately obtaining the integer target number of the overcapacitive half-bridge submodules after closed-loop regulation, and combining the real-time detection of the overcapacitive branch current direction with dynamic adaptation sorting logic, a bubble sorting strategy of ascending and descending capacitor voltage is adopted in the charging and discharging states, respectively. This ensures both the accurate matching of submodule switching and energy flow direction and the targeted suppression of cluster-level voltage difference expansion during charging and discharging. By screening fault-free and voltage-compliant usable submodules, and combining the NLM modulation algorithm to select the corresponding number of preceding submodules for operation, while isolating the remaining submodules through an electronic bypass mechanism, the reliability of the operated submodules is ensured. It reduced ineffective energy consumption; and finally, through precise switching control of submodules, it achieved voltage balancing among the supercapacitor clusters within the supercapacitor branch, completing cluster-level adaptive balancing control. This not only meets the self-synchronization characteristics and inertia response requirements of the static synchronous condenser SSC simulating a synchronous generator, but also lays a stable foundation for subsequent synchronous and coordinated balancing among multiple supercapacitor branches. It effectively improved the voltage consistency and operational stability of the supercapacitor energy storage system, strengthened the active power support capability and grid transient response performance of the SSC, and avoided the risks of faulty submodule commissioning and switching losses caused by excessive switching, thus balancing control accuracy, reliability, and operational efficiency.

[0099] In a preferred embodiment of the present invention, step 5 above may include:

[0100] Step 5.1: After completing the cluster-level equalization control of each overcapacity branch, the main controller generates a unified modulation wave command based on the active and reactive power support requirements of the power grid. Specifically, the main controller is a static synchronous condenser (SSC) polar control protection system (PCP) with a primary / backup redundant hot backup configuration. The primary and backup units achieve millisecond-level real-time data synchronization via gigabit fiber optic cable to ensure uninterrupted command generation under extreme conditions. The PCP collects the three-phase voltage at the grid connection point in real time through voltage transformers and current transformers. U ga , U gb , U gc ), three-phase current ( I ga , I gb , I gc After being converted to dq-axis components via Clark and Park transforms, the real-time frequency of the power grid is calculated. oh g Line voltage RMS value U g Total active power P g and total reactive power Q gThe data update cycle is 100μs; simultaneously, the PCP receives branch status data uploaded by each overcapacity branch management unit (MCCMU), including branch port voltage. U dc Number of sub-modules to be invested N sc_run Average voltage of supercapacitive clusters The system uses a list of submodule health status codes and fault IDs to comprehensively assess the available capacity and dynamic response capability of the supercapacity energy storage system.

[0101] Based on preset active and reactive power support curves of the power grid, such as an active power support coefficient of 0.8 when the frequency deviation is ±0.2Hz and a reactive power support coefficient of 0.9 when the voltage deviation is ±5%, it is determined whether there is a frequency drop, voltage sag, or active power deficit in the power grid; based on constant voltage control logic and formulas: In the formula oh MMC For the pre-stage MMC angular frequency, oh 0 represents the rated angular frequency of the power grid, 50Hz. K 1 represents the voltage-frequency response coefficient, ranging from 0.1 to 0.3, and is adjusted according to the grid inertia requirements. U dc0 A uniform modulation waveform command is generated for the rated voltage of the overcapacitive branch; this command includes the target value of the overcapacitive branch port voltage. U dcref The submodule switching adjustment step size is ≤5 units / cycle, and the response speed level includes fast, medium and slow, corresponding to different grid disturbance intensities and fault blocking thresholds. Furthermore, the modulation wave instructions corresponding to all overcapacity branches are generated within the same 100μs task cycle and share the same memory address segment, ensuring that the instruction parameters are completely consistent, thus laying the foundation for subsequent branch synchronization.

[0102] Step 5.2: Through the synchronous communication link between the main controller and each branch management unit, the unified modulation wave command is synchronously sent to the branch management units corresponding to all overcapacity branches. Specifically, this includes: a synchronous communication link is established between the main controller PCP and each overcapacity branch management unit MCCMU via dual-redundant gigabit optical fiber, with a communication rate of 1Gbps and a transmission delay strictly controlled within 10μs. Differential signal transmission is used to resist electromagnetic interference in the industrial environment. The PCP acts as the communication host, with a 100μs hard interrupt cycle internally, used for centralized processing of control logic operations and command issuance tasks. At the same time, a pulse synchronization signal forces the interrupt task functions of all MCCMUs to maintain timing alignment with the PCP, ensuring that the time base for command interaction between the two parties is consistent. After the unified modulation wave command is generated, the PCP encapsulates the command according to a preset frame structure. The frame structure consists of an 8-byte frame header (identifying the command type). The command consists of 32 bytes of instruction data (including core parameters such as Udcref and adjustment step size), 4 bytes of CRC-32 checksum (covering the frame header and instruction data, used to verify integrity), and 2 bytes of frame trailer (marking the end of the instruction). After encapsulation, the PCP broadcasts the instruction to all MCCMUs simultaneously via the synchronous communication link. During the broadcasting process, a broadcast + one-to-one response mechanism is enabled: after receiving the instruction, each MCCMU first verifies the format of the frame header and frame trailer, and then verifies the data integrity through the CRC-32 checksum. After the verification is successful, it immediately sends a reception confirmation signal containing its own address code back to the PCP. If the PCP does not receive a confirmation signal from a certain MCCMU within 50μs, it determines that the instruction transmission has failed and immediately starts the retransmission process. The number of retransmissions shall not exceed 3. If the retransmission fails 3 times, the communication failure of that branch is marked and reported to the operation and maintenance platform to ensure that all branches can obtain complete and consistent modulated wave instructions.

[0103] Step 5.3: Based on the received unified modulation wave command and the electrical state of the overcapacity branch corresponding to each branch management unit, each branch management unit generates an initial drive command for the overcapacity branch. Specifically, after receiving the unified modulation wave command, each overcapacity branch management unit (MCCMU) first parses the frame structure... U dcref Core parameters such as switching adjustment step size and response speed level are analyzed. If the parameters are found to be outside the preset valid range during the analysis process, such as... U dcref Exceeding 0.8 U dc0 Up to 1.2 U dc0 If the previous cycle's valid parameters are used temporarily, an alarm for parameter anomalies will be issued. Subsequently, the MCCMU will call its own real-time collected branch electrical status data, including real-time branch current. i brnReal-time voltage of each supercapacitor cluster, acquired by Hall effect sensor and processed by 5th-order Butterworth low-pass filter. U smc1 to U smck Uploaded by CCMU via a daisy-chain loop; total number of available overcapacity half-bridge submodules. N avail Remove submodules with overvoltage, undervoltage, or switch malfunctions; list the IDs of faulty submodules and the current status of operational submodules. m sw 1 indicates input, 0 indicates bypass; these data are updated and cached at 100μs intervals; based on the parsed modulation wave command, combined with the bubble sorting rule and NLM modulation algorithm used in cluster-level equalization control, the MCCMU first sorts the capacitor voltages of all available submodules, and then calculates the number of submodules to be added or removed and their specific IDs according to the switching adjustment step size and the current number of modules in operation in the command.

[0104] Subsequently, initial drive instructions are generated for the overcapacitance half-bridge submodules of this branch. These instructions include the submodule ID, switching status, switching transistor timing (3μs turn-on delay, 2μs turn-off delay), and fault lockout conditions, such as immediate lockout if the current surge exceeds 5A / μs. After generation, the initial drive instructions must be verified to ensure they comply with the branch's current electrical constraints: current surge not exceeding 5A / μs, overcapacitance cluster voltage change rate not exceeding 5V / ms, and the total number of engaged submodules not exceeding [a certain threshold]. N sc_max If the verification passes, the system enters the instruction ready state; otherwise, the number of switches is adjusted and the system is regenerated to ensure the feasibility and security of the instruction.

[0105] Step 5.4 involves coordinating through high-frequency synchronization signals between branch management units to ensure that all branch management units perform latching operations on their generated initial drive commands at the same time, thereby obtaining and maintaining synchronized final drive commands. Specifically, this includes: pre-setting the MCCMU of branch 1 as the master MCCMU and the MCCMUs of the other branches as slave MCCMUs, with the master and slave MCCMUs connected via high-frequency modulation signal lines, and the synchronization signal frequency set to 1MHz to ensure microsecond-level synchronization accuracy between branches; after each MCCMU generates the initial drive command and completes electrical constraint verification, it sends a command ready signal to the master MCCMU, which includes its own branch ID and command generation timestamp; the master MCCMU receives the ready signals from all slave MCCMUs in real time, and after confirming that all branches are in a ready state, it sends a high-frequency synchronization trigger signal (rising edge valid) after a 10μs delay to avoid synchronization deviation due to signal transmission delay.

[0106] Upon detecting the rising edge of the synchronization signal via a hardware interrupt, each MCCMU immediately initiates a latching mechanism to latch the initial drive command within 1μs. The latched command is no longer affected by subsequent modulation wave changes or signal interference, ensuring consistent drive command states across all branches. The latched final drive command remains until the next cycle's synchronization signal arrives. If a master / slave switch occurs during this period, the new modulation wave command must wait for the next synchronization signal to take effect before triggering the generation of a new drive command, preventing circulating current caused by differences in the number of switching operations between branches due to sudden modulation wave changes. Simultaneously, each MCCMU monitors the integrity of the synchronization signal in real time. If no synchronization signal is received from the master MCCMU for 3 consecutive synchronization cycles (3ms), an inter-branch synchronization fault alarm is immediately reported to the PCP, and the current drive command state is maintained until the synchronization signal is restored. Finally, all MCCMUs simultaneously send the latched final drive command to the corresponding CCMU, achieving strict synchronization of drive commands across all overcapacity branches and effectively suppressing circulating current caused by timing differences between branches.

[0107] In this embodiment of the invention, a unified modulation wave command is generated by the main controller in conjunction with the active and reactive power support requirements of the power grid, ensuring the consistency of the control benchmark for multiple overcapacity branches and avoiding inter-branch coordination disorder caused by command differences. Synchronous command issuance is achieved through a highly reliable synchronous communication link, coupled with a primary / backup redundancy design and a strict verification and retransmission mechanism, ensuring the integrity and timeliness of command transmission. Each branch management unit generates initial drive commands based on the unified command and its own branch electrical status (such as current, voltage, and submodule health status), taking into account both the adaptability to individual branch operating differences and the overall control objective. Furthermore, a master-slave high-frequency synchronization... The signal coordination and latching mechanism enables all branch drive commands to take effect and remain stable at the same time, effectively solving the problem of inter-branch circulating current caused by asynchronous modulation commands and disordered drive timing in existing technologies. This series of operations constructs a synchronous and coordinated equalization control system among multiple supercapacitor branches, which not only enhances the grid-type voltage source characteristics and virtual inertia response capability of the static synchronous condenser (SSC), but also ensures the consistency and stability of multi-branch operation, effectively suppresses branch circulating current, avoids command errors during redundant switching, provides accurate and reliable active and reactive power support for the power grid, and improves the overall operating efficiency and service life of the supercapacitor energy storage system.

[0108] In a preferred embodiment of the present invention, step 6 above may include:

[0109] Step 6.1: Each branch management unit (MCCMU) acquires the final drive instruction for synchronization. Specifically, after completing the initial drive instruction latch, each branch management unit (MCCMU) reads the final drive instruction for synchronization from its own latch register. This instruction has been ensured by the high-frequency synchronization signal (1MHz) between the master and slave MCCMUs to ensure that the timing of all branches is consistent. The final drive instruction includes the ID of each overcapacity half-bridge submodule, the target status (engaged, bypassed, or blocked), the action timing parameters (3μs turn-on delay, 2μs turn-off delay), and the fault blocking threshold. The instruction format is consistent with the previous initial drive instruction to ensure compatibility. During the reading process, the MCCMU performs double verification on the instruction: first, it verifies the CRC-16 checksum of the instruction to ensure that there are no data transmission errors; second, it verifies the matching of the submodule ID in the instruction with the list of submodules under the jurisdiction of this branch, and removes invalid ID instructions. If the verification fails, the MCCMU maintains the final drive instruction of the previous cycle and feeds back an instruction reading anomaly alarm to the master controller (PCP) to ensure that the acquired instructions are accurate, effective, and synchronized.

[0110] Step 6.2: Each branch management unit (MCCMU) transmits the acquired final synchronized drive instructions to its respective cluster management units (CCMUs) via the communication link between the branch management unit and the cluster management unit. Specifically, the MCCMU establishes a communication link with each of its subordinate CCMUs through a ring topology daisy chain at a communication rate of 1 Mbps. Differential signal transmission is used to resist electromagnetic interference in the industrial environment, and the transmission delay is controlled within 5 μs. The MCCMU encapsulates the synchronized final drive instructions into cluster groups. Each data packet contains the drive instructions of the corresponding CCMU's submodule. The frame structure consists of a 4-byte header (identifying the CCMU address) and 32 bytes of instruction data. (Including submodule ID, target status, etc.), 2-byte CRC-16 checksum, 2-byte frame tail (marking the end of the instruction); After encapsulation, the MCCMU sends the instructions sequentially according to the CCMU address order. During the sending process, a point-to-point confirmation mechanism is enabled: After each CCMU receives the instruction, it first verifies the frame header address matching, and then verifies the data integrity through the checksum. After the verification is successful, it immediately sends an confirmation signal containing its own address back to the MCCMU. If the MCCMU does not receive a confirmation signal from a CCMU within 30μs, it immediately starts the retransmission process. The number of retransmissions shall not exceed 2. If the retransmission fails twice, the CCMU is marked as having a communication failure and reported, ensuring that all CCMUs can accurately receive the driver instructions.

[0111] Step 6.3: Each cluster management unit (CCMU) parses and generates a corresponding power semiconductor switch control signal based on the received drive command. This signal controls one or more supercapacitive half-bridge submodules under each CCMU to perform a unified switching operation for the enabled, bypassed, or locked states. Specifically, after receiving the drive command from the branch management unit (MCCMU), each CCMU first verifies the integrity of the command using a CRC-16 checksum, then parses the supercapacitive half-bridge submodule ID, the target state (enabled, bypassed, or locked), and the timing parameters in the command. After parsing, it performs a secondary judgment based on the real-time status of its submodules, including voltage, temperature, and fault records. If a submodule has an overvoltage, undervoltage, or short-circuit fault, it is automatically corrected to a locked state regardless of the target state, and a correction log is recorded. If the submodule is in a normal state, a corresponding power semiconductor switch control signal is generated according to the target state. For the enabled state, high-level conduction control signals for transistors T1 and T2 are generated. The signal duration matches the submodule's action requirements, and the conduction delay is strictly controlled within 3μs to ensure that the supercapacitive cluster is smoothly connected to the main circuit and meets the formula. m sw =1 ( m sw The definition of the submodule switching status is as follows: For the bypass state, a 10μs wide pulse thyristor turn-on control signal is first generated to achieve rapid short-circuiting of the submodule; after 50μs, a mechanical switch closing control signal is generated to take over the bypass function to reduce long-term losses, which is in line with... m sw =0 bypass definition; for the locked state, generate low-level turn-off control signals for T1, T2 transistors and thyristors to ensure that the submodule is completely disconnected from the main circuit; all control signals are optically isolated, and the rise and fall times are controlled within 1μs to resist electromagnetic interference and ensure the precise operation of the switching devices.

[0112] Step 6.4: All overcapacitance half-bridge submodules in all overcapacitance branches, based on the final synchronous drive command, perform a unified switching operation for activation, bypass, or blocking within the same control cycle. This suppresses inter-branch circulating currents caused by timing differences, achieving coordinated and stable operation of the multiple overcapacitance branches. Specifically, after receiving the synchronous drive command from the MCCMU, the CCMUs of all overcapacitance branches use the rising edge of the 1MHz high-frequency synchronization signal from the main MCCMU as a unified trigger reference, ensuring that all submodules initiate state switching operations within the same 100μs control cycle, with a timing error ≤1μs. During the process, the voltage change rate of the submodules is monitored in real time and controlled to ≤5V / ms, and the branch current surge is limited to ≤5A / μs to avoid device damage. Simultaneously, each MCCMU collects inter-branch circulating current data through Hall current sensors, and performs real-time verification in conjunction with the circulating current suppression target (reducing from 80A to within 10A) in the handover document. After switching, the status of all overcapacitance half-bridge submodules strictly follows the final synchronous drive command. The engaged submodules are stably connected to the main circuit, the bypassed submodules are isolated through thyristors and mechanical switches, and the locked submodules are completely disconnected from the main circuit. At this point, the port voltage of each overcapacitance branch satisfies the formula: , U dc For branch port voltage, U smc For the voltage of a single supercapacitive cluster, k The total number of submodules is controlled within 15V for the maximum and minimum voltage difference between branches, effectively suppressing circulating current caused by differences in action timing. Finally, each MCCMU feeds back the submodule state switching results to the main controller PCP. After the PCP confirms that the state of all branches is synchronized, it determines that the multiple overcapacity branches have achieved coordinated and stable operation, providing reliable active and reactive power support for the power grid.

[0113] In this embodiment of the invention, the final drive command for synchronization is accurately obtained by each branch management unit. Relying on a reliable communication link and a strict verification mechanism, the integrity and accuracy of the command transmission to the cluster management unit are ensured. The cluster management unit then analyzes the command in a targeted manner and generates control signals adapted to the power semiconductor switches. It can also automatically correct the status commands of faulty submodules and avoid invalid operations. Finally, all overcapacity half-bridge submodules of all overcapacity branches are synchronously executed in the same control cycle to switch between the engaged, bypassed, or blocked states. This ensures a high degree of consistency in the timing of actions throughout the entire process from command transmission and parsing to execution, effectively suppressing the circulating current between branches from 80A to less than 10A. This solves the problem of circulating current caused by timing differences in the prior art. Furthermore, precise status control avoids the risk of faulty submodule commissioning and damage to switching devices, enhances the full-level balancing effect of overcapacity units, clusters, and branches, and ensures the coordinated and stable operation of multiple overcapacity branches. This further improves the grid-type voltage source characteristics, virtual inertia response capability, and active power support reliability of the static synchronous condenser (SSC), providing a solid guarantee for the safe and stable operation of the power grid.

[0114] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A multi-super-capacitor branch layered decoupling equalization control method of a static synchronous compensator, characterized in that, The method comprises: Collecting voltage information of each super capacitor unit in the super capacitor branch, and determining a voltage reference value for equalization control; Based on the determined voltage reference value, discharging equalization control is performed on each super capacitor unit to achieve voltage equalization of all super capacitor units in the super capacitor branch; On the basis of completing voltage equalization of all super capacitor units, the DC port voltage of the super capacitor branch is detected, and the deviation of the DC port voltage from the preset target voltage is calculated; according to the calculated deviation, the number of super capacitor half-bridge submodules required to be put into operation to maintain the stability of the port voltage is calculated through closed-loop adjustment; According to the calculated number of super capacitor half-bridge submodules, and in combination with the detected real-time current direction of the super capacitor branch, all available super capacitor half-bridge submodules are sorted and selectively switched on to achieve voltage equalization between each super capacitor cluster in the super capacitor branch and complete cluster-level equalization control; On the basis of completing cluster-level equalization control, a unified modulation wave instruction is generated by the main controller and synchronously issued to the branch management units corresponding to each super capacitor branch; each branch management unit generates and latches a synchronous driving instruction based on the unified modulation wave instruction at the same time; Each branch management unit issues and executes the synchronous driving instruction to control all super capacitor half-bridge submodules in the super capacitor branch to perform unified operation to suppress inter-branch circulating current and achieve cooperative stable operation of the multiple super capacitor branches.

2. The hierarchical decoupling and equalization control method of a multi-superconductance branch of a static synchronous compensator according to claim 1, characterized in that, Collecting voltage information of each super capacitor unit in the super capacitor branch, and determining a voltage reference value for equalization control, comprises: Collecting real-time voltage of the super capacitor unit to which the management unit belongs through the management unit corresponding to each super capacitor module; Collecting real-time voltage of all super capacitor units in the super capacitor branch, and calculating average voltage value and minimum voltage value of the super capacitor branch; Detecting the real-time current size of the super capacitor branch, and comparing the real-time current size with the preset current threshold to obtain a comparison result; According to the comparison result of the real-time current size and the preset current threshold, one of the calculated average voltage value and minimum voltage value is dynamically selected as the voltage reference value for discharging equalization control.

3. The hierarchical decoupling and equalization control method of a multi-superconductance branch of a static synchronous compensator according to claim 2, characterized in that, Based on the determined voltage reference value, discharging equalization control is performed on each super capacitor unit to achieve voltage equalization of all super capacitor units in the super capacitor branch, comprising: Obtaining the determined voltage reference value, and comparing the real-time voltage of each super capacitor unit with the voltage reference value to obtain the real-time voltage difference corresponding to each super capacitor unit; Comparing the real-time voltage difference corresponding to each super capacitor unit with a first set threshold, wherein the first set threshold is dynamically determined according to the real-time current size; When the real-time voltage difference corresponding to a certain super capacitor unit is greater than the first set threshold, the discharging circuit parallel to the super capacitor unit is turned on to discharge the super capacitor unit through the equalization resistor; During the discharging process, the real-time voltage difference of the super capacitor unit is continuously monitored, and when the real-time voltage difference drops below a second set threshold, the discharging circuit is turned off to complete the discharging equalization control of the super capacitor unit; The operations of obtaining the corresponding real-time voltage difference, performing threshold comparison, and controlling the on and off of the discharge circuit are repeatedly performed for each super capacitor unit in the super capacitor branch until the real-time voltage differences of all super capacitor units are maintained within the second set threshold, thereby realizing voltage balancing of all super capacitor units in the super capacitor branch.

4. The hierarchical decoupling and equalization control method of a multi-superconductance branch of a static synchronous compensator according to claim 3, characterized in that, On the basis of completing voltage balancing of all super capacitor units, the DC port voltage of the super capacitor branch is detected, and the deviation of the DC port voltage from the preset target voltage is calculated. According to the calculated deviation, the number of super capacitor half-bridge submodules required to be put into operation to maintain the stability of the port voltage is calculated through closed-loop regulation, including: After the super capacitor branch completes voltage balancing of all super capacitor units, the real-time DC port voltage of the super capacitor branch is detected; The detected real-time DC port voltage is compared with the preset target voltage value to calculate the real-time voltage deviation value; The real-time voltage deviation value is input to the closed-loop regulator; The real-time voltage deviation value is processed by the closed-loop regulator to calculate the target number of super capacitor half-bridge submodules required to be put into operation to maintain the stability of the DC port voltage.

5. The hierarchical decoupling and equalization control method of a multi-superconductance branch of a static synchronous compensator according to claim 4, characterized in that, The real-time voltage deviation value is processed by the closed-loop regulator to calculate the target number of super capacitor half-bridge submodules required to be put into operation to maintain the stability of the DC port voltage, including: According to the real-time voltage deviation value, the proportional term output is calculated through the proportional link of the closed-loop regulator; According to the real-time voltage deviation value, the integral term output is calculated through the integral link of the closed-loop regulator; The proportional term output and the integral term output are summed to obtain the total adjustment output value of the closed-loop regulator; Based on the total adjustment output value of the closed-loop regulator, the integer target number of super capacitor half-bridge submodules required to be put into operation to maintain the stability of the DC port voltage is determined and output.

6. The hierarchical decoupling and equalization control method of a multi-superconductance branch of a static synchronous compensator according to claim 5, characterized in that, According to the calculated number of super capacitor half-bridge submodules and in combination with the detected real-time current direction of the super capacitor branch, all available super capacitor half-bridge submodules are sorted and selectively switched on to realize voltage balancing between each super capacitor cluster in the super capacitor branch, complete cluster-level balancing control, including: The calculated integer target number of super capacitor half-bridge submodules is obtained, and the real-time current direction of the super capacitor branch is detected; According to the detected real-time current direction, the sorting rule is determined, and the capacitance voltage values of all available super capacitor half-bridge submodules in the super capacitor branch are sorted according to the determined sorting rule to obtain an ordered submodule sequence; Based on the obtained integer target number, a corresponding number of front submodules are selected from the obtained ordered submodule sequence; The selected front submodules are controlled to be put into the working state, and the remaining submodules in the ordered submodule sequence are controlled to be in the bypass state, thereby realizing voltage balancing between each super capacitor cluster in the super capacitor branch and completing cluster-level balancing control.

7. The hierarchical decoupling and equalization control method of a multi-superconductance branch of a static synchronous compensator according to claim 6, characterized in that, On the basis of completing cluster-level balancing control, a unified modulation wave instruction is generated by the main controller and synchronously issued to the branch management units corresponding to each super capacitor branch; The branch management units coordinate to generate and latch synchronous driving instructions at the same time based on the unified modulation wave instruction, including: After the cluster-level equalization control of each super-capacity branch is completed, the main controller generates a unified modulation wave instruction according to the active and reactive power support demand of the power grid; Through the synchronous communication link between the main controller and each branch management unit, the unified modulation wave instruction is synchronously issued to the branch management units corresponding to all super-capacity branches; Each branch management unit generates an initial drive instruction for the super-capacity branch based on the received unified modulation wave instruction and the electrical state of the super-capacity branch corresponding to the branch management unit itself; Through high-frequency synchronization signals between branch management units, all branch management units perform a latch operation on the initial drive instructions generated by them at the same time to obtain and maintain synchronized final drive instructions.

8. The hierarchical decoupling and equalization control method of a multi-superconductance branch of a static synchronous compensator according to claim 7, characterized in that, Each branch management unit issues and executes the synchronized drive instructions to control all super-capacity half-bridge sub-modules in the super-capacity branches to perform unified operations to suppress inter-branch circulating current and achieve coordinated stable operation of the multiple super-capacity branches, including: Each branch management unit obtains synchronized final drive instructions; Each branch management unit issues the obtained synchronized final drive instructions to the cluster management units under the jurisdiction of the branch management unit through the communication link between the branch management unit and the cluster management unit; Each cluster management unit analyzes and generates corresponding power semiconductor switch control signals according to the received drive instructions to control one or more super-capacity half-bridge sub-modules under the cluster management unit to perform unified input, bypass or lockout state switching operations; All super-capacity half-bridge sub-modules in the super-capacity branches perform unified input, bypass or lockout state switching operations in the same control period based on synchronized final drive instructions, thereby suppressing inter-branch circulating current caused by action timing differences and achieving coordinated stable operation of the multiple super-capacity branches.

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