Switching control, system and method during conversion of multi-level power converter

Abstract

The present disclosure discloses switching control, systems, and methods during conversion of a multi-level power converter. Circuits and methods are provided for a multilevel converter circuit having switches arranged in pairs. The first pair of switches includes two innermost switches, the second pair of switches includes two switches located on either side of the two innermost switches, and the like, until two outermost switches are reached. During transition of the multilevel converter circuit from a first state to a second state, the pairs of switches are sequentially opened or closed to charge or discharge a node in the multilevel converter coupled to the inductor or a node between the pairs to minimize power loss. The pair of switches opens or closes starting from the first pair, followed by the second pair, and so on, until the outermost switch is reached. The circuits and methods also relate to a controller that changes state of the multilevel converter circuit.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to U.S. Provisional Patent Application No. 63 / 682,300, filed August 12, 2024, entitled “SWITCH CONTROL DURING MULTILEVEL POWER CONVERTER TRANSITION SYSTEMS AND METHODS”, the entire contents of which are incorporated herein by reference. Background Technology

[0003] This disclosure relates to electronic circuits, and more particularly to, for example, multilevel power converters.

[0004] Many electronic products, including mobile computing and / or communication products and components (e.g., notebook computers, ultrabooks, tablet devices, LCDs, LED displays, etc.), operate using multiple voltage levels. For example, radio frequency (RF) transmitter power amplifiers may operate at relatively high voltages (e.g., 12V or higher), while logic circuit systems may operate at relatively low voltage levels (e.g., 1V to 3V) and other circuit systems may operate at intermediate voltage levels (e.g., 5V to 10V).

[0005] DC power converters are typically used to generate lower or higher voltages from common power sources such as batteries, solar cells, and rectified AC sources. Power converters that generate a lower output voltage level from a higher input voltage source are often called buck converters, named so because the output voltage V... OUT Less than the input voltage V IN Therefore, the converter "steps down" the input voltage. A power converter that generates a higher output voltage level from a lower input voltage source is often called a boost converter because V... OUT Greater than V IN Some power converters can be either buck converters or boost converters, depending on which terminals are used for input and output. Some power converters can provide inverting outputs.

[0006] One type of DC power converter, known as a multilevel power converter, includes a charge transfer capacitor as an energy storage element, which is coupled via a controlled switch to transfer charge from V... IN Transfer to V OUT Such charge-transfer capacitors are commonly referred to as "fly capacitors" or "pump capacitors." When a fly capacitor is used (i.e., without bypassing), the electrical energy flowing through it typically charges or discharges the capacitor.

[0007] There is a ongoing need for improved circuits and methods for operating and implementing various types of electronic circuits and devices, including, for example, multilevel converter circuits, more effectively and efficiently. Summary of the Invention

[0008] Embodiments of this disclosure include systems, circuits, and methods for operating and implementing various electronic circuits, including multilevel converter circuits.

[0009] The embodiment relates to a system comprising: a controller configured to transition a multilevel converter circuit from a first state corresponding to a first voltage level to a second state corresponding to a second voltage level, wherein the controller for the transition is configured to: control a switch of the multilevel converter circuit to open to discharge parasitic capacitance at a node through an inductor, or control a switch of the multilevel converter circuit to close to charge a node through an inductor, wherein the switches are arranged in pairs and include a first pair and a second pair, wherein the first pair includes an innermost switch and the second pair includes a switch on each side of the innermost switch, and wherein the node is located between the innermost switches of the first pair or between the switch pairs; and control the switch pairs to sequentially close to discharge the node through an inductor, or control the switch pairs to sequentially open to charge the node through an inductor, wherein the closing or opening of the switches begins with the first pair, followed by the second pair.

[0010] The embodiments also relate to a multilevel converter circuit, the multilevel converter circuit comprising: a plurality of switches arranged in pairs, wherein a first pair comprises two innermost switches, and a second pair comprises two switches on either side of the two innermost switches, wherein a first switch in the second pair is connected in series to one of the innermost switches in the first pair, and a second switch in the second pair is connected in series to the other switch in the innermost switch, and wherein, during a transition of the multilevel converter circuit from a first state to a second state, one or more switches in the switch pairs are sequentially opened or closed, starting with the first pair and then the second pair; and an inductor arranged between the first switch pairs, wherein the opening or closing of one or more switches in the switch pairs charges or discharges parasitic capacitance at nodes between or between the first switch pairs via the inductor.

[0011] The implementation also relates to a method comprising: generating a signal for switching a multilevel converter circuit from a first state associated with a first voltage to a second state associated with a second voltage, wherein the multilevel converter circuit includes a plurality of switches arranged in non-overlapping pairs; and, in response to the signal, switching the multilevel converter circuit from the first state to the second state, wherein the switching further comprises: closing or opening all switches in the multilevel converter circuit; and sequentially opening closed switches in the pairs or sequentially closing open switches in the pairs, starting from the innermost pair and ending with the outermost pair, to charge or discharge parasitic capacitance at nodes via inductors, wherein the nodes are located between the innermost pairs or between the non-overlapping pairs.

[0012] The scope of this disclosure is defined by the claims, which are incorporated herein by reference. A more comprehensive understanding of embodiments of this disclosure and the realization of its additional advantages will be provided to those skilled in the art by considering the following detailed description of one or more embodiments. A brief description of the accompanying drawings will be given first with reference to the drawings. Attached Figure Description

[0013] Figure 1A This is an example power converter circuit with internal input current sensing according to one or more embodiments of the present disclosure.

[0014] Figure 1B This is an example power converter circuit with external input current sensing according to one or more embodiments of the present disclosure.

[0015] Figure 2A This is an example dual integrated circuit (IC) power converter circuit with internal input current sensing, according to one or more embodiments of this disclosure.

[0016] Figure 2B This is an example dual-IC power converter circuit with external input current sensing, according to one or more embodiments of the present disclosure.

[0017] Figure 3A This is an example functional block diagram of a power converter circuit according to one or more embodiments of the present disclosure.

[0018] Figure 3B This is an example functional block diagram of a power converter circuit according to one or more embodiments of the present disclosure.

[0019] Figure 4 This is a diagram illustrating an example charging function in buck regulation mode of an example power converter circuit according to one or more embodiments of the present disclosure.

[0020] Figure 5 This is a diagram illustrating an example charging function in buck 3-frequency charge pump mode according to one or more embodiments of the present disclosure.

[0021] Figure 6 This is a functional block diagram illustrating aspects of an example power converter circuit according to one or more embodiments of the present disclosure.

[0022] Figure 7 This is a block diagram illustrating an example system for implementing a power converter circuit according to one or more embodiments of the present disclosure.

[0023] Figure 8A This is a circuit diagram illustrating an example 3 level converter circuit according to one or more embodiments of the present disclosure.

[0024] Figure 8B This is a circuit diagram illustrating an example 4 level converter circuit according to one or more embodiments of the present disclosure.

[0025] Figure 8C This is a circuit diagram illustrating an example M-level converter circuit according to one or more embodiments of the present disclosure.

[0026] Figure 9 This is an example M-level converter circuit according to one or more embodiments of the present disclosure.

[0027] Figure 10 This is a block diagram of an example embodiment of a control circuit system for an M-level converter unit according to one or more embodiments of the present disclosure.

[0028] Figure 11 This is another diagram of a 4-level converter circuit according to some implementations.

[0029] Figures 12A to 12B This is a diagram illustrating how a 4-level converter circuit, according to some embodiments, discharges through an inductor during the transition from a first state to a second state.

[0030] Figure 13 An interlock circuit is shown that determines the variable time delay between closed switch pairs.

[0031] Figure 14 A feedthrough circuit is shown that defines a variable time delay between closed switch pairs according to some embodiments.

[0032] Figure 15 A circuit is shown that includes both an interlock circuit and a feedthrough circuit, according to some embodiments.

[0033] Figures 16 to 17 This is an example method for transitioning a multilevel converter from a first state to a second state according to one or more embodiments.

[0034] A better understanding of embodiments of this disclosure and its advantages will be gained by referring to the following detailed description. Note that the dimensions of the various components and the distances between them are not drawn to scale in the accompanying drawings. It should be understood that similar reference numerals are used to identify similar elements shown in one or more drawings. Detailed Implementation

[0035] This disclosure includes novel circuits, architectures, systems, and methods for more effectively and efficiently configuring and operating multilevel converter circuits. It should be understood that the various improvements disclosed herein include innovative circuits, hardware components, architectures, and related logic applicable to applications beyond multilevel converter circuits.

[0036] Figure 1 to Figure 6 Various embodiments of efficient 4-level buck and boost power converters for battery charging applications, such as single-cell lithium-ion and lithium-polymer battery applications, are illustrated. In the illustrated embodiments, the power converter is configured to deliver up to 5 amps (A) of charging current in regulation mode and in a 3-division charge pump mode, although other configurations are also within the scope of this disclosure. For example, the power converter may be configured for dual-IC operation to achieve a charging current of 9A in regulation mode and in a 3-division charge pump mode. Although a 4-level power converter is illustrated, it should be understood that the embodiments described herein are applicable to various M-level implementations, where M>=3. Furthermore, as those skilled in the art will understand, inductors and / or other components, such as inductor L1 and / or inductor L2, may be optional depending on the desired application.

[0037] For example, in some implementations, the power converter can provide an input range of approximately 4.5V to 18V to support both Universal Serial Bus (USB) and wireless input, and in reverse boost mode, the output can be programmed in 100mV steps from 4.8V to 16V, with a programmable output current limit up to 1.7A. This input voltage range can be used, for example, to support fast charging of a single lithium-ion cell via USB and wireless input. It should be understood that other voltage and current ranges and limitations may be implemented depending on the application. It should also be understood that while USB compatibility is described herein, the power converter of this disclosure can implement other wired interfaces and protocols.

[0038] In various implementations, the power converter can be implemented as a single integrated circuit (IC) (see example...). Figures 1A to 1B ), dual integrated circuits (see example) Figures 2A to 2B (or, depending on other configurations implemented. As those skilled in the art will understand, in various implementations, such as...) Figure 3B As shown, the power converter can operate as a parallel charger together with the main charger to provide the desired functionality described herein, and for example, as Figure 4 and Figure 5 As shown, this represents the desired charging functionality for various applications. Figure 3B This can represent a system-level view of a mobile architecture having a main charger and parallel chargers that accept power from a wired port (e.g., wired USB) or a wireless interface. For example, a parallel charger for one or more implementations can be represented as shown in Figures 1 to 12. Figure 3A The IC shown can be used based on some parts of the charging curve (e.g., as...). Figure 4 and Figure 5 The parallel charger charges the battery (as shown), while the main charger charges the battery according to the other part of the charging curve. In various implementations, the parallel charger can also be configured to act as the main charger, depending on the desired application. The novel architecture disclosed herein can be implemented to achieve (i) improved efficiency in low-profile solutions (e.g., at a charging current of 9A); (ii) low electromagnetic interference (EMI) fixed-frequency operation under heavy load conditions; (iii) input and output current and voltage, IC temperature monitoring and telemetry via internal integrated circuit (I2C) technology; and / or (iv) full protection including input and output undervoltage lockout (UVLO), input and output overvoltage protection (OVP), input and output overcurrent protection (OCP), and IC overtemperature with fault and warning states. In some implementations, the power converter supports 3-way frequency division, buck and boost regulation modes, dual external disconnect switch control, and / or parallel operation.

[0039] In the illustrated embodiment, the power converter is implemented as a multilevel charge pump including power switches and control circuitry. The internal bias of the power converter can be provided by the system battery via a VOUT connection (e.g., a pin). The charging input can be a USB (or other wired input) or wireless input controlled by an external FET register. In some implementations, the power converter can be programmed to different operating modes, which may include a buck regulation mode, a buck divide-3 charge pump mode, and a reverse boost mode.

[0040] In buck regulation mode, the power converter operates as a multi-level buck regulator to support USB Power Delivery (USB-PD) (or other wired protocols) or fixed input charging. During the constant current (CC) phase, the maximum charging current can be limited, for example, via a configuration register. When the input current does not reach a predetermined maximum input setting, the charging current is set to a predetermined maximum output setting. If the input current reaches the maximum input setting, the charging current is throttled and maintained at the maximum input setting. This allows for the maximum charging current while ensuring that the charging current does not exceed the battery's maximum rated current and that the input current does not trigger the adapter's overcurrent protection.

[0041] During the constant voltage (CV) phase, CV regulation can be limited, for example, by configuring a register. In operation, a single-wire sensing pin or other sensor is configured to sense the output voltage VOUT, which is compared to a predetermined value VOUT_REG stored in a register. The voltage difference between the positive and negative terminals of the battery is sensed and compared to a predetermined value VBATT_REG stored in a register. In some implementations, the single-wire sensing pin or other sensor senses VBATTP (the battery voltage at the positive terminal), and the single-wire sensing pin or other sensor senses VBATTN (the battery voltage at the negative terminal). CV is regulated to the lower of the two settings. If the VOUT sensed voltage first reaches VOUT_REG, CV is regulated to VOUT_REG. If the VBATTP sensed voltage first reaches VBATT_REG, CV is regulated to VBATT_REG. This provides rapid battery charging while preventing the voltage from exceeding safe limits.

[0042] In buck-3 divider charge pump mode (e.g., selectable by setting the corresponding register), the power converter is configured as a buck-3 divider charge distributor to support USB Programmable Power Supply (USB-PPS) or other charging protocols or programmable input charging. In some implementations, the power converter allows the USB-PPS adapter to control voltage and current and ignore conflicting settings (e.g., settings IOUT_MAX, VOUT_REG, and VBATT_REG stored in registers). In this mode, the power converter monitors the IIN_MAX setting and, when the IIN current exceeds the IIN_MAX setting, shuts down the power train (which includes switches for configuring, enabling, and disabling various operating modes) and disconnects the external FET. In the illustrated implementation, the output current is up to 10A in dual-IC operation and up to 5A in single-IC operation.

[0043] In reverse boost mode (which can be selected by setting a corresponding register), the power converter is configured as a multi-level boost regulator to power peripheral devices connected to a USB (or other wired protocol or standard) or wireless input. The power converter draws power from the system battery and regulates VIN to a programmable VOUT_REG setting from 4.8V to 16V. For example, the VIN output current limit can be set via the IIN_MAX register.

[0044] In some implementations, both the EN pin and the IC_EN bit are set to logic high (1) to enable the IC. The IC is disabled when either the EN pin or the IC_EN bit is set to logic low (0). After enabling the IC, the POR status bit is set to 1 to indicate that the IC has been newly powered on.

[0045] In some implementations, the power converter provides gate drivers to control two external N-channel MOSFETs and senses inputs to monitor the source input voltage at each FET. The external FETs can be controlled by registers (e.g., 1-bit registers V_EXTG, EXTG_EN, and EXTGX). In the illustrated implementation, the V_EXTG bit sets the gate drive voltage and can be set to 9V or 5V. The EXTGX bit selects the FET to be turned on. The EXTG_EN bit enables the gate driver to turn on the selected FET. In various implementations, the external FETs can be turned on or off independently of other IC operations, except when the IC is disabled. When the external FET is enabled, the EXT_EN_IND status bit is set to 1. The external FET may automatically turn off when a fault is detected and shutdown is triggered. If EXT1 or EXT2 detects an OVP (Out of Validation), the corresponding FET will not turn on from the shutdown mode.

[0046] In various implementations, the power link is enabled after all registers have been initialized and the target input external FET has been turned on. Sufficient time based on the capacitance on the power path can be configured between the external FET turn-on time and the power link turn-on time to minimize inrush current. Next, both the PT_EN pin and the PT_EN bit are set to logic high (1) to turn on the power link. When either the PT_EN pin or the PT_EN bit is logic low, the power link is turned off. In dual-IC operation, the slave IC power link can be configured to turn on first before the master IC. The COMP, SYNC, and SYNCH pins of both ICs are gated to control the power link and operate synchronously. The SYNC_SEL pin sets the IC to master or slave mode. Internal IC fault detection and programmable fault detection shut down the power link operation when a fault is detected.

[0047] In reverse boost mode (which can be selected by setting the corresponding register), the power converter is configured as a multi-level boost regulator to power peripherals connected to a USB (or other wired port) or wireless input. The power converter draws power from the system battery and regulates the VIN pin to a programmable VOUT_REG setting from 4.8V to 16V. The VIN output current limit is set via the IIN_MAX register.

[0048] To enable the IC, both the EN pin and the IC_EN bit are set to logic high (1). The IC is disabled when either the EN pin or the IC_EN bit is set to logic low (0). After enabling the IC, the POR status bit is set to 1 to indicate that the IC has been newly powered on. The power converter provides gate drivers to control two external N-channel MOSFETs and senses inputs to monitor the source input voltage at each FET. The external FETs are controlled by register bits such as V_EXTG, EXTG_EN, and EXTGX. For example, the V_EXTG bit sets the gate drive voltage and can be set to 9V or 5V. The EXTGX bit selects the FET to be turned on. The EXTG_EN bit enables the gate driver to turn on the selected FET. Except when the IC is disabled, the external FETs can be turned on or off independently of other IC operations. When the external FET is enabled, the EXT_EN_IND status bit is set to 1.

[0049] When a fault is detected and shutdown is triggered, the external FET can be automatically turned off. If EXT1 or EXT2 detects an OVP, the corresponding FET will not be turned on from shutdown mode. The power link is enabled after all registers have been initialized and the target input external FET is turned on. Sufficient time based on the capacitance on the power path should be allowed between the external FET turn-on time and the power link turn-on time to minimize inrush current. Next, both the PT_EN pin and the PT_EN bit are set to logic high (1) to turn on the power link. The power link is turned off when either the PT_EN pin or the PT_EN bit is logic low. In dual-IC operation, the slave IC power link is turned on before the master IC. The COMP, SYNC, and SYNCH pins of both ICs control the power link with gates and operate synchronously. The SYNC_SEL pin sets the IC to master or slave mode. When a fault is detected, internal IC fault and programmable fault detection shut down the power link operation.

[0050] Based on various implementations, example power converter initialization, example power-on sequence, and example fault handling will now be described for three different operating modes. In example buck regulation mode, the initialization and power-on sequence uses EXT1 as an example. The same sequence can be applied to EXT2, with only the EXTGX bit and the associated EXT2 register settings changing. First, EN is pulled high, and then the IC_EN bit is set to 1 to enable the IC 100µs (TBD) after EN is high. The IC starts from the POR phase, with the POR bit reporting 1 to indicate the new IC startup. Next, the POR bit is read to confirm that the IC is enabled. Then, the FREQUENCY register is set to the desired setting. In dual-IC operation, both ICs are set to the same frequency setting. In CV operation, the VOUT_REG register is set to the target regulated voltage on the VOUT sensing pin. In CV operation, the VBATT_REG register is set to the target regulated voltage on the VBATTP sensing pin. In CC operation, the IOUT_MAX register is set to the target maximum charger current, and the IIN_MAX register is set to a value below the adapter current limit. Next, the FAULT and WARNING registers are set to their desired settings. Each fault and warning is activated at different times based on the IC state and operating mode. Then, the WATCHDOG register is set to its desired settings.

[0051] The MODE register and other relevant registers are set for buck regulation mode, including power link setup and external FET enablement, while checking for faults. In dual-IC operation, the external FET is controlled by the master IC. If a fault is detected (e.g., an OVP event), the shutdown register can be set to "1" to indicate a fault shutdown event and the sequence of enabling the external FET after initiating a fault shutdown. Next, the power link is enabled. In dual-IC operation, the slave IC power link is turned on before the master IC. After enabling the power link, a bit can be set to indicate that the power link is ready and charging the battery. In some implementations, a watchdog timer can be set to periodically check the IC status during charging operations.

[0052] If a fault event is detected, the IC determines which fault events were triggered. For example, a power link might be set to enable but shut down due to a fault, or an external FET might be set to enable but shut down due to a fault. The shutdown procedure may include resetting register values ​​and re-enabling settings for power links, external FETs, or other components that were disabled due to the fault.

[0053] The example buck-3 divider power converter initialization and power-on sequence will now be described. The initialization and power-on sequence uses EXT1 as an example, but it should be understood that the same sequence applies to EXT2, with changes in the EXTGX bit and related EXT2 register settings. EN is pulled high, and then the IC_EN bit is set to 1 100µs (TBD) after EN is high to enable the IC. The IC starts from the POR phase, with the POR bit reporting 1 to indicate a new IC startup. The POR bit is read to confirm that the IC is enabled. The FREQUENCY register is set to the desired setting. In dual-IC operation, both ICs are set to the same frequency setting. The IIN_MAX register is set to a value below the adapter current limit. In buck-3 divider charge pump mode, the VOUT_REG, VBATT_REG, and IOUT_MAX registers are not used. Voltage and current regulation in buck-3 divider charge pump mode can be controlled by the PPS adapter. The FAULT, WARNING, and WATCHDOG registers are set to the desired settings. Each fault and warning is enabled at a different time based on the IC state and operating mode.

[0054] The MODE register and other registers are configured for buck-3 divider mode, including power link settings and external FET settings, while also checking for faults. If a fault is detected (e.g., an OVP event), the shutdown register can be set to "1" to indicate a fault shutdown event and the sequence of enabling the power link or external FET as needed after initiating a fault shutdown. Next, the power link is enabled. After enabling the power link, bits can be set to indicate that the power link is ready and charging the battery. In some implementations, a watchdog timer can be set to periodically check the IC status during charging operations. Voltage and current regulation in buck-3 divider charge pump mode can be controlled by the PPS adapter.

[0055] If a fault event is detected, the IC determines which fault events were triggered. For example, a power link might be set to enable but shut down due to a fault, or an external FET might be set to enable but shut down due to a fault. The shutdown procedure may include resetting register values ​​and re-enabling settings for power links, external FETs, or other components that were disabled due to the fault.

[0056] The example reverse boost mode initialization and power-up sequence will now be described. This initialization and power-up sequence uses EXT2 as an example, but the same sequence applies to EXT1, with changes to the EXTGX bit and the associated EXT1 register settings. The EN value is pulled high, and then the IC_EN bit is set to 1 to enable the IC 100µs (TBD) after EN is high. The IC starts from the POR phase, and the POR bit reports 1 to indicate a new IC startup. The POR bit is read to confirm that the IC is enabled. Next, the FREQUENCY register is set to the desired settings. In dual-IC operation, both ICs are set to the same frequency settings. The VOUT_REG register is set to the target regulated voltage at VIN. Next, the IIN_MAX register is set to the target current limit. The VBATT_REG and IOUT_MAX registers are not used in reverse boost mode. The FAULT, WARNING, and WATCHDOG registers are set to the desired settings. Each fault and warning is enabled at a different time based on the IC state and operating mode.

[0057] The MODE register and other registers are configured for reverse boost mode, including power link settings and external FET settings, while also checking for faults. If a fault is detected (e.g., an OVP event), the shutdown register can be set to "1" to indicate a fault shutdown event and the sequence of enabling the power link or external FET as needed after initiating a shutdown fault. Next, the power link is enabled. After enabling the power link, bits can be set to indicate that the power link is ready and charging the battery. In some implementations, a watchdog timer can be set to periodically check the IC status during charging operations. Voltage and current regulation in buck-3 divider charge pump mode can be controlled by the PPS adapter. In dual-IC operation, the slave IC power link is turned on before the master IC and is controlled by the master IC.

[0058] If a fault event is detected, the IC determines which fault events were triggered. For example, a power link might be set to enable but shut down due to a fault, or an external FET might be set to enable but shut down due to a fault. The shutdown procedure may include resetting register values ​​and re-enabling the power link, external FET, or other components that were disabled due to the fault. The EXT2 or VIN pin is not configured to detect OVP because it is set to output in reverse boost mode. However, if an OVP event is detected on the EXT2 or VIN pin, IC_STATUS1 and IC_STATUS2 will report the fault event.

[0059] exist Figure 7In the example system 700 shown, a power converter 720 is implemented in a host 710 (e.g., device or system) that includes a battery 730 and various system components 740. The host 710 can be any system or device that implements the power converter as described herein, including but not limited to smartphones, tablets, portable electronic devices, mobile devices, low-power electronic devices, and other electronic systems. The battery 730 may include one or more batteries, such as single-cell lithium-ion and lithium-polymer batteries, for storing power for use by the host 710.

[0060] The power converter 720 can be configured to convert the power stored in the battery 730 into the desired system voltage V. SYS The power converter 720 is used to power various system components 740, which may include one or more logic devices 742, memory 744, communication components 746, input / output (I / O) components 748, circuitry 750, and other components 752. The power converter 720 can also supply power to one or more external devices 760, such as components connected to the host 710 via wired or wireless connections, like USB-compatible devices. The power converter 720 can also be configured to receive power from an external power source 712 and convert the received power to a battery 730 for storage, or, where applicable, to system components 740 and / or external devices 760.

[0061] In various embodiments, one or more logic devices 742 and memory 744 may be configured to perform operations of host 710. Logic device 742 may be implemented as a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), microcontroller, programmable logic device (PLD), field-programmable gate array (FPGA), or other programmable logic device. Logic device 742 and other components may be configured via hard-wired, software execution, or a combination of both. In various embodiments, host 710 includes one or more memory devices designed to store data, such as software instructions executed by the logic devices. Memory may include volatile and non-volatile memory, such as random access memory (RAM), dynamic RAM (DRAM), static RAM (SRAM), non-volatile random access memory (NVRAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, hard disk drive, or other memory types. Logic devices may be configured to execute software instructions residing in memory to perform method steps and operations.

[0062] Reference Figures 8A to 8CThe converter circuit can be configured to switch between two or more switching states. One or more PWM duty cycle controllers can be provided to set the time for each switching state based on the voltage at VOUT. For example, Figure 8A It can be used as Figure 9 The diagram shows a 3-level DC-to-DC buck converter circuit 800 of the converter circuit 920. A set of four switches S1 to S4 are connected in series between VIN and circuit ground. A flying capacitor C1 is connected in series with switches S3 and S4, and in parallel with switches S1 and S2. An inductor L1 is coupled to the output capacitor COUT, and also to the node Lx between switches S1 and S2, and the voltage across the output capacitor COUT is VOUT.

[0063] In the example shown, the presence of a single flying capacitor C1 in the converter circuit 800 enables four switching states, each generating one of three voltage levels at node Lx. In the first switching state, S2 and S4 are closed, and S1 and S3 are open, effectively bypassing C1 and connecting Lx to circuit ground (voltage level at Lx = GND). In the second switching state, S2 and S4 are open, and S1 and S3 are closed, effectively bypassing C1 and connecting Lx to VIN (voltage level at Lx = VIN). In the third switching state, S1 and S4 are open, and S2 and S3 are closed, connecting C1 from VIN to Lx, thereby charging C1 with the current flowing from the inductor L1 into the load. The voltage across C1 is approximately VIN / 2, and the voltage level at Lx is also approximately VIN / 2. In the fourth switching state, S1 and S4 are closed, and S2 and S3 are open, connecting C1 from Lx to GND, thereby discharging C1 with the current flowing from the inductor L1 into the load. The voltage across C1 is approximately VIN / 2, and the voltage level at Lx is also approximately VIN / 2 (for example, this can be assumed that C1 was previously charged in state three). Therefore, the converter circuit 800 shown has two switching states that generate a voltage level VIN / 2 at the Lx node.

[0064] If the converter circuit 800 switches between switch state three and switch state four (avoiding switch state two which bypasses the flying capacitor C1), the inductor L1 sees a small jump in the voltage level at Lx from GND to only VIN / 2 and back to GND. Compared to a converter circuit with only switches S1 and S2, this results in reduced voltage ripple across the inductor L1 and less filtering to smooth VOUT.

[0065] Adding an additional series switch Sx and a flying capacitor Cx to the 2-level converter circuit 800 increases the number of switching states and the resulting voltage level between VIN and circuit ground that can be applied to the Lx node, thereby generating even less voltage ripple across the inductor L. This reduces the filtering requirements for obtaining a smooth output voltage. For example, a 4-level DC-to-DC buck converter circuit (see, for example, [link to example]). Figure 8B The circuit comprises six series-coupled switches S1 to S6 and two flying capacitors Cx (X = 2). Therefore, the 4-level converter circuit can define four voltage levels (VIN, GND, 1 / 3VIN, and 2 / 3VIN) at node LX from eight switching states (three resulting in 1 / 3VIN at Lx, and the other three in 2 / 3VIN at Lx). For some applications, VOUT is set low enough that the voltage level at node Lx alternates between GND and the next available higher voltage level. For higher output voltages, the switching mode may never use GND. For example, in a 4-level converter circuit, by alternating the Lx node between 2 / 3VIN and 1 / 3V, the output VOUT can be implemented as 0.5*VIN.

[0066] One interpretation of a multilevel converter circuit is that the flying capacitor Cx acts as a charge pump for the buck converter circuit. Unlike a standard charge pump, which is limited to a single output, a multilevel converter circuit allows the flying capacitor Cx to be coupled to generate multiple intermediate voltages. In the 4-level example, each of the two flying capacitors acts as a 1 / 3 charge pump, with the added advantage of being able to generate any input voltage (including VIN and GND) summed to a 1 / 3 ratio.

[0067] Multilevel converter circuits couple flying capacitor Cx in different combinations to lower or raise the voltage level at node Lx. As mentioned above, when using (i.e., without bypassing) a flying capacitor, the electrical energy flowing through it typically charges or discharges it, which creates control problems in maintaining the average voltage.

[0068] The solution to the charge balance problem to maintain the average voltage across a single capacitor in a 3-level converter circuit will now be described. For example, in a 3-level converter circuit, one method for generating level 1 (GND) and level 3 (VIN) voltage levels at node Lx is to not use a flying capacitor C1 for these Lx voltage levels. However, for the level 2 (VIN / 2) voltage level at Lx, two independent switching states can be used: one switching state to charge the capacitor (S3 and S2 closed, S1 and S4 open), and another switching state to discharge the capacitor (S3 and S2 open, S1 and S4 closed). The control of the 3-level converter circuit can be operated such that each time the converter circuit switches to level 2, the controller can alternate between charging and discharging the single capacitor to maintain its voltage. A voltage comparator can be used to monitor the capacitor to help determine the charging or discharging state. For example, if the capacitor voltage is below VIN / 2, the controller will select charging (third switching state), and if the capacitor voltage is above VIN / 2, the controller will select discharging (fourth switching state).

[0069] Reference Figure 8B The 4-level converter circuit 830 (X=2) illustrates the difficulty of charge balance when more capacitors are present. The level 1 voltage (GND) and level 4 voltage (VIN) at node Lx are both determined by a single switching state. However, the level 2 voltage (1 / 3VIN) and level 3 voltage (2 / 3VIN) at Lx can both be achieved by any of three different switching states. The higher the order of the multilevel converter circuit (X>2), the more switching states can produce the intermediate level between VIN and GND. The problem is more complex with the 5-level converter circuit (X=3). The level 1 voltage (GND) and level 5 voltage (VIN) at node Lx are both determined by a single switching state. However, the level 2 voltage (1 / 4VIN) and level 4 voltage (3 / 4VIN) at Lx can both be achieved by any of four different switching states, and the level 3 voltage (2 / 4VIN) at Lx can be achieved by any of six different switching states.

[0070] These examples clearly demonstrate that as the complexity of multilevel converter circuits increases, determining a suitable charge balancing method can become exceptionally difficult. As mentioned earlier, most traditional control methods rely on establishing a sequence of correlated state changes to attempt to achieve charge balance. Control systems based on long sequences of switching states typically assume that all system variables—such as input voltage and output current—are constant during the sequence. This is unrealistic for real-world environments where all system variables are often dynamic.

[0071] In the 2-level example, the converter circuit switches between two switching states: S1 is closed and S2 is open (L X Voltage level at the location = V IN ), or S1 is open and S2 is closed (L X The voltage level at that point = GND). The PWM duty cycle controller is based on V. OUT Voltage setting for the duration of each switching state, V OUT The voltage determines L X The amplitude of the average voltage at the location (note that theoretically the average L) X Voltage equals V OUT Average voltage, but due to parasitics, L X Average voltage is higher and / or lower (for negative current) V OUT (Average value). It's understandable that inductor L sees L... X The voltage level at the point from GND to V IN And a large jump back to GND. The resulting voltage ripple across inductor L requires extensive filtering to reduce V. OUT smooth.

[0072] An alternative method to reduce the voltage ripple across inductor L is to add more series switches and charge transfer capacitors as energy storage elements to transfer charge from V. IN Transfer to V OUT As described above, such charge transfer capacitors are commonly referred to as "flying capacitors" or "pump capacitors" and can be external components of an integrated circuit implementation coupled to a converter circuit. The presence of X flying capacitors Cx defines a multilevel capacitor converter circuit capable of operating according to 2... (X+1) The switch states are at node L. X M = X + 2 voltage levels are generated at that location.

[0073] Figure 8C It can be used as Figure 9 A schematic diagram of the general-purpose M-level multilevel converter unit 870 of the converter circuit 920. A set of switches S1-S[2*(M-1)] are connected in series and coupled to V. IN Between the circuit ground and the circuit. This group of switches is organized in switch pairs: S1 & S2, S3 & S4, ..., S[2*(M-2)+1] & S[2*(M-1)]. A set of M-2 flying capacitors Cx are coupled in series with some of the corresponding switches and in parallel with the switches between these switches. In terms of switch pairs, there are M-1 pairs of switches, or one more than the number of flying capacitors. An optional inductor L is coupled to the output capacitor C. OUT And coupled to node L between switches S1 and S2 X And the output capacitor C OUT The voltage across both ends is also VOUT The inductor L also acts as a virtual current source, facilitating the movement of charge between the flying capacitors Cx. This creates a very efficient form of charge transport, but introduces a charge balance problem across the flying capacitors Cx.

[0074] In various implementations, each flying capacitor Cx has a first terminal coupled between an external high-side switch S[2*x+1] and an internal high-side switch S[2*x-1], where "high-side" refers to the V0 of the converter circuit. IN Each flying capacitor Cx has a second terminal coupled between the external low-side switch S[2*x+2] and the internal low-side switch S[2*x], where "low-side" refers to the circuit ground (GND) side of the converter circuit. Therefore, for a multilevel converter unit with M=3, the first terminal of a single (X=1) flying capacitor C1 will be coupled between the external high-side switch S3 and the internal high-side switch S1, and the second terminal of capacitor C1 will be coupled between the internal low-side switch S2 and the external low-side switch S4. Thus, each flying capacitor Cx within the multilevel converter unit 870 has four switches that can affect the current flowing through it.

[0075] In some implementations, the voltage detector can be a simple comparator-type circuit that provides a voltage detector to sense relative to a reference voltage V. REF The voltage across the corresponding flying capacitor Cx, and the reference voltage V. REF Let Cx represent the desired target voltage across capacitor Cx. Each capacitor Cx can have a target average voltage to maintain an appropriate output level. For an M-level converter and capacitor Cx (where x = 1, 2, ... [M-2]), the target voltage is:

[0076]

[0077] The voltage detector can be configured to output a high / low status signal C Fx_H / L This indicates that the voltage across the corresponding flying capacitor Cx is greater than V. REF Still less than V REF C Fx_H / L The status signal is coupled to the control circuit system of the switch associated with the flying capacitor Cx.

[0078] The control circuitry system for the four switches that can affect the current flowing through the flying capacitor Cx sets the states of these switches in part based on the voltage across the flying capacitor Cx, which is measured by an associated voltage detector and transmitted via C. Fx_H / L x-state signal transmission. Therefore, for ease of understanding, it can be said that each flying capacitor Cx “controls” its own high-side and low-side switching pair. If we assume that the current in the inductor is affecting the output V...OUT When charging, there are four possible states defined for the high-side and low-side switches of each capacitor Cx.

[0079] When the external high-side and internal low-side switches associated with the flying capacitor Cx are closed and all other associated switches are open, capacitor Cx will be in a charging configuration (whether charging actually occurs may depend on the switching states of the other flying capacitors Cx). When the internal high-side and external low-side switches associated with the flying capacitor Cx are closed and all other associated switches are open, the flying capacitor Cx will be in a discharging configuration (whether discharging actually occurs may depend on the switching states of the other flying capacitors Cx). When the internal low-side and external low-side switches associated with the flying capacitor Cx are closed and all other associated switches are open, the flying capacitor Cx will be bypassed. When the external high-side and internal high-side switches associated with the flying capacitor Cx are closed and all other associated switches are open, the flying capacitor Cx will be bypassed again.

[0080] While each flying capacitor Cx can control its own high-side and low-side switches, in general, the control method disclosed herein can utilize external or internal switches that can be controlled by each corresponding capacitor. For example, refer to Figure 8B In the "external switch" method, flying capacitor C1 controls its external switches S3 and S4, flying capacitor C2 controls its external switches S5 and S6, and so on. Conversely, for example, in the "internal switch" method, flying capacitor C1 controls its internal switches S1 and S2, flying capacitor C2 controls its internal switches S3 and S4, and so on. The switching states of any pair of switches (internal or external) controlled by flying capacitor Cx can be complementary—that is, no flying capacitor Cx will simultaneously close or open both its high-side and low-side controlled switches. If each flying capacitor Cx controls its external switches, then no flying capacitor will control the remaining innermost switches S1 and S2. If, alternatively, each flying capacitor Cx controls its internal switches, then no flying capacitor will control the remaining outermost switches S[2*(M-1)] and S[2*(M-2)+1]. The switching states of the remaining switches are also complementary.

[0081] Figure 9 This is a high-level block diagram of an example circuit including a power converter 900 according to one or more embodiments of the present disclosure. In the example shown, the power converter 900 includes converter circuitry 920 and a controller 910. Converter circuitry 920 and controller 910 can be configured to implement, for example, those previously referenced. Figures 1A to 8CThis refers to any of the multilevel power converter circuits described herein, as well as others. In the illustrated embodiment, converter circuit 920 is configured to receive an input voltage VIN from a voltage source and convert the input voltage VIN into an output voltage VOUT. In some embodiments of power converter 900, auxiliary circuitry (not shown), such as a bias voltage generator, clock generator, voltage control circuitry, etc., may also be present and coupled to converter circuit 920 and controller 910.

[0082] Controller 910 receives a set of input signals and generates a set of output signals. Some of these input signals arrive along signal paths connected to converter circuit 920. These input signals carry information indicating the operating state of converter circuit 920. Controller 910 may also receive a clock signal CLK (for synchronizing converter circuit 920) and one or more external input / output signal I / Os, which may be analog, digital (encoded or direct signal lines), or a combination of both. Based on the received input signals, controller 910 generates a set of control signals that return to converter circuit 920, controlling internal components of converter circuit 920 (e.g., internal switches, such as low-voltage FETs / MOSFETs) to cause converter circuit 920 to boost or buck VIN to VOUT. In some embodiments, auxiliary circuitry (not shown) may provide various signals to controller 910 (and optionally directly to converter circuit 920), such as clock signal CLK, input / output signal I / Os, and various voltages such as universal supply voltage VDD and transistor bias voltage VBIAS.

[0083] Figure 10 It is used for M-level converter unit 1000 (e.g.) Figure 8B A block diagram of one embodiment of an advanced control circuit system 1000 (general version depicted in the diagram). An M-level converter unit 1020 is shown coupled to an inductor L and an output capacitor C. OUT The output block 1001 (conceptually, the inductor L can also be considered as being included within the M-level converter unit 1020). The advanced control circuitry system 1000 serves as a control loop coupled to the output of the M-level converter unit 1020 and to the switching control inputs of the M-level converter unit 1020. Typically, the advanced control circuitry system 1000 is configured to monitor the output (e.g., voltage and / or current) of the M-level converter unit 1020 and take into account V... INThe output load changes dynamically generate a set of switching control inputs to the M-level converter unit 1020, which attempt to stabilize the output voltage and / or current at specified values. In an alternative embodiment, the advanced control circuitry system 1000 may be configured to monitor the inputs (e.g., voltage and / or current) and / or internal nodes of the M-level converter unit 1020 (e.g., voltage across one or more flying capacitors or current through one or more power switches). Therefore, most generally, the advanced control circuitry system 1000 may be configured to monitor the voltage and / or current of the nodes (e.g., input terminals, internal nodes, or output terminals) of the M-level converter unit 1020. The advanced control circuitry system 1000 may be incorporated into or separated from the overall controller of the power converter 100 that implements the M-level converter unit 1020.

[0084] The first component includes a feedback controller 1002, which can be a conventional controller, such as a fixed-frequency voltage-mode or current-mode controller, a constant on-time controller, a hysteresis controller, or any other variant. The feedback controller 1002 is shown coupled to a V-channel from the M-level converter unit 1020. OUT In an alternative embodiment, the feedback controller 1002 may be configured to monitor the input of the M-level converter unit 1020 and / or the internal nodes of the M-level converter unit 1020. The feedback controller 1002 generates direct or indirect indications V. OUT The voltage signal at the location generally determines what needs to be done in the multilevel converter unit 1020 to maintain V. OUT The expected values ​​are: charging, discharging, or tri-state (i.e., disconnected, with no current flowing).

[0085] In the example shown, the feedback controller 1002 includes a feedback circuit 1004, a compensation circuit 1006, and a PWM generator 1008. The feedback circuit 1004 may, for example, include a feedback loop voltage detector that measures V... OUT (or V) OUT (the decayed version) and the expected V OUT The target voltage (which can be dynamic) is compared with a reference voltage, and a control signal is output to indicate V. OUT Whether it is above or below the target voltage. The feedback loop voltage detector can be implemented using a comparator device such as an operational amplifier (op-amp) or a transconductance amplifier (gm amplifier).

[0086] The compensation circuit 1006 is configured to stabilize the closed-loop response of the feedback controller 1002 by: avoiding the unintentional creation of positive feedback that may cause oscillations, and controlling overshoot and ringing in the step response of the feedback controller 1002. The compensation circuit 1006 can be implemented in known ways and may include LC and / or RC circuits.

[0087] PWM generator 1008 generates an actual PWM control signal that ultimately sets the duty cycle of the switching of multilevel converter unit 1020. Furthermore, in some embodiments, PWM generator 1008 may transmit an additional optional control signal CTRL, which indicates, for example, V... OUT The magnitude of the difference between the voltage and the reference voltage (thus indicating certain levels of the M-level converter unit 1020 that should be bypassed to achieve a higher or lower level) and the direction of that difference (e.g., V). OUT (Whether it is greater than or less than the reference voltage). In other embodiments, the optional control signal CTRL can be generated from the output of the compensation circuit 1006 or the output of the feedback circuit 1004, or from a source coupled to, for example, V. OUT A separate comparator (not shown) is used. One purpose of the optional control signal CTRL is for advanced control algorithms, where it may be beneficial to know V. OUT How far from the target output voltage, thus allowing for V OUT The inductor L is charged faster when it is severely underregulated.

[0088] The second component includes a multilevel controller 1010. The main function of the multilevel controller 1010 is to select the desired V each time the output voltage level is selected. OUT The switching state maintains the charge balance state on the flying capacitor within the M-level converter unit 1020, regardless of which switching state or which switching states were used in the past.

[0089] The multilevel controller 1010 includes a voltage level selector 1012, which receives a PWM control signal and an additional control signal CTRL (if available). Furthermore, the voltage level selector 1012 can be coupled to V... OUT and / or V IN In some embodiments, and coupled to a corresponding flying capacitor C coupled to the M-level converter unit 1020. Fx The high / low status signal C of the voltage detector Fx_H / L The function of voltage level selector 1012 is to convert the received signal into a target output voltage level (e.g., on a cycle-by-cycle basis). Voltage level selector 1012 will typically consider at least V...OUT and V IN To determine which target level should charge or discharge the output of the M-level converter unit 1020 at the desired rate. For example, in a 6-level converter circuit, the available target levels are level 1 (GND) and level 2 (1 / 5V). IN Level 3 (2 / 5V) IN ), Level 4 (3 / 5V) IN ), Level 5 (4 / 5V) IN ) and level 6 (V) IN These levels can be represented as count values ​​from 1 to 6 (or 0 to 5).

[0090] As an example, in a 4-level converter circuit, if V IN =12V and V OUT The nominal voltage should be 3V, so the voltage level selector 1012 can indicate that the target voltage "2" can be selected, thus enabling the voltage level selection in L. X 1 / 3V is generated at the location IN The voltage level (i.e., 4V). The PWM control signal sets the duty cycle between this target level and another target level (e.g., GND), such that L... X The average voltage level at that location is approximately 3V.

[0091] Generally, for steady-state operation, you can choose the value closest to V. OUT The target voltage level is selected to simplify the selection algorithm for charging or discharging inductor L. Generally, for transient responses, a target voltage higher than the nearest target voltage (for charging) or a lower target voltage (for discharging) can be selected to quickly charge or discharge inductor L. For example, voltage level selector 1012 can be implemented as a lookup table (LUT) or as a comparison circuit system and combinational logic or a more general processor circuit system. In some implementations, voltage level selector 1012 can implement advanced methods (described below) that attempt to accelerate charging or discharging based on additional factors such as inductor voltage drop, load transients, the magnitude of output deviation, and / or external input signals from external sources. The output of voltage level selector 1012 may include duty cycle information (e.g., derived from the input PWM control signal) and switching states.

[0092] The output of voltage level selector 1012 is coupled to multilevel switch state selector 1014, which is typically coupled to a state signal C from a voltage detector used for flying capacitor Cx. Fx_H / LTaking into account the target level generated by voltage level selector 1012, multilevel switch state selector 1014 determines the mode of the switch state for the desired output level, which typically achieves charge balance across capacitor Cx. Multilevel switch state selector 1014 can be implemented, for example, as a comparison circuit system and combinational logic, as a lookup table (LUT), or as a more general processor circuit system. The output of multilevel switch state selector 1014 is coupled to the switch of multilevel converter unit 1020 (via appropriate level shifter circuitry and driver circuitry, as may be required by a particular converter unit) and includes the mode of switch state setting determined by multilevel switch state selector 1014. The mode of switch state setting selects the configuration of the switches within multilevel converter unit 1020.

[0093] Typically (but not always), for PWM-based control systems, voltage level selector 1012 and M-level switch state selector 1014 change their states only when the PWM signal changes. For example, when the PWM signal goes high, voltage level selector 1012 selects the level that causes inductor L to charge, and M-level switch state selector 1014 sets the version of that level. Then, when the PWM signal goes low, voltage level selector 1012 selects the level that causes inductor L to discharge, and M-level switch state selector 1014 sets the version of that level to use. Therefore, voltage level selector 1012 and M-level switch state selector 1014 typically change their states only when the PWM signal changes (the PWM signal is actually their clock signal). However, there may be situations or events where it is expected that the CTRL signal will change the state of voltage level selector 1012. Furthermore, there may be situations or events where, for example, when a severe mid-cycle imbalance occurs, it is expected that the CTRL signal will change the state of voltage level selector 1012. Fx_H / L The status signal causes the M-level switch status selector 1014 to select a specific configuration of the power switch settings. In some embodiments, including a timing function may be useful: this timing function forces the M-level switch status selector 1014 to periodically re-evaluate the optimal version of the status, for example, to avoid being “stuck” at a level for an extended period, which could lead to charge imbalance.

[0094] Figure 10 A significant advantage of the control circuit system shown is that it enables the generation of voltages in the boundary region between voltage levels, representing output voltages that conventional multilevel DC-to-DC converter circuits cannot achieve.

[0095] In the alternative unregulated charge pump implementation, the feedback controller 1002 and voltage level selector 1012 can be omitted, and instead, a clock signal CLK can be applied to an M-level switch state selector 1014. The M-level switch state selector 1014 will generate a switch state setting pattern that periodically causes the flying capacitor Cx to undergo charge balancing, regardless of which switch state or switching states were used in the past (instead of cycling through a predefined sequence of states). This ensures that if V IN When changes occur or abnormal events happen, the system will usually seek charge balance for the flying capacitor Cx.

[0096] In some implementations, the M-level switch state selector 1014 can select the current I flowing through the inductor L via an optional current measurement input 1016 (which can be implemented in a conventional manner). L Taken into consideration.

[0097] In an M-level multilevel converter circuit, level 1 (e.g., GND) or level M (e.g., V) is implemented. IN The switching configuration effectively bypasses the flying capacitor Cx. Conversely, for all intermediate voltage levels, at least one flying capacitor Cx is coupled to V. OUT Furthermore, there are always at least two switching configurations that can achieve any intermediate voltage level. For any given intermediate voltage level, at least one switching configuration results in charging of the associated flying capacitor, and at least one other switching configuration results in discharging of the associated flying capacitor. One aspect of this disclosure is the implementation of any achievable output voltage V that requires an intermediate voltage level. OUT Both can be achieved by: dynamically selecting the switch configuration mode—that is, selecting the appropriate level by choosing the switch configuration without considering or remembering any previous switching cycles, and doing so in a way that purposefully selects the charging or discharging switch configuration, which also balances the charge across the capacitor Cx.

[0098] The embodiments of this disclosure relate to the positive inductor L current (charging V). OUT Use the following method:

[0099] (1) The flying capacitor Cx that needs to be charged will be configured to close its charging switch (the external high-side switch in the external switch control method, or the internal low-side switch in the internal switch control method); and

[0100] (2) The flying capacitor Cx that needs to be discharged will be set to close its discharge switch (the external low-side switch in the external switch control method, or the internal high-side switch in the internal switch control method).

[0101] For the negative inductor current L (discharge V) OUT This reverses the selection of the switch. Accordingly:

[0102] (1) The flying capacitor Cx that needs to be charged will be configured to close its charging switch (the external low-side switch in the external switch control method, or the internal high-side switch in the internal switch control method); and

[0103] (2) The flying capacitor Cx that needs to be discharged will be set to close its discharge switch (external high-side switch in external switch control method, or internal low-side switch in internal switch control method).

[0104] Note again that whether a particular flying capacitor Cx actually charges generally depends on the switching states of all other flying capacitors. For a flying capacitor C(x) to actually charge or discharge, the next inward (if any) flying capacitor C(x-1) (for external switching control methods) or the previous outward (if any) flying capacitor C(x+1) (for internal switching control methods) must be set to the opposite state (i.e., discharging or charging) to prevent bypassing.

[0105] For a voltage level that can be generated M—that is, from level 1 (e.g., GND) to level M (e.g., V)— IN For any M-order multilevel converter circuit, the following switch counting rule applies to any level m:

[0106] (1) Mm low-side switches must be set to closed (on);

[0107] (2) m-1 high-side switches must be set to closed (on); and

[0108] (3) Switches that do not need to be turned on must be set to off (disconnected).

[0109] Considering these switch counting rules, the following general capacitor control method applies to each state change of the multilevel switch state selector 1014:

[0110] Step 1) Select the flying capacitor that was not previously selected;

[0111] Step 2) If the voltage of the selected flying capacitor is above its Vtarget, and there are remaining (i.e., not set by this method in this cycle) low-side or high-side switches that can be set to close to enable the discharge path of the selected flying capacitor, then those switches that enable the discharge path of the selected flying capacitor are set to close, one or more appropriate counters are decremented (e.g., for the number of low-side switches set to close and the number of high-side switches set to close), and the current flying capacitor is marked as "complete" (i.e., selected); otherwise (since the voltage of the selected flying capacitor is below its Vtarget), the switches that enable the charging path of the selected flying capacitor are set to close, and the current flying capacitor is marked as "complete".

[0112] Step 3) Repeat step 1 until all flying capacitors have been selected;

[0113] Step 4) For the remaining pair of switches, set the high-side switch or the low-side switch to closed based on the switch counting rules and the counter value.

[0114] Using the general capacitor control method described above, more specific multilevel charge balance control methods can be created. For example, an example can be found in U.S. Patent Publication No. 20230148059, which is incorporated herein by reference in its entirety.

[0115] Figure 11 This is another diagram of a 4-level converter circuit according to some embodiments. See reference... Figure 8B The discussed four-level converter circuit comprises six series-coupled switches S1 to S6 and two flying capacitors C1 and C2. The four-level converter circuit can define four voltage levels (VIN, GND, 1 / 3VIN, and 2 / 3VIN) at node LX based on eight switch states. Although the embodiments discussed herein are applicable to four-level converter circuits that can operate in buck or boost modes, these embodiments are also applicable to three-level converter circuits, other types of M-level converter circuits, and other converters with stacked switches.

[0116] In some implementations... Figure 11 The switches S1 to S6 shown can be implemented as MOSFETs, including N-MOSFETs and P-MOSFETs.

[0117] Each node between switches S1 and S6 may have parasitic capacitances, as shown by C11 to C15. For example, the LX node may have parasitic capacitance C11, the PA node may have parasitic capacitance C12, the PB node may have parasitic capacitance C14, the CA node may have parasitic capacitance C13, and the CB node may have parasitic capacitance C15. Depending on the voltage at the LX node, parasitic capacitances C11 to C15 may have some associated voltages. When the 4-level converter circuit changes the voltage level in buck mode (e.g., from VIN to 2 / 3VIN at the LX node), the 4-level converter circuit can control all switches S1 to S6 to discharge the LX node to a voltage consistent with level 2 / 3VIN. For example, when switches S1 to S6 are closed, the voltages corresponding to parasitic capacitances C11 to C15 can be discharged. The voltages corresponding to parasitic capacitances C11 to C15 may be discharged via GND, which may result in unnecessary energy loss. Alternatively, the voltage corresponding to the parasitic capacitances C11 to C15 can also discharge the inductor L1, which can minimize energy loss in the 4-level converter circuit because the energy is recycled to the output VOUT.

[0118] As discussed above, the 4-level converter circuit switches states to change the voltage level. Conventionally, in buck mode, the 4-level converter circuit can open all switches S1 to S6 and then close switches S1 to S6 to discharge the LX node. Alternatively, in buck mode, the 4-level converter circuit can close all switches S1 to S6 and then open switches S1 to S6 to charge the LX node. However, such switching results in energy loss due to the parasitic capacitances C11 to C15 at the LX, PA, PB, CA, and CB nodes.

[0119] The implementation involves closing switches S1 to S6 in a sequence that maximizes the amount of energy passing through inductor L1 and reduces power loss through GND in the 4-level converter circuit. Switches S1 to S6 can be divided into pairs such that switches S1 and S2 form pair P1 (e.g., P1(S1,S2)), switches S3 and S4 form pair P2 (e.g., P2(S3,S4)), and switches S5 and S6 form pair P3 (e.g., P3(S5,S6)). Figure 11As shown, switches S1 and S2 in pair P1 are the innermost switches in the 4-level converter circuit and are located on either side of the LX node. Switches S3 and S4 in pair P2 are the next innermost switches and are located on either side of switches S1 and S2 in pair P1. Switches S5 and S6 in pair P3 are the outermost switches and are located on either side of switches S3 and S4 in pair P2. When the 4-level converter circuit changes states corresponding to different voltage levels in buck mode, all switches S1 through S6 are open. Next, the switches in pairs P1 through P3 can be closed sequentially from the innermost pair to the outermost pair. When pairs P1 through P3 are closed sequentially, one or both switches in each pair of P1 through P3 can be closed. For example, switches S1 and / or S2 in pair P1 can be closed first, followed by switches S3 and / or S4 in pair P2, and then switches S5 and / or S6 in pair P3. In this way, parasitic capacitances C11 to C15 are discharged through inductor L1, reducing power losses in the 4-level converter circuit. In some implementations, the outermost switches, such as switches S5 and / or S6 in P3, can be closed last, regardless of the order in which switches S1 to S4 in P1 to P2 are closed.

[0120] In some cases, there may be a predetermined delay between closing each switch pair and closing the next switch pair. For example, after closing switches S1 and S2 for P1, the 4-level converter circuit may wait for a predetermined time period before closing switches S3 and S4 for P2, and then wait for another predetermined time period before closing switches S5 and S6 for P3.

[0121] A similar technique can be applied to boost mode. In boost mode, switches S1 to S6 can be initially closed and then opened to draw maximum energy from inductor L1 to increase the voltage across parasitic capacitances C11 to C15. In this case, the switches for P1 to P3 can be opened sequentially from the innermost pair P1 to the outermost pair P3. For example, switches S1 and S2 in pair P1 can be opened first, followed by switches S3 and S4 in pair P2, and then the outermost switches S5 and S6 in pair P3.

[0122] The above implementation differs from the conventional technique where switches S1 to S6 are unpaired. In the conventional technique, switches S6, S4, and S2 can be closed first during level transitions. For example, switch S6 can be closed first, followed by switch S4, and then switch S2. Because parasitic capacitance C14 at node PB and parasitic capacitance C12 at node PA exist between switches S6 and S4 and between switches S4 and S2, respectively, the energy associated with parasitic capacitances C14 and C12 is dissipated through ground GND, resulting in energy loss in the 4-level converter circuit. For example, suppose parasitic capacitances C11, C12, and C14 are set to 5V, and the 4-level converter circuit attempts to reduce the voltage at node LX to 0V. In buck mode, using the conventional method, closing switch S6 will reduce the voltage at parasitic capacitor C14 to zero through ground GND. Next, closing switch S4 will reduce the voltage at parasitic capacitor C12 to zero through ground GND, and then closing switch S2 will reduce the voltage at parasitic capacitor C11 to zero through ground GND. This results in excessive energy loss.

[0123] However, using the implementation discussed herein, switches S1 and S2 in P1 are first closed, causing the 5V parasitic capacitance C11 to discharge across inductor L1. Next, switches S3 and S4 in P2 are closed, causing the 5V parasitic capacitances C12 and C13 to discharge across inductor L1. Finally, switches S5 and S6 are closed, causing the 5V parasitic capacitances C14 and C15 to discharge across inductor L1, thereby minimizing the energy loss of the 4-level converter circuit.

[0124] In some implementations, whether switches S1 and S2 are sequentially closed (in buck mode) or open (in boost mode) can depend on whether the polarity of the current flowing through inductor L1 changes. For example, in boost mode, when the 4-level converter circuit increases the voltage at node LX to VIN, current can flow through inductor L1 into node LX. If the next step is to increase the voltage at node LX to VIN, switches S1 to S6 are opened sequentially by disconnecting pairs P1 to P3. Specifically, switches S1 and S2 in P2 are opened, followed by switches S3 and S4 in P2, and then switches S5 and S6 in P3. However, if the next step is to decrease the voltage at node LX, switches S1 to S6 can all be opened instead of sequentially opening switches S1 to S6 as pairs P1 to P3. For example, suppose the voltage at node LX is 5V, and the next state will cause the voltage at node LX to reach 12V (which is equal to the voltage at VIN). In this scenario, switches S1 through S6 can be opened sequentially as pairs of P1 through P3 to discharge parasitic capacitances C11 through C15 through inductor L1. In another example, suppose the voltage at node LX is 5V, and the next state will cause the voltage at node LX to reach 1V. In this case, the current across inductor L1 will switch polarity and flow away from node LX towards VOUT. In this case, switches S1 through S6 can be opened immediately instead of sequentially as pairs of P1 through P3.

[0125] In some implementations, once the controller (e.g., controller 1002) determines the next voltage level of the 4-level converter circuit and initiates a state change from one level to another, controller 1002 can determine the sequence in which P1 to P3 can be turned on and off sequentially.

[0126] Figures 12A to 12B These are diagrams 1200A to 1200B illustrating how a 4-level converter circuit discharges through an inductor according to some embodiments. Figure 12A A 4-level converter circuit is shown, comprising switches S1L, S2L, S3L, S1H, S2H, and S3H, and capacitors C1 and C2. Furthermore, switches S1L and S1H are grouped together as a pair P1, switches S2L and S2H as a pair P2, and switches S3L and S3H as a pair P3.

[0127] For illustrative purposes only, it is assumed that the 4-level converter circuit operates at level 2, where VIN = 15V, C1 = 5V, C2 = 10V, and VOUT = 3.2V. Furthermore, node CB = 15V, node CA = 10V, node LX = 10V, node PA = 5V, and node PB = 5V. Additionally, parasitic capacitances C11 to C15 can be approximately 300 picofarads (pF), ranging from 150pF to 450pF. In some cases, parasitic capacitances C12 and C13, and C14 and C15, can have the same or approximately the same values.

[0128] Assume a 4-level converter circuit transitions from state level 2 to state level 0. At level 0, the voltage at node LX is 0V. Figure 12B This is a graph showing the discharge curve of node LX during the transition when switches S1L, S2L, S3L, S1H, S2H and S3H are closed as pairs P1 to P3, and the parasitic capacitances at nodes LX, CA, CB, PA and PB are discharged through inductor L1.

[0129] Assume that at time t1, the transition from level 2 to level 0 begins, and all switches S1L, S2L, S3L, S1H, S2H, and S3H are turned off (e.g., open). From time t1 to t2, node LX discharges from 10V to 5V through inductor L1. At time t2, node LX = 5V, and due to parasitic capacitances C12 and C13, it has the same voltage as node PA. At time t2, switches S1L and S2L in P1 close, causing parasitic capacitances C12 and C13 at the corresponding nodes PA and CA to discharge through inductor L1. Furthermore, at or shortly thereafter at time t2, switches S2L and S2H in P2 close because at time t2, node PA = node PB = 5V. Once switches S2L and S2H in P2 close, parasitic capacitances C14 and C15 at the corresponding nodes PB and CB discharge through inductor L1. At time t3, the voltage at nodes LX, PA, and PB reaches 0V, which causes switches S3L and S3H to P3 to close.

[0130] Back Figure 11In some implementations, there may be a time delay between the opening or closing of the switches in each pair of P1 to P3 (depending on the boost or buck mode). This delay can be a fixed delay or a variable delay. For example, in the pair of P1, switch S2 may close first, while switch S1 may close after a time delay. A fixed delay may limit the amount of energy that inductor L1 can draw, but it is probably the simplest to implement. A variable delay can vary based on the current. For example, the time delay may decrease for high currents (e.g., currents above certain current thresholds) or increase for low currents (e.g., currents below certain current thresholds). Alternatively, a variable time delay may decrease as the current increases. The goal of using a fixed or variable time delay is to balance the efficiency of the 4-level converter circuit with the expectation of saving excess energy.

[0131] In some implementations, one method for determining the variable time delay between the two switches in a closed pair P is to use a comparator at node LX (or at another node during discharge). The comparator compares the voltage at node LX with the voltage level of the next state after the first switch in the pair is closed (e.g., VIN, GND, 1 / 3VIN, and 2 / 3VIN). When the voltage at node LX drops below the next voltage level, the second switch in the pair can close. For example, suppose node LX is at 8V, VIN = 12V, and the next voltage level is 1 / 3VIN, or 4V. After switch S2 closes, the comparator can monitor the voltage at node LX until it drops below 4V. Once the voltage at node LX drops below 4V, switch S1 in pair P1 can also close. Subsequent processing can also be repeated sequentially for pairs P2 and P3 in a 4-level converter circuit.

[0132] Figures 13 to 15 Block diagrams 1300 to 1500 illustrate circuits implementing variable delay according to some embodiments. Figure 13 An interlock circuit 1300 is shown that can determine a variable time delay between closed switch pairs. For illustrative purposes only, the interlock circuit is shown between switches S1 and S2 in pair P1, although the circuit can be applied to other switch pairs. Figure 13Gate driver 1302 and gate 1304 are shown. Gate driver 1302 controls switch S1, and gate 1304 controls switch S2. Both gate driver 1302 and gate 1304 receive a PWM signal 1306. The PWM signal 1306 sets the voltage at the next voltage level. The output of gate driver 1302 is interlocked with the LX node and also with the input to gate 1304. Once switch S1 is closed, the interlock mechanism measures the voltage at the LX node and turns on gate 1304 when gate driver 1302 is turned off. When the voltage at the LX node is lower than the voltage at the next voltage level, gate driver 1302 is turned off. The variable time delay between the closing of switch S2 and switch S1 is the dead time, which allows inductor L1 to discharge the voltage at the LX node.

[0133] Figure 14 A feedthrough circuit 1400 is shown that determines a variable time delay between closed switch pairs. For illustrative purposes only, an interlocking circuit is shown between switches S1 and S2 in pair P1, although this circuit can be applied to other switch pairs. Figure 14 Two gate drivers, 1402 and 1404, are shown. Gate driver 1402 is connected to rising edge delay circuit 1406, and gate driver 1404 is connected to an inverting rising edge delay circuit 1408. When rising edge delay circuits 1406 and 1408 receive PWM signal 1410, they delay the PWM signal 1410 on the rising edge, not the falling edge. The time delay caused by rising edge delay circuits 1406 and 1408 results in a delay in gate drivers 1402 and 1404 when switches S2 and S1 are closed. The variable time delay between the closing of switch S2 and switch S1 is the dead time. This, in turn, results in a time delay during the discharge of inductor L1 to the LX node.

[0134] Figure 15 A circuit including both an interlock circuit and a feedthrough circuit is shown, which can determine the variable time delay between closed switch pairs. For illustrative purposes only, the interlock circuit is shown between switches S1 and S2 in pair P1, although this circuit can be applied to other switch pairs. Figure 15 Two gate drivers, 1502 and 1504, are shown. Gate driver 1502 is connected to rising edge delay circuit 1506, and gate driver 1504 is connected to rising edge delay circuit 1508. When rising edge delay circuits 1506 and 1508 receive PWM signal 1510, they delay the PWM signal 1510 on the rising edge, rather than on the falling edge.

[0135] in addition, Figure 15The circuitry includes a comparator 1512 and a time delay circuit 1514. The comparator 1512 measures the voltage at node LX and determines whether the voltage at node LX is below 0V or the next level voltage. The time delay circuit 1514 is set to a fixed time value, which is measured from the time switch S1 is closed. Once the time delay exceeds the fixed time value, the time delay circuit 1514 is turned on. The outputs of the comparator 1512, the time delay circuit 1514, and the rising edge delay circuit 516 are fed as inputs to the gate 1518. The gate 1518 can be an or-ing circuit that is turned on once the voltage at node LX is below 0V or the next level voltage, or when the output of the time delay circuit 1514 exceeds the fixed time value, or when the rising edge delay circuit 1508 is on its rising edge. When the voltage at the LX node is below 0V, when the time delay exceeds a fixed value, or when the PWM signal is at its rising edge, the output of gate 1518 is fed to gate driver 1504, causing gate driver 1504 to drive the voltage. The time delay caused by the rising edge delay circuits 1506, 1508, and 1516 causes delays in gate drivers 1502 and 1504 when switches S1 and S2 are closed. This, in turn, results in a time delay during the discharge of inductor L1 to the LX node.

[0136] Figure 16 This is an example method 1600 for transitioning a multilevel converter from a first state to a second state according to one or more embodiments. Method 1600 can be implemented using Figures 1 to 1600. Figure 15 The components and circuits discussed in the previous section are used to implement this. In method 1600, the multilevel converter operates in buck mode, where current flows from node LX through inductor L1 and to VOUT.

[0137] In operation 1602, signals are generated for switching the multilevel converter circuit. For example, controller 1002 generates a signal to switch the multilevel converter circuit from a first state to a second state. As discussed above, the switches of the multilevel converter can be divided into pairs, where the two innermost switches form a pair P1, the two switches adjacent to the innermost switches and on either side of the innermost switches form a pair P2, and so on. The two outermost switches form a pair Pn, where n is the number of switches divided by 2.

[0138] In operation 1604, all switches are turned off. For example, all switches in a multilevel converter circuit, such as switches S1 to S6 in a 4-level converter circuit, are turned off.

[0139] In operation 1606, the switches are closed sequentially. For example, the switch to P1 is closed first, then the switch to P2, and so on, until the switch to Pn is closed. In some cases, there may be a fixed time delay between closing the same pair of switches. In other cases, there may be a variable time delay between closing the same pair of switches. The variable time delay can be set using interlocking circuits, feedthrough circuits, and combinations of interlocking and feedthrough circuits.

[0140] Figure 17 This is an example method 1700 for switching a multilevel converter from a first state to a second state according to one or more embodiments. Method 1700 can be implemented using Figures 1 to 1700. Figure 15 The components and circuits discussed in the previous section are used to implement this. In method 1700, the multilevel converter operates in boost mode, where current flows to node LX, through inductor L1, and out of VOUT.

[0141] In operation 1702, signals are generated for switching the multilevel converter circuit. For example, controller 1002 generates a signal to switch the multilevel converter circuit from a first state to a second state. As discussed above, the switches of the multilevel converter can be divided into pairs, where the two innermost switches form a pair P1, the two switches adjacent to the innermost switches and on either side of the innermost switches form a pair P2, and so on. The two outermost switches form a pair Pn, where n is the number of switches divided by 2.

[0142] In operation 1704, all switches are turned on. For example, all switches in a multilevel converter circuit, such as switches S1 to S6 in a 4-level converter circuit, are closed.

[0143] In operation 1706, the switches are opened sequentially. For example, the switch to P1 is opened first, then the switch to P2 is opened, and so on, until the switch to Pn is opened. In some cases, there may be a fixed time delay between opening the same pair of switches. In other cases, there may be a variable time delay between opening the same pair of switches. The variable time delay can be set using interlocking circuits, feedthrough circuits, and combinations of interlocking and feedthrough circuits.

[0144] Other aspects of this disclosure include the following:

[0145] Aspect 1 includes a system comprising: a controller configured to transition a multilevel converter circuit from a first state corresponding to a first voltage level to a second state corresponding to a second voltage level, wherein the controller for the transition is configured to: control a switch of the multilevel converter circuit to open to discharge parasitic capacitance at a node through an inductor, or control a switch of the multilevel converter circuit to close to charge a node through an inductor, wherein the switches are arranged in pairs and include a first pair and a second pair, wherein the first pair includes an innermost switch and the second pair includes a switch on each side of the innermost switch, and wherein the node is located between the innermost switches of the first pair or between the switch pairs; and control the switch pairs to sequentially close to discharge the node through an inductor, or control the switch pairs to sequentially open to charge the node through an inductor, wherein the closing or opening of the switches begins with the first pair, followed by the second pair.

[0146] Aspect 2 includes the system according to aspect 1, wherein the switches of the multilevel converter circuit are arranged in series.

[0147] Aspect 3 includes the system according to aspect 1, wherein, in order to control the switch pair, the controller is further configured to: determine the polarity of the current through the inductor in a first state; and, based on the change in the polarity of the current from the first state to the second state, close or open the switch pair of the multilevel converter circuit at approximately the same time, or close or open the switch pair sequentially.

[0148] Aspect 4 includes the system according to aspect 1, wherein the switch pair further includes a third switch pair, with one switch on each side of the switches in the second pair.

[0149] Aspect 5 includes the system according to aspect 4, wherein, in order to switch the multilevel converter circuit, the controller is further configured to close the third pair of switches to discharge the node or open the third pair of switches to charge the node after closing or opening the second pair of switches.

[0150] Aspect 6 includes the system according to aspect 1, wherein one of the switch pairs has a time delay between closing the first and second switches in the pair.

[0151] Aspect 7 includes the system according to aspect 6, wherein the time delay is a fixed time delay or a variable time delay.

[0152] Aspect 8 includes the system described in aspect 6, wherein the time delay is different for one pair and another pair.

[0153] Aspect 9 includes the system according to aspect 6, wherein the time delay depends on the current through the inductor.

[0154] Aspect 10 includes the system according to aspect 6, wherein the time delay depends on a comparator configured to measure the voltage at the node and the voltage level corresponding to the second state.

[0155] Aspect 11 includes the system according to aspect 6, wherein the time delay depends on a first switch and a second switch coupled to the pair and includes an interlocking circuit comprising a gate driver and a gate, wherein the gate driver is configured to receive a PWM signal and generate an output, wherein the output causes the first switch of the pair to close or open, and the output is interlocked with the node, and wherein the gate is configured to receive the PWM signal and the output of the gate driver and generate an output that causes the second switch of the pair to close.

[0156] Aspect 12 includes the system according to aspect 6, wherein the time delay depends on a feedthrough circuit coupled to the pair and includes a first rising edge delay circuit and a first gate driver coupled to a first switch in the pair, and a second rising edge circuit and a second gate driver coupled to a second switch in the pair, wherein the first rising edge circuit and the second rising edge circuit receive a PWM signal and delay the PWM signal on the rising edge, and wherein the delay causes a time delay between the closing or opening of the first switch and the second switch.

[0157] Aspect 13 includes the system according to aspect 6, wherein the time delay depends on the interlocking circuit and feedthrough circuit coupled to the first and second switches of the pair.

[0158] Aspect 14 includes a multilevel converter circuit comprising: a plurality of switches arranged in pairs, wherein a first pair comprises two innermost switches, and a second pair comprises two switches on either side of the two innermost switches, wherein a first switch in the second pair is connected in series to one of the innermost switches in the first pair, and a second switch in the second pair is connected in series to the other switch in the innermost pair, and wherein, during a transition of the multilevel converter circuit from a first state to a second state, one or more switches in the switch pairs are sequentially opened or closed, starting with the first pair and then the second pair; and an inductor arranged between the first switch pairs, wherein the opening or closing of one or more switches in the switch pairs charges or discharges parasitic capacitance at nodes between or between the first switch pairs via the inductor.

[0159] Aspect 15 includes a multilevel converter circuit according to aspect 14, wherein each switch pair has a time delay independent of other switch pairs, wherein the time delay is between opening or closing the first and second switches of each pair.

[0160] Aspect 16 includes a multilevel converter circuit according to aspect 14, wherein one or more switches in a switch pair are sequentially opened or closed to reduce power loss during transitions between a first state associated with a first voltage and a second state associated with a second voltage.

[0161] Aspect 17 includes the multilevel converter circuit according to aspect 14, further comprising: a third switch pair on each side of the first and second switches of the second pair, wherein the first switch of the third pair is coupled in series with the first switch of the second pair, and the second switch of the third pair is coupled in series with the second switch of the second pair, wherein the third switch pair is sequentially opened or closed after the second switch pair.

[0162] Aspect 18 includes the multilevel converter circuit according to aspect 14, wherein the plurality of switches are MOSFETs.

[0163] Aspect 19 includes a method comprising: generating a signal for switching a multilevel converter circuit from a first state associated with a first voltage to a second state associated with a second voltage, wherein the multilevel converter circuit includes a plurality of switches arranged in non-overlapping pairs; and, in response to the signal, switching the multilevel converter circuit from the first state to the second state, wherein the switching further comprises: closing or opening all switches in the multilevel converter circuit; and sequentially opening closed switches in the pairs or sequentially closing open switches in the pairs, starting from the innermost pair and ending with the outermost pair, to charge or discharge parasitic capacitance at nodes via inductors, wherein the nodes are located between the innermost pairs or between the non-overlapping pairs.

[0164] Aspect 20 includes the method according to sequence 19, wherein the non-overlapping pair includes the innermost switch pair and a subsequent switch pair having a switch on either side of the innermost switch pair and immediately adjacent to the preceding switch pair.

[0165] General benefits and advantages of multilevel power converters

[0166] Embodiments of the present invention improve the power density and / or power efficiency of integrated circuits and circuit modules or blocks. As will be understood by those skilled in the art, embodiments of the present invention, utilized in a critical manner, advantageously influence system architecture, including lower power consumption and / or longer battery life. Therefore, the present invention specifically includes system-level embodiments inventively implemented through inclusion in large-scale system designs and applications.

[0167] More specifically, multilevel power converters offer or achieve numerous benefits and advantages, including:

[0168] - Adaptability to applications where the input and / or output voltages can have a wide dynamic range (e.g., different battery input voltage levels, different output voltages);

[0169] - Improved efficiency of operating time for devices that run on portable electrical energy sources (batteries, generators, or fuel cells using liquid or gaseous fuels, solar cells, etc.);

[0170] - Improved efficiency in situations where thermal management, particularly protecting other components (e.g., displays, nearby ICs) from overheating, is important;

[0171] - To achieve design optimization of power efficiency, power density and form factor of power converters - for example, smaller multilevel power converters may allow the power converter to be placed closer to the load, thus improving efficiency and / or reducing the overall bill of materials;

[0172] - The ability to utilize the performance of smaller, lower-voltage transistors;

[0173] - Adaptability to applications where the power source can vary widely, such as batteries, other power converters, generators, or fuel cells using liquid or gaseous fuels, solar cells, line voltage (AC) and DC voltage sources (e.g., USB, USB-C, Power over Ethernet, etc.);

[0174] - Adaptability to applications where the load can vary widely, such as general ICs (including microprocessors and memory ICs), motors and actuators, transducers, sensors and displays (e.g., all types of LCDs and LEDs);

[0175] - Capabilities to be implemented in a variety of IC technologies (e.g., MOSFET, GaN, GaAs, and bulk silicon) and packaging technologies (e.g., flip chip, ball grid array, wafer-level chip packaging, wide fan-out packaging, and embedded packaging).

[0176] The advantages and benefits of multilevel power converters enable their use in a wide range of applications. For example, applications of multilevel power converters include portable and mobile computing and / or communication products and components (e.g., laptops, ultrabooks, tablets, and phones), displays (e.g., LCDs, LEDs), radio-based devices and systems (e.g., cellular systems, WiFi, Bluetooth, Zigbee, Z-Wave, and GPS-based devices), wired network devices and systems, data centers (e.g., power conversion for battery backup systems and / or for processing systems and / or electronic / optical networking systems), Internet of Things (IoT) devices (e.g., smart switches and lights, security sensors and security cameras), home appliances and electronics (e.g., set-top boxes, battery-powered vacuum cleaners, appliances with built-in radio transceivers such as washing machines, dryers, and refrigerators), AC / DC power converters, all types of electric vehicles (e.g., for drivetrains, control systems, and / or infotainment systems), and other devices and systems that use portable power sources and / or require power conversion.

[0177] The applications of radio systems include wireless RF systems (including base stations, relay stations, and handheld transceivers) using a variety of technologies and protocols. These technologies and protocols include various types of Orthogonal Frequency Division Multiplexing (“OFDM”), Orthogonal Amplitude Modulation (“QAM”), Code Division Multiple Access (“CDMA”), Time Division Multiple Access (“TDMA”), Wideband Code Division Multiple Access (“W-CDMA”), Global System for Mobile Communications (“GSM”), Long Term Evolution (“LTE”), 5G and WiFi (e.g., 802.11a, 802.11b, 802.11g, 802.11ac, 802.11ax) and other radio communication standards and protocols.

[0178] Programmable implementation

[0179] Some or all aspects of the present invention (in particular) Figure 10The multi-level switch state selector 1014 can be implemented by hardware or software, or a combination of both (e.g., a programmable logic array). Unless otherwise stated, the algorithms included as part of this invention are not inherently associated with any particular computer or other device. In particular, various general-purpose computing machines can be used with programs written in accordance with the teachings herein, or specific functions can be performed more conveniently using dedicated computers or dedicated hardware (e.g., integrated circuits). Therefore, embodiments of the invention can be implemented in one or more computer programs (i.e., sets of instructions or code) executing on one or more programmed or programmable computer systems (which may have various architectures, such as distributed, client / server, or grid systems), each system including at least one processor, at least one data storage system (which may include volatile and non-volatile memory and / or storage elements), at least one input device or port, and at least one output device or port. Program instructions or code can be applied to input data to perform the functions described in this disclosure and generate output information. Output information can be applied to one or more output devices in known manners.

[0180] Each such computer program can be implemented in any desired computer language (including machine, assembly, or high-level procedural, logical, or object-oriented programming languages) to communicate with a computer system, and can be implemented in a distributed manner, in which different parts of the computation specified by the software are executed by different computers or processors. In any case, the computer language can be a compiled or interpreted language. Some or all of the computer programs implementing this invention can form one or more modules of a larger program or program system. Some or all of the elements of the computer program can be implemented as data structures stored in a computer-readable medium or other organized data conforming to a data model stored in a data repository.

[0181] Each such computer program may be stored on or downloaded to (e.g., by means of a solid-state memory medium or device, or a magnetic or optical medium) a tangible, non-transitory storage medium or device for a period of time (e.g., the time between refresh cycles of a dynamic memory device such as dynamic RAM, or semi-permanently, or permanently), which may be read by a general-purpose or special-purpose programmable computer or processor to configure and operate the computer or processor when the computer or processor reads the storage medium or device to perform the processes described above. The system of the present invention can also be considered as a non-transitory computer-readable storage medium configured with a computer program, wherein such a storage medium causes a computer or processor to operate in a particular or predefined manner to perform the functions described in this disclosure.

[0182] Manufacturing technology and options

[0183] In various implementations of multilevel power converters, the use of specific types of capacitors can be beneficial, particularly flying capacitors. For example, such capacitors often possess low equivalent series resistance (ESR), low DC bias degradation, high capacitance, and small size. Low ESR is especially important for multilevel power converters that incorporate additional switches and flying capacitors to increase the number of voltage levels. Specific capacitors should be selected after considering specifications such as power level, efficiency, size, etc. Various types of capacitor technologies can be used, including ceramic (including multilayer ceramic capacitors), electrolytic capacitors, film capacitors (including power film capacitors), and IC-based capacitors. The capacitor dielectric can vary depending on the specific application requirements and can include paraelectric dielectrics such as silicon dioxide (SiO2), hafnium dioxide (HFO2), or aluminum oxide (Al2O3). Furthermore, multilevel power converter designs can advantageously utilize inherent parasitic capacitances (e.g., inherent to power FETs) in combination with or in place of the designed capacitors to reduce circuit size and / or improve circuit performance. The selection of capacitors for multilevel power converters can also take into account factors such as capacitor component variations, reduced effective capacitance with DC bias, and the temperature coefficient of ceramic capacitors (minimum and maximum operating temperature limits, and capacitance variation with temperature).

[0184] Similarly, in various implementations of multilevel power converters, the use of specific types of inductors can be advantageous. For example, inductors with low DC equivalent resistance, high inductance, and small size are often useful.

[0185] The controller used to control the startup and operation of a multilevel power converter can be implemented as a microprocessor, microcontroller, digital signal processor (DSP), register-transfer-level (RTL) circuit system, and / or combinational logic.

[0186] As used in this disclosure, the term "MOSFET" includes any field-effect transistor (FET) having an insulated gate with conductivity that determines its voltage, and includes an insulated gate having a metallic or metalloid, insulator, and / or semiconductor structure. The terms "metal" or "metalloid" include at least one conductive material (e.g., aluminum, copper, or other metals, or highly doped polycrystalline silicon, graphene, or other electrical conductors), "insulator" includes at least one insulating material (e.g., silicon oxide or other dielectric material), and "semiconductor" includes at least one semiconductor material.

[0187] As used in this disclosure, the term "radio frequency" (RF) refers to an oscillation rate in the range of about 3 kHz to about 300 GHz. The term also includes frequencies used in wireless communication systems. RF frequencies can be the frequencies of electromagnetic waves or the frequencies of alternating voltage or current in a circuit.

[0188] Regarding the accompanying drawings referenced in this disclosure, the dimensions of the individual elements are not drawn to scale; for clarity or emphasis, some dimensions have been significantly enlarged vertically and / or horizontally. Furthermore, references to orientation and direction (e.g., "at the top of," "at the bottom of," "above," "below," "horizontal," "vertical," "horizontal," etc.) are relative to the example drawings and are not necessarily absolute orientations or directions.

[0189] Various embodiments of the present invention can be implemented to meet a wide range of specifications. Unless otherwise stated above, the selection of suitable component values ​​is a matter of design choice. Various embodiments of the present invention can be implemented using any suitable integrated circuit (IC) technology (including, but not limited to, MOSFET structures) or in hybrid or discrete circuit form. Integrated circuit embodiments can be fabricated using any suitable substrate and process (including, but not limited to, standard bulk silicon, high resistivity bulk CMOS, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS)). Unless otherwise stated above, embodiments of the present invention can be implemented using other transistor technologies such as bipolar, BiCMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAs pHEMT, and MESFET technologies. However, embodiments of the present invention are particularly useful when fabricated using SOI or SOS-based processes or when fabricated using processes with similar characteristics. Fabrication in CMOS using SOI or SOS processes enables circuits to have low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high-frequency operation (i.e., radio frequency up to and exceeding 300 GHz). Since parasitic capacitances can usually be kept low (or minimized, and kept consistent across all cells, thus allowing them to be compensated) through careful design, monolithic IC implementations are particularly useful.

[0190] Depending on specific specifications and / or implementation technologies (e.g., NMOS, PMOS, or CMOS, and enhancement-mode or depletion-mode transistor devices), voltage levels and / or the polarity of voltage and / or logic signals can be reversed. The voltage, current, and power handling capabilities of components can be adjusted as needed, for example, by adjusting device size, "stacking" components (especially FETs) in series to withstand higher voltages, and / or using multiple components in parallel to handle higher currents. Additional circuit components can be added to enhance the capabilities of the disclosed circuit and / or to provide additional functionality without significantly altering its functionality.

[0191] The circuits and devices according to the invention can be used alone or in combination with other components, circuits, and devices. Embodiments of the invention can be manufactured as integrated circuits (ICs), which can be encapsulated in IC packages and / or modules for ease of handling, manufacturing, and / or performance improvement. In particular, IC embodiments of the invention are typically used in modules in which one or more such ICs are combined with other circuit blocks (e.g., filters, amplifiers, passive components, and possible additional ICs) into a single package. Then, typically, the ICs and / or modules are often combined with other components on a printed circuit board to form part of an end product such as a cellular phone, laptop computer, or tablet computer, or to form a higher-level module that can be used in a wide variety of products such as vehicles, test equipment, medical devices, etc. Through various configurations of modules and components, such ICs typically implement a communication mode, typically wireless communication.

[0192] Several embodiments of this disclosure have been described. It should be understood that various modifications can be made without departing from the spirit and scope of this disclosure. For example, some steps in the above-described steps may be order-independent and therefore may be performed in a different order than that described. Furthermore, some steps in the above-described steps may be optional. The various activities described with respect to the methods identified above may be performed in a repetitive, serial, and / or parallel manner.

[0193] It should be understood that the foregoing description is intended to illustrate, not limit, the scope of this disclosure, which is defined by the scope of the appended claims, and other embodiments are also within the scope of the claims. In particular, the scope of this disclosure includes any and all possible combinations of one or more of the processes, machines, manufactures, or compositions of matter set forth in the appended claims. (Note that the bracket markings used for claim elements are for the convenience of referencing such elements and do not in themselves indicate a specific desired order or enumeration of elements; furthermore, such markings may be repeated in dependent claims as references to additional elements and are not considered as initiating a conflicting sequence of markings.)

Claims

1. A system comprising: A controller configured to transition a multilevel converter circuit from a first state corresponding to a first voltage level to a second state corresponding to a second voltage level, wherein the controller for the transition is configured to: The switch of the multilevel converter circuit is controlled to open to discharge the parasitic capacitance at the node through the inductor, or the switch of the multilevel converter circuit is controlled to close to charge the node through the inductor, wherein the switches are arranged in pairs and include a first pair and a second pair, wherein the first pair includes the innermost switch, and the second pair includes one switch on each side of the innermost switch, and wherein the node is located between the innermost switches of the first pair or between the switch pairs; and The switches are controlled to close sequentially to discharge the node through the inductor, or to open sequentially to charge the node through the inductor, wherein the closing or opening of the switches begins with the first pair, followed by the second pair.

2. The system according to claim 1, wherein, The switches of the multilevel converter circuit are arranged in series.

3. The system according to claim 1, wherein, In order to control the switch pair, the controller is also configured to: Determine the polarity of the current flowing through the inductor in the first state; and Depending on the change in current polarity from the first state to the second state, the switches of the multilevel converter circuit are closed or opened at approximately the same time, or the switches are closed or opened sequentially.

4. The system according to claim 1, wherein, The switch pair also includes a third switch pair, with one switch on each side of the switches in the second pair.

5. The system according to claim 4, wherein, In order to switch the multilevel converter circuit, the controller is also configured to: close the third switch pair to discharge the node, or open the third switch pair to charge the node, after closing or opening the second pair of switches.

6. The system according to claim 1, wherein, One of the switch pairs has a time delay between closing the first and second switches in the pair.

7. The system according to claim 6, wherein, The time delay is either a fixed time delay or a variable time delay.

8. The system according to claim 6, wherein, The time delay is different for this pair and the other pair.

9. The system according to claim 6, wherein, The time delay depends on the current flowing through the inductor.

10. The system according to claim 6, wherein, The time delay depends on a comparator configured to measure the voltage at the node and the voltage level corresponding to the second state.

11. The system according to claim 6, wherein, The time delay depends on an interlock circuit coupled to the first and second switches of the pair and including a gate driver and a gate. The gate driver is configured to receive a PWM signal and generate an output, wherein the output causes the first switch of the pair to close or open, and the output is interlocked with the node. The gate is configured to receive the PWM signal and the output of the gate driver, and to generate an output that closes the second switch of the pair.

12. The system according to claim 6, wherein, The time delay depends on a feedthrough circuit coupled to the pair of switches and includes a first rising edge delay circuit and a first gate driver coupled to the first switch in the pair, and a second rising edge circuit and a second gate driver coupled to the second switch in the pair, wherein the first rising edge circuit and the second rising edge circuit receive a PWM signal and delay the PWM signal on the rising edge, and wherein the delay causes a time delay between the closing or opening of the first switch and the second switch.

13. The system according to claim 6, wherein, The time delay depends on the interlocking circuit and feedthrough circuit coupled to the first and second switches of the pair.

14. A multilevel converter circuit, comprising: Multiple switches arranged in pairs, The first pair comprises two innermost switches, and the second pair comprises two switches on either side of the two innermost switches. In this pair, the first switch is connected in series with one of the innermost switches in the first pair, and the second switch in the second pair is connected in series with another switch in the innermost switch. During the transition from a first state to a second state in the multilevel converter circuit, one or more switches in a switch pair sequentially open or close, starting with the first pair and followed by the second pair; and An inductor is arranged between first switch pairs, wherein the opening or closing of one or more switches in the switch pairs charges or discharges the parasitic capacitance at the nodes between or between the first switch pairs through the inductor.

15. The multilevel converter circuit according to claim 14, wherein, Each switch pair has a time delay independent of other switch pairs, wherein the time delay is between opening or closing the first and second switches of each pair.

16. The multilevel converter circuit according to claim 14, wherein, One or more switches in the switch pair are sequentially opened or closed to reduce power loss during the transition between a first state associated with a first voltage and a second state associated with a second voltage.

17. The multilevel converter circuit according to claim 14, further comprising: A third switch pair on each side of the first and second switches of the second pair, wherein the first switch of the third pair is coupled in series with the first switch of the second pair, and the second switch of the third pair is coupled in series with the second switch of the second pair, wherein the third switch pair is sequentially opened or closed after the second switch pair.

18. The multilevel converter circuit according to claim 14, wherein, The multiple switches are MOSFETs.

19. A method comprising: Generate a signal for switching a multilevel converter circuit from a first state associated with a first voltage to a second state associated with a second voltage, wherein the multilevel converter circuit includes a plurality of switches arranged in non-overlapping pairs; and In response to the signal, the multilevel converter circuit is switched from the first state to the second state, wherein the switching further includes: Close or open all switches in the multilevel converter circuit; and Sequentially disconnecting closed switches in the pair or sequentially closing open switches in the pair, starting from the innermost pair and ending with the outermost pair, to charge or discharge parasitic capacitance at the node via an inductor, wherein the node is located between the innermost pairs or between the non-overlapping pairs.

20. The method according to claim 19, wherein, The non-overlapping pairs include the innermost switch pair and the subsequent switch pair having a switch on either side of the innermost switch pair and immediately adjacent to the previous switch pair.

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