Continuous time linear equalizer circuit based on attenuator structure

Abstract

The invention relates to a continuous time linear equalizer circuit based on an attenuator structure, and the circuit comprises three stages of circuits, the first stage of circuit is composed of an attenuator circuit, and the multi-stage adjustment of the low-frequency signal attenuation capability of the attenuator circuit is realized through different control code signals, so as to meet the circuit gain requirements under various conditions; the second-stage circuit is composed of a continuous time linear equalizer adopting a negative capacitance structure and serves as a high-frequency gain compensation stage; the third-stage circuit is composed of two stages of variable gain amplifiers, and each variable gain amplifier is a differential operational amplifier and has a certain capacity of assisting in improving gain. The circuit is built in a mode of combining MOSFET devices, the high-frequency and low-frequency gain difference of the whole circuit is improved by attenuating a signal low-frequency part, better balance compensation capacity is provided compared with a traditional continuous time linear equalizer circuit, and the balance compensation capacity of the circuit can be improved by adjusting a variable resistor and a capacitor network in the circuit. And the equalization requirements of the circuit under various conditions are met.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design technology, and in particular to a continuous-time linear equalizer circuit based on an attenuator structure. Background Technology

[0002] With the advent of the 5G era, data transmission rates are accelerating. High-speed serial interfaces (SerDes), as essential components for high-speed data exchange between chips, backplanes, and cabinets, have a crucial impact on the rapid development of data transmission. The continuous-time linear equalizer (RTE), as the core module of the receiver analog front-end in the SerDes system, determines the overall data rate of the entire SerDes transceiver system based on its channel equalization compensation capability. Due to the ever-increasing data transmission rates, traditional RTE structures are no longer sufficient to meet equalization requirements. Therefore, various improved structures of RTEs have been proposed to address the shortcomings of insufficient compensation capability in traditional RTEs. Summary of the Invention

[0003] To address the problems existing in the above-mentioned traditional methods, this invention proposes a continuous-time linear equalizer circuit based on an attenuator structure.

[0004] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions: On the one hand, a continuous-time linear equalizer circuit based on an attenuator structure is provided, which includes a first-stage circuit, a second-stage circuit, and a third-stage circuit cascaded in sequence.

[0005] The first-stage circuit consists of an attenuator circuit, which is used to receive the differential input signal and adjust the dynamic range of the differential input signal through a control signal.

[0006] The second-stage circuit consists of a continuous-time linear equalizer, which receives the output signal from the first-stage circuit and performs gain compensation on the high-frequency components of the first-stage circuit's output signal.

[0007] The third-stage circuit consists of two variable-gain amplifiers. It receives the output signal from the second-stage circuit and calibrates the amplitude of the second-stage circuit's output signal to the target range through its own gain control. At the same time, it enhances the driving capability using the two-stage structure and finally outputs a differential signal that meets the requirements of the subsequent stage.

[0008] One of the above technical solutions has the following advantages and beneficial effects: The aforementioned continuous-time linear equalizer circuit based on an attenuator structure comprises three stages. The first stage consists of an attenuator circuit, which, through different control code signals, allows for multi-level adjustment of the attenuation capability of the low-frequency signal to meet circuit gain requirements under various conditions. The second stage consists of a continuous-time linear equalizer employing a negative capacitor structure, serving as a high-frequency gain compensation stage. The third stage consists of two stages of variable gain amplifiers, each a differential operational amplifier, providing some auxiliary gain enhancement capability. This circuit is constructed using a combination of MOSFET devices. By attenuating the low-frequency portion of the signal, it improves the overall high-low frequency gain difference of the circuit, providing better equalization compensation capabilities compared to traditional continuous-time linear equalizer circuits. Furthermore, by adjusting the variable resistor and capacitor network within the circuit, it can meet the equalization requirements of the circuit under various conditions. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a schematic diagram of a continuous-time linear equalizer circuit based on an attenuator structure in one embodiment; Figure 2 This is a schematic diagram of the first-stage circuit in one embodiment; Figure 3 This is a schematic diagram of the variable capacitor network circuit in the first stage circuit of one embodiment; Figure 4 This is a schematic diagram of the second-stage circuit in one embodiment; Figure 5 In one embodiment, the variable resistor network R is used in the second-stage and third-stage circuits. S Circuit schematic; Figure 6 In one embodiment, the variable capacitor network C in the second-stage circuit S Circuit schematic; Figure 7 This is a schematic diagram of the third-stage circuit in one embodiment. Detailed Implementation

[0011] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0012] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0013] It should be noted that, in this document, the reference to "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The presentation of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will understand that the embodiments described herein can be combined with other embodiments. The term "and / or" as used herein refers to any combination of one or more of the associated listed items, and all possible combinations, including such combinations.

[0014] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0015] In one embodiment, such as Figure 1 As shown, a continuous-time linear equalizer circuit based on an attenuator structure is provided. The circuit includes a first-stage circuit 10, a second-stage circuit 20, and a third-stage circuit 30 cascaded in sequence.

[0016] The first-stage circuit 10 consists of an attenuator circuit, which is used to receive differential input signals and adjust the dynamic range of differential input signals through control signals.

[0017] Specifically, the attenuator circuit contains an adjustable resistor-capacitor network. Through different control code signals, the low-frequency signal attenuation capability of the attenuator circuit can be adjusted in multiple stages to meet circuit gain requirements under various conditions. The schematic diagram of the first-stage circuit is shown below. Figure 2 As shown.

[0018] The second-stage circuit 20 consists of a continuous-time linear equalizer, which is used to receive the output signal of the first-stage circuit and perform gain compensation on the high-frequency components of the output signal of the first-stage circuit.

[0019] Specifically, it consists of a continuous-time linear equalizer with a negative capacitor structure. The continuous-time linear equalizer circuit in the second-stage circuit 20 is the main high-frequency gain compensation stage.

[0020] The third-stage circuit 30 consists of two variable-gain amplifiers. It receives the output signal from the second-stage circuit and calibrates the amplitude of the output signal to the target range through its own gain control. At the same time, it enhances the driving capability by utilizing the two-stage structure and finally outputs a differential signal that meets the requirements of the subsequent stage.

[0021] Specifically, the third-stage circuit 30 consists of two stages of variable gain amplifiers. The variable gain amplifier is a differential operational amplifier, which has a certain ability to help improve the gain.

[0022] The basic device used in traditional continuous-time linear equalizer circuits is a metal-oxide-semiconductor field-effect transistor (MOSFET). The continuous-time linear equalizer circuit with a negative capacitor structure proposed in this example is also based on the MOSFET device in the traditional continuous-time linear equalizer circuit. However, a first-stage attenuator circuit and a third-stage variable gain amplifier circuit are added to the traditional circuit.

[0023] The aforementioned continuous-time linear equalizer circuit based on an attenuator structure comprises three stages. The first stage consists of an attenuator circuit, which, through different control code signals, allows for multi-level adjustment of the attenuation capability of the low-frequency signal to meet circuit gain requirements under various conditions. The second stage consists of a continuous-time linear equalizer employing a negative capacitor structure, serving as a high-frequency gain compensation stage. The third stage consists of two stages of variable gain amplifiers, each a differential operational amplifier, providing some auxiliary gain enhancement capability. This circuit is constructed using a combination of MOSFET devices. By attenuating the low-frequency portion of the signal, it improves the overall high-low frequency gain difference of the circuit, providing better equalization compensation capabilities compared to traditional continuous-time linear equalizer circuits. Furthermore, by adjusting the variable resistor and capacitor network within the circuit, it can meet the equalization requirements of the circuit under various conditions.

[0024] In one embodiment, the first-stage circuit 10 includes two capacitors and two variable capacitor networks.

[0025] The positive terminal Vim of the first capacitor C1 receives the positive signal of the differential input signal, and the negative terminal of the first capacitor C1 is connected to the positive output terminal ctle_m of the first stage circuit. The positive terminal Vip of the second capacitor C2 receives the negative signal of the differential input signal, and the negative terminal of the second capacitor C2 is connected to the negative output terminal ctle_p of the first stage circuit. The first variable capacitor network C V1 and the second variable capacitor network C V2 The positive terminals of both variable capacitor networks are connected to the positive output terminal ctle_m of the first stage circuit; the negative terminals of both the first and second variable capacitor networks are connected to the negative output terminal ctle_p of the first stage circuit.

[0026] In one embodiment, the schematic diagram of the variable capacitor network circuit in the first-stage attenuator is as follows: Figure 3 As shown, the variable capacitor network includes three differential attenuation type variable capacitor tuning branches and one RC tuning matching branch.

[0027] The inputs of the three differential attenuation type variable capacitor tuning branches and the RC tuning matching branch are all connected to the positive output of the first stage circuit; the outputs of the three differential attenuation type variable capacitor tuning branches and the RC tuning matching branch are all connected to the negative output of the first stage circuit.

[0028] Each differential attenuation type variable capacitor tuning branch includes two PMOS transistors, two resistors, and two capacitors.

[0029] In the first differential attenuation type variable capacitor tuning branch: the first PMOS transistor M P1 The source of the transistor serves as the input of the differential attenuation type variable capacitor tuning branch and is connected to the positive output terminal ctle_m of the first stage circuit; the first PMOS transistor M P1 The gate of the second PMOS transistor M P2 The gates of all are att_lvl <2> Node connection, first PMOS transistor M P1 The drain of the first PMOS transistor is connected to the positive terminal of the first resistor R1 and the positive terminal of the fourth capacitor C4. The negative terminal of the first resistor R1 is connected to the positive terminal of the third capacitor C3. The negative terminal of the third capacitor C3 is connected to the positive terminal of the second resistor R2. The negative terminals of the second resistor R2 and the fourth capacitor C4 are both connected to the second PMOS transistor M. P2 The drain connection; the second PMOS transistor M P2 The source of the circuit is used as the output terminal of the differential attenuation type variable capacitor tuning branch and is connected to the negative output terminal ctle_p of the first stage circuit.

[0030] The RC tuning matching branch includes resistor R7, capacitor C9, and resistor R8. One end of resistor R7 is connected to the positive output terminal ctle_m of the first stage circuit, and the other end of resistor R7 is connected to the positive terminal of capacitor C9. The negative terminal of capacitor C9 is connected to one end of resistor R8, and the other end of resistor R8 is connected to the negative output terminal ctle_p of the first stage circuit.

[0031] like Figure 3 As shown, in the second differential attenuation type variable capacitor tuning branch: the third PMOS transistor M P3 The source of the transistor serves as the input of the differential attenuation type variable capacitor tuning branch and is connected to the positive output terminal ctle_m of the first stage circuit; the third PMOS transistor M P3 The gate of the fourth PMOS transistor M P4 The gates of all are att_lvl <1> Node connection, third PMOS transistor M P3The drain of the transistor is connected to the positive terminal of the third resistor R3 and the positive terminal of the sixth capacitor C6. The negative terminal of the third resistor R3 is connected to the positive terminal of the fifth capacitor C5. The negative terminal of the fifth capacitor C5 is connected to the positive terminal of the fourth resistor R4. The negative terminals of the fourth resistor R4 and the sixth capacitor C6 are both connected to the fourth PMOS transistor M. P4 The drain connection; the fourth PMOS transistor M P4 The source of the circuit is used as the output terminal of the differential attenuation type variable capacitor tuning branch and is connected to the negative output terminal ctle_p of the first stage circuit.

[0032] In the third differential attenuation type variable capacitor tuning branch: the fifth PMOS transistor M P5 The source of the transistor serves as the input of the differential attenuation type variable capacitor tuning branch and is connected to the positive output terminal ctle_m of the first stage circuit; the fifth PMOS transistor M P5 The gate of the sixth PMOS transistor M P6 The gates of all are att_lvl <0> Node connection, fifth PMOS transistor M P5 The drain of the transistor is connected to the positive terminal of the fifth resistor R5 and the positive terminal of the eighth capacitor C8. The negative terminal of the fifth resistor R5 is connected to the positive terminal of the seventh capacitor C7. The negative terminal of the seventh capacitor C7 is connected to the positive terminal of the sixth resistor R6. The negative terminals of the sixth resistor R6 and the eighth capacitor C8 are both connected to the sixth PMOS transistor M. P6 The drain connection; the sixth PMOS transistor M P6 The source of the circuit is used as the output terminal of the differential attenuation type variable capacitor tuning branch and is connected to the negative output terminal ctle_p of the first stage circuit.

[0033] In one embodiment, the second-stage circuit includes: a seventh PMOS transistor M P7 The eighth PMOS transistor M P8 The first NMOS transistor M N1 The second NMOS transistor M N2 The third NMOS transistor M N3 The fourth NMOS transistor M N4 The fifth NMOS transistor M N5 The sixth NMOS transistor M N6 The seventh NMOS transistor M N7 The eighth NMOS transistor M N8 The ninth resistor R9, the tenth resistor R 10 The eleventh resistor R 11 The twelfth resistor R 12 The tenth capacitor C 10 The eleventh capacitor C 11The twelfth capacitor C 12 A variable resistor network R s and a variable capacitor network C s .

[0034] M P7 and M P8 The source, R 10 To R 11 The positive terminals of M are all connected to the power supply VDD. P7 The drain of R9 is connected to the positive terminal of R9, and R9 and R 10 negative end, M N1 and M N5 Drain, C 10 The positive terminals of M are all connected to the positive output terminal vga_m of the second-stage circuit. P8 Drain and R 12 The positive terminal is connected, R 11 and R 12 negative end, M N2 and M N6 Drain, C 11 The positive terminals of M are all connected to the negative output terminal vga_p of the second-stage circuit; P7 and M P8 The gate is connected to Rclt; M N1 The source of M is connected to the positive output terminal ctle_m of the first-stage circuit. N5 The source is connected to the negative output terminal ctle_p of the first-stage circuit; M N1 The gate of M is connected to the negative output terminal ctle_p of the first-stage circuit. N1 The source and C S positive end, R S The positive end and M N3 The drain connection, C S The negative end, R S The negative end and M N4 The drains are all with M N2 The source connection, M N3 and M N4 The gate of M is connected to the power supply Vb. N7 and M N8 The gate is connected to the power supply Vbc, M N3 M N4 M N7 M N8 The source, C 10 and C 11 The negative terminals are all connected to ground (GND), M N5 The gate and M N6 The drain connection, M N6 The gate and M N5The drain connection, M N5 The source and C 12 positive end and M N7 The drain connection, M N6 The source and C 12 The negative end and M N8 The drain connection.

[0035] The schematic diagram of the second-stage circuit is as follows: Figure 4 As shown.

[0036] In one embodiment, the variable resistance network R S Includes six NMOS transistors M N9 To M N14 Seven resistors R 13 To R 19 Variable resistor network R s The schematic diagram is as follows Figure 5 As shown.

[0037] M N9 M N11 M N13 The source and R 13 The positive terminal is connected, M N10 M N12 M N14 Drain and R 13 The negative end is connected.

[0038] M N9 The drain is through R 14 With M N10 The source connection, M N9 and M N10 The gates of all are connected to the variable resistor control signal input node Rct. <0> connect.

[0039] M N11 Drain and R 15 The positive terminal is connected, R 15 The negative end and R 16 The positive terminal is connected, R 16 The negative end and M N12 The source connection, M N11 and M N12 The gates of all are connected to the variable resistor control signal input node Rct. <1> connect; M N13 Drain and R 17 The positive terminal is connected, R 17 The negative end and R 18 The positive terminal is connected, R 18 The negative end and R 19 The positive terminal is connected, R 19 The negative end and M N14 The source connection, MN13 and M N14 The gates of all are connected to the variable resistor control signal input node Rct. <2> connect.

[0040] R 13 positive end, M N9 M N11 and M N13 The source poles are connected to a single point, denoted as R. s The positive terminator Rs_p. R 13 negative end, M N10 M N12 and M N14 The drain of the electrode is connected to a single point, denoted as R. s The negative end Rs_n.

[0041] In one embodiment, the variable capacitor network C s Circuit schematic as follows Figure 6 As shown, the variable capacitor network C S Includes: 6 PMOS transistors M P9 To M P14 .

[0042] M P9 M P11 The gate and M P13 gate connection, M P10 M P12 The gate and M P14 gate connection, M P9 M P10 Both the source and drain are connected to the control signal input node Cct of the variable capacitor. <0> Connection, M P11 M P12 Both the source and drain are connected to the control signal input node Cct of the variable capacitor. <1> Connection, M P13 M P14 The source and drain are connected at a single point.

[0043] M P9 M P11 and M P13 The gate is connected to a single point, denoted as C. s The positive terminal Cs_p.M P10 M P12 and M P14 The gate is connected to a single point, denoted as C. s The negative end Cs_n.

[0044] In one embodiment, such as Figure 7 As shown, the third-stage circuit includes: four NMOS transistors M N15 To M N18 Two resistors R20 and R 21 Two capacitors C 13 and C 14 A variable resistor network R S .

[0045] R 20 and R 21 The positive terminal is connected to the power supply VDD, R 20 negative end, C 13 The positive end and M N15 The drains of both are connected to the positive output terminal V of the third stage circuit. outm Connection; M N15 The gate of M is connected to the positive output terminal vga_m of the second-stage circuit. N16 The gate of M is connected to the negative output terminal vga_p of the second-stage circuit. N15 The source and M N17 The drain of M is connected to the positive terminal of the variable resistor network. N17 The gate and M N18 The gate is connected to the power supply VB, M N17 The source, M N18 The source, C 13 and C 14 The negative terminals of all resistors are connected to ground (GND), and the negative terminal of the variable resistor network is connected to M. N16 The source and M N18 The drain connection, M N16 Drain, R 21 The negative end and C 13 The positive terminals are all connected to the negative output terminal V of the third-stage circuit. outp connect.

[0046] In one embodiment, all PMOS transistors and NMOS transistors are metal-oxide-semiconductor field-effect transistors.

[0047] In a specific embodiment, a schematic diagram of a continuous-time linear equalizer circuit employing a negative capacitor structure is shown below. Figure 1 As shown, the circuit includes eighteen NMOS transistors, the first NMOS transistor M N1 The second NMOS transistor M N2 The third NMOS transistor M N3 The fourth NMOS transistor M N4 The fifth NMOS transistor M N5 The sixth NMOS transistor M N6 The seventh NMOS transistor M N7 The eighth NMOS transistor M N8 The ninth NMOS transistor M N9The tenth NMOS transistor M N10 The eleventh NMOS transistor M N11 The twelfth NMOS transistor M N12 The thirteenth NMOS transistor M N13 The fourteenth NMOS transistor M N14 The fifteenth NMOS transistor M N15 The sixteenth NMOS transistor M N16 The seventeenth NMOS transistor M N17 The eighteenth NMOS transistor M N18 Fourteen PMOS transistors, namely: the first PMOS transistor M P1 The second PMOS transistor M P2 The third PMOS transistor M P3 The fourth PMOS transistor M P4 The fifth PMOS transistor M P5 The sixth PMOS transistor M P6 The seventh PMOS transistor M P7 The eighth PMOS transistor M P8 The ninth PMOS transistor M P9 The tenth PMOS transistor M P10 The eleventh PMOS transistor M P11 The twelfth PMOS transistor M P12 The thirteenth PMOS transistor M P13 The fourteenth PMOS transistor M P14 The twenty-one resistors are: R1, R2, R3, R4, R5, R6, R7, R8, R9, and R10. 10 The eleventh resistor R 11 The twelfth resistor R 12 The thirteenth resistor R 13 The fourteenth resistor R 14 The fifteenth resistor R 15 The sixteenth resistor R 16 The seventeenth resistor R 17 The eighteenth resistor R 18 The nineteenth resistor R 19 The twentieth resistor R 20 The twenty-first resistor R 21Fourteen capacitors, namely: capacitor C1, capacitor C2, capacitor C3, capacitor C4, capacitor C5, capacitor C6, capacitor C7, capacitor C8, capacitor C9, capacitor C1, capacitor C2, capacitor C3, capacitor C4, capacitor C5, capacitor C6, capacitor C7, capacitor C8, capacitor C9, capacitor C1, capacitor C1, capacitor C2, capacitor C3, capacitor C4, capacitor C5, capacitor C6, capacitor C7, capacitor C8, capacitor C9, capacitor C1, capacitor C1, capacitor C1, capacitor C2 ... 10 The eleventh capacitor C 11 The twelfth capacitor C 12 The thirteenth capacitor C 13 The fourteenth capacitor C 14 .

[0048] The positive terminal of the first capacitor C1 is denoted as the input node Vim, and the negative terminal as the output node ctle_m. The positive terminal of the second capacitor C2 is denoted as the input node Vip, and the negative terminal as the output node ctle_p. The first variable capacitor network C... V1 The positive terminal and the second variable capacitor network C V2 The positive terminal is connected to the output node ctle_m, and the negative terminal is connected to the output node ctle_p. The first PMOS transistor M P1 The drain of the first PMOS transistor is connected to the positive terminal of the first resistor R1 and the positive terminal of the fourth capacitor C4. The negative terminal of the first resistor R1 is connected to the positive terminal of the third capacitor C3. The negative terminal of the third capacitor C3 is connected to the positive terminal of the second resistor R2. The negative terminal of the second resistor R2 is connected to the negative terminal of the fourth capacitor C4 and the second PMOS transistor M. P2 The drain connection, the first PMOS transistor M P1 The gate and the second PMOS transistor M P2 The gate connection is denoted as the input node att_lvl. <2> The third PMOS transistor M P3 The drain of the transistor is connected to the positive terminal of the third resistor R3 and the positive terminal of the sixth capacitor C6. The negative terminal of the third resistor R3 is connected to the positive terminal of the fifth capacitor C5. The negative terminal of the fifth capacitor C5 is connected to the positive terminal of the fourth resistor R4. The negative terminal of the fourth resistor R4 is connected to the negative terminal of the sixth capacitor C6 and the fourth PMOS transistor M. P4 The drain connection, the third PMOS transistor M P3 The gate and the fourth PMOS transistor M P4 The gate connection is denoted as the input node att_lvl. <1> The fifth PMOS transistor M P5 The drain of the transistor is connected to the positive terminal of the fifth resistor R5 and the positive terminal of the eighth capacitor C8. The negative terminal of the fifth resistor R5 is connected to the positive terminal of the seventh capacitor C7. The negative terminal of the seventh capacitor C7 is connected to the positive terminal of the sixth resistor R6. The negative terminal of the sixth resistor R6 is connected to the negative terminal of the eighth capacitor C8 and the sixth PMOS transistor M. P6 The drain connection, the fifth PMOS transistor MP5 The gate and the sixth PMOS transistor M P6 The gate connection is denoted as the input node att_lvl. <0> The negative terminal of the seventh resistor R7 is connected to the positive terminal of the ninth capacitor C9, and the negative terminal of the ninth capacitor C9 is connected to the positive terminal of the eighth resistor R8. The first PMOS transistor M... P1 The source stage, the third PMOS transistor M P3 The source stage, the fifth PMOS transistor M P5 The source terminal and the positive terminal of the seventh resistor R7 are connected, and the second PMOS transistor M is connected. P2 The source stage, the fourth PMOS transistor M P4 The source stage, the sixth PMOS transistor M P6 The source terminal and the negative terminal of the eighth resistor R8 are connected, and att_lvl is controlled. <2> ,att_lvl <1> ,att_lvl <0> Different control code values ​​are generated to correspond to the switching of different branches, thereby realizing the performance of the first-stage attenuator circuit and achieving different degrees of attenuation of the low-frequency band of the input signal. The power supply VDD and the seventh PMOS transistor M... P7 The source of the eighth PMOS transistor M P8 The source, the tenth resistor R 10 The positive terminal and the eleventh resistor R 11 The positive terminal is connected to the seventh PMOS transistor M. P7 The drain of the first resistor is connected to the positive terminal of the ninth resistor R9, and the negative terminal of the ninth resistor R9 is connected to the tenth resistor R. 10 The negative terminal and the tenth capacitor C 10 The positive terminal is connected to the eighth PMOS transistor M. P8 The drain and the twelfth resistor R 12 The positive terminal is connected, and the eleventh resistor R 11 The negative terminal and the twelfth resistor R 12 The negative terminal and the eleventh capacitor C 11 The positive terminal is connected, which controls the seventh PMOS transistor M. P7 and the eighth PMOS transistor M P8 The switching on and off of the transistor allows for adjustment of the drain resistance of the input pair. The first NMOS transistor M... N1 The second NMOS transistor M N2 The input pair consists of a variable resistor network R. s and variable capacitor network C s Connected to the source of the input pair transistors, different control code values ​​correspond to the switching of different branches, thereby adjusting the source resistance and capacitance, and thus adjusting the position of the circuit's zeros and poles. The third NMOS transistor below is M. N3and the fourth NMOS transistor M N4 The fifth NMOS transistor, M, acts as a current source. N5 and the sixth NMOS transistor M N6 After cross-coupling, it is connected to the twelfth capacitor C. 12 The parallel connection forms a negative capacitor structure, introducing a zero and a pole into the circuit. This is achieved through the appropriate selection of the twelfth capacitor, C. 12 The capacitance value allows the newly introduced zero to be positioned near the first pole of the traditional continuous-time linear equalizer circuit, thus canceling each other out and increasing the high-frequency gain and bandwidth of the circuit. The second-stage circuit, based on the traditional continuous-time linear equalizer, adds a variable resistor between the input pair and the drain of the transistor, allowing adjustment of the zero and pole positions to meet the equalization requirements under different conditions. Furthermore, by introducing a negative capacitor structure, it achieves higher high-frequency gain and greater bandwidth compared to the traditional continuous-time linear equalizer circuit. The seventh NMOS transistor M under the negative capacitor structure of the second-stage circuit... N7 and the eighth NMOS transistor M N8 This forms the tail current source, which controls the seventh NMOS transistor M. N7 and the eighth NMOS transistor M N8 The gate voltage is used to control the switching on and off of the tail current source, thereby controlling the switching on and off of the negative capacitor structure. When the channel loss is low, the second-stage circuit can achieve a good channel compensation and equalization effect without using the negative capacitor structure. The tail current source of the negative capacitor structure is turned off, and the circuit power consumption will be reduced accordingly. When the channel loss is high, the tail current source switch is turned on, allowing the negative capacitor structure to participate in the operation, improving the high-frequency gain of the circuit and achieving a better channel compensation and equalization effect.

[0049] right Figure 1 Functional analysis of the continuous-time linear equalizer shown shows that when the input nodes Vip, Vim, Vb, and Vbc are all 0V, the first NMOS transistor M... N1 The second NMOS transistor M N2 The third NMOS transistor M N3 The fourth NMOS transistor M N4 The fifth NMOS transistor M N5 The sixth NMOS transistor M N6 The seventh NMOS transistor M N7 The eighth NMOS transistor M N8 The fifteenth NMOS transistor M N15 The sixteenth NMOS transistor M N16 The seventeenth NMOS transistor M N17 The eighteenth NMOS transistor MN18 All are turned off, thus making both output nodes Voutp and Voutm zero. With input nodes Vip, Vim, and Vb normally input and Vbc voltage zero, the first-stage attenuator circuit attenuates the low-frequency portion of the input signal first through resistor-capacitor coupling. The seventh NMOS transistor M... N7 and the eighth NMOS transistor M N8 When the circuit is closed, the negative capacitor structure of the second-stage circuit is not working. At this time, the overall circuit has one zero and two poles. When the input nodes Vip, Vim, Vb, and Vbc are all functioning normally, the seventh NMOS transistor M... N7 and the eighth NMOS transistor M N8 When the circuit is turned on, the negative capacitor structure of the second-stage circuit becomes active, through the fifth NMOS transistor M. N5 The sixth NMOS transistor M N6 The third capacitor C3 introduces a zero and a pole, giving the entire circuit two zeros and three poles. Compared to when the negative capacitor is not involved, a new zero is introduced near the first pole, causing the zero and pole at that point to cancel each other out. The circuit gain can continue to increase under the influence of the first zero, resulting in higher gain and greater bandwidth than a traditional continuous-time linear equalizer circuit. The seventeenth NMOS transistor M... N17 and the eighteenth NMOS transistor M N18 When turned on, the third-stage variable gain amplifier operates normally. The third-stage circuit is a differential op-amp with a certain auxiliary gain capability.

[0050] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0051] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of protection of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and all such modifications and improvements fall within the scope of protection of this application.

Claims

1. A continuous-time linear equalizer circuit based on an attenuator structure, characterized by, The circuit comprises a first-stage circuit, a second-stage circuit and a third-stage circuit connected in sequence; The first-stage circuit is composed of an attenuator circuit, which is configured to receive a differential input signal and adjust a dynamic range of the differential input signal through a control signal; The second-stage circuit is composed of a continuous-time linear equalizer, which is configured to receive an output signal of the first-stage circuit and perform gain compensation on a high-frequency component of the output signal of the first-stage circuit; The third-stage circuit is composed of a two-stage variable gain amplifier, which is configured to receive an output signal of the second-stage circuit, calibrate an amplitude of the output signal of the second-stage circuit to a target range through gain control of the third-stage circuit, and enhance driving capability through a two-stage structure, and finally output a differential signal meeting requirements of a subsequent stage.

2. The continuous-time linear equalizer circuit based on an attenuator structure according to claim 1, characterized in that, The first-stage circuit comprises two capacitors and two variable capacitor networks. A positive terminal of the first capacitor is configured to receive a positive terminal signal of the differential input signal, a negative terminal of the first capacitor is connected to a positive output terminal of the first-stage circuit, a positive terminal of the second capacitor is configured to receive a negative terminal signal of the differential input signal, and a negative terminal of the second capacitor is connected to a negative output terminal of the first-stage circuit. Positive terminals of the first variable capacitor network and the second variable capacitor network are both connected to the positive output terminal of the first-stage circuit, and negative terminals of the first variable capacitor network and the second variable capacitor network are both connected to the negative output terminal of the first-stage circuit.

3. The continuous-time linear equalizer circuit based on an attenuator structure according to claim 2, characterized in that The variable capacitor network comprises three differential attenuation type variable capacitor tuning branches and one resistance-capacitance tuning matching branch. Input terminals of the three differential attenuation type variable capacitor tuning branches and the one resistance-capacitance tuning matching branch are all connected to the positive output terminal of the first-stage circuit. Output terminals of the three differential attenuation type variable capacitor tuning branches and the one resistance-capacitance tuning matching branch are all connected to the negative output terminal of the first-stage circuit. Each differential attenuation type variable capacitor tuning branch comprises two PMOS transistors, two resistors and two capacitors. In the first differential attenuation type variable capacitor tuning branch: a source of the first PMOS transistor is connected to the positive output terminal of the first-stage circuit as an input terminal of the differential attenuation type variable capacitor tuning branch; gates of the first PMOS transistor and the second PMOS transistor are both connected to an att_lvl<2> node; a drain of the first PMOS transistor is connected to a positive terminal of the first resistor and a positive terminal of the fourth capacitor; a negative terminal of the first resistor is connected to a positive terminal of the third capacitor; a negative terminal of the third capacitor and a negative terminal of the fourth capacitor are both connected to a drain of the second PMOS transistor; and a source of the second PMOS transistor is connected to the negative output terminal of the first-stage circuit as an output terminal of the differential attenuation type variable capacitor tuning branch. The resistance-capacitance tuning matching branch comprises a resistor R7, a capacitor C9 and a resistor R8; one end of the resistor R7 is connected to the positive output terminal of the first-stage circuit; the other end of the resistor R7 is connected to a positive terminal of the capacitor C9; a negative terminal of the capacitor C9 is connected to one end of the resistor R8; and the other end of the resistor R8 is connected to the negative output terminal of the first-stage circuit.

4. The continuous-time linear equalizer circuit based on an attenuator structure according to claim 1, characterized by The second stage circuit comprises two PMOS transistors M P7 and M P8 , eight PMOS transistors M N1 to M N8 , four resistors R9 to R 12 , three capacitors C 10 to C 12 , a variable resistor network R S , and a variable capacitor network C S ; M P7 and M P8 , the positive end of R 10 to R 11 are connected with power supply VDD, the drain of M P7 is connected with the positive end of R9, R9 and R 10 , the negative end of M N1 and M N5 , the positive end of C 10 are all connected with the positive output end of the second stage circuit, the drain of M P8 is connected with R 12 , the positive end of R 11 and R 12 , the negative end of M N2 and M N6 , the positive end of C 11 are all connected with the negative output end of the second stage circuit; the gate of M P7 and M P8 is connected with Rclt; the source of M N1 is connected with the positive output end of the first stage circuit, the source of M N5 is connected with the negative output end of the first stage circuit; M N1 The gate of M N1 The source of M S The positive terminal of C S The positive terminal of R N3 The drain of M S The negative terminal of C S The negative terminal of R N4 The drain of M N2 The source of M N3 The gate of M N4 The gate of M N7 The gate of M N8 The gate of M N3 The source of M N4 The source of M N7 The source of M N8 The source of M 10 The negative terminal of C 11 The negative terminal of C N5 The gate of M N6 The drain of M N6 The gate of M N5 The drain of M N5 The source of M 12 The positive terminal of C N7 The drain of M N6 The source of M 12 The negative terminal of C N8 The drain of M 5. The continuous-time linear equalizer circuit based on an attenuator structure according to claim 4, characterized by Variable resistance network R S Comprises six NMOS transistors M N9 To M N14 , seven resistors R 13 To R 19 ; M N9 , M N11 , M N13 , the source of M 13 , and the positive terminal of R N10 , M N12 , M N14 , and the negative terminal of R 13 are connected; M N9 The drain of M 14 is connected with the source of M N10 , and the gate of M N9 and M N10 is connected with the variable resistance control signal input node Rct<0>; M N11 Drain and R 15 The positive terminal is connected, R 15 The negative end and R 16 The positive terminal is connected, R 16 The negative end and M N12 The source connection, M N11 and M N12 The gates of all are connected to the variable resistor control signal input node Rct. <1> connect; M N13 the drain of R 17 the positive terminal of R 17 the negative terminal of R 18 the positive terminal of R 18 the negative terminal of R 19 the positive terminal of R 19 the negative terminal of R N14 the source of M N13 the gate of M N14 the gate of M 6. The continuous-time linear equalizer circuit based on an attenuator structure according to claim 4, characterized by Variable capacitance network C S includes: 6 PMOS transistors M P9 to M P14 ; M P9 The gate of M P11 is connected to the gate of M P13 , the gate of M P10 , the gate of M P12 is connected to the gate of M P14 , the gate of M P9 , the source and drain of M P10 are connected to the control signal input node Cct<0> of the variable capacitance, the source and drain of M P11 , the source and drain of M P12 are connected to the control signal input node Cct<1> of the variable capacitance, the source and drain of M P13 , the source and drain of M P14 are connected to a point.

7. The continuous-time linear equalizer circuit based on an attenuator structure according to claim 1, characterized by The third stage circuit comprises four NMOS transistors M N15 to M N18 , two resistors R 20 and R 21 , two capacitors C 13 and C 14 , and a variable resistor network R S ; R 20 and the positive terminal of R 21 are connected with the power supply VDD, the negative terminal of R 20 , the positive terminal of C 13 and the drain of M N15 are all connected with the positive output terminal of the third stage circuit; the gate of M N15 is connected with the positive output terminal of the second stage circuit, the gate of M N16 is connected with the negative output terminal of the second stage circuit, the source of M N15 and the drain of M N17 are connected with the positive terminal of the variable resistance network, the gate of M N17 and the gate of M N18 are connected with the power supply VB, the source of M N17 , the source of M N18 , the negative terminal of C 13 and C 14 are all connected with the ground GND, the negative terminal of the variable resistance network is connected with the source of M N16 and the drain of M N18 , the drain of M N16 , the negative terminal of R 21 and the positive terminal of C 13 are all connected with the negative output terminal of the third stage circuit.

8. The continuous-time linear equalizer circuit based on an attenuator structure according to any one of claims 2, 3, 4, 5, 6 or 7, characterized by All the PMOS transistors and NMOS transistors are metal-oxide-semiconductor field effect transistors.

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