Clock domain crossing counter device and clock domain crossing method thereof

Abstract

The invention provides a clock domain crossing counter device and a clock domain crossing method thereof, and the device comprises a low n-bit clock domain crossing processing module which processes low n-bit clock domain crossing processing of a counter; the high m-bit clock domain crossing control module is used for generating high m-bit clock domain crossing control logic according to values before and after low n-bit clock domain crossing of the counter; the high m-bit clock domain crossing processing module is used for finishing high m-bit clock domain crossing of the counter based on control logic driving of the high m-bit clock domain crossing control module; and high m-bit data sent by the counter accumulator is input into the first high m-bit register of the module. According to the scheme, a handshake type cross-clock domain is adopted, high logic complexity of a large-bit-width counter is avoided, time sequence performance is improved, register resource consumption is reduced, and the area is optimized.

Description

Technical Field

[0001] This invention relates to the fields of integrated circuit design, counter data control and clock signal processing, and in particular to a cross-clock domain counter device and a cross-clock domain method thereof. Background Technology

[0002] In ASIC (Application-Specific Integrated Circuit) design, a counter is a basic but critical logic structure. It is usually represented in binary or decimal and increments by 1. It is widely used in scenarios such as time base, timing control, state machines, clock division, and data address generation.

[0003] In some application scenarios, it is necessary to transfer the value of a counter from one clock domain to another. For example, a time counter needs to use a common reference. In this case, the time count value generated from a certain reference clock domain needs to be transferred to other clock domains through cross-clock domain logic.

[0004] Counter logic across clock domains is typically implemented based on Gray code conversion. Gray code only changes one bit between adjacent states during accumulation. However, the increment logic of Gray code is difficult to implement, so the increment of the counter is usually implemented in the decimal or binary domain, and then cross-clock domains are achieved through Gray code conversion and inverse conversion.

[0005] In existing technology, the driving clock for all logic is divided into two clock domains: a source clock domain and a destination clock domain. The source clock domain is the original driving clock for the counter logic to operate, while the destination clock domain is the clock at which the counter operates after crossing clock domains. The general conversion process is as follows: 1. Under the control of the counter accumulation logic, the counter register performs accumulation transitions; 2. The output value of the counter register is converted to Gray code in preparation for crossing clock domains; 3. The converted Gray code value is combinational logic and is registered before crossing clock domains; 4. Crossing clock domains is performed using classic two-stage register pausing logic; 5. The Gray code value output by the second-stage register is converted to binary to complete the cross-clock domain operation.

[0006] The principle and algorithm for converting binary to Gray code are as follows: The i-th bit of an n-bit Gray code is obtained by XORing the i-th bit and the (i+1)-th bit of the binary code, with the highest bit (MSB) being G. n-1 Remain unchanged: ;

[0007] In the above formula, G i For the i-th bit of the Gray code, B i It represents the i-th bit of the binary code.

[0008] The principle and algorithm for converting Gray code to binary are as follows: The i-th bit of an n-bit binary code is obtained by XORing each bit from the most significant bit to the i-th bit in the Gray code. The most significant bit (MSB) is G. n-1 Remain unchanged:

[0009] As can be seen from the formula for converting Gray code to binary, the calculation of each binary bit depends on the result of the previous bit (e.g., for a 4-bit counter, B3 → B2 → B1 → B0), resulting in the least significant bit B0 being the critical path. The complexity of its logic implementation and the length of the implementation path are linearly related to the number of bits n in the binary code. The timing of Gray code to binary conversion with high bit numbers has the problem of non-convergence. Summary of the Invention

[0010] In view of this, embodiments of the present invention provide a cross-clock domain counter device, the device comprising: The low n-bit cross-clock domain processing module uses Gray code cross-clock domain processing to process the low n bits of the counter. This module receives the low n-bit data sent from the counter accumulator through the low n-bit register of the counter, and generates the counter combination output low n bits through the low n-bit binary converter of the counter. The high m-bit cross-clock domain control module is used to determine whether a carry to the high m bits has occurred based on the changes in the values ​​of the low n bits of the counter before and after the cross-clock domain. This determines the control logic for the high m bits, which is implemented through a synchronous request (req) signal and a synchronous response (ack) signal. The change is determined as follows: for the value before the low n bits cross the clock domain, it is determined whether it has changed from all 1s to all 0s. If it has, then it is determined that a carry to the high m bits has occurred. For the value after the low n bits cross the clock domain, the values ​​before and after the delay are compared. If the value before the delay is greater than the value after the delay, then it is determined that a carry to the high m bits has occurred. The high m-bit cross-clock domain processing module is used to complete the high m-bit cross-clock domain processing of the counter under the control logic driven by the high m-bit cross-clock domain control module; the high m-bit data sent by the counter accumulator is input into the first high m-bit register of this module; Cross-clock domain refers to crossing a clock domain from the source clock domain to the destination clock domain.

[0011] Preferably, the high m-bit cross-clock domain control module includes a synchronization request req signal unit, a request cross-clock domain synchronization unit, a response cross-clock domain synchronization unit, a synchronization response register unit, and a low n-bit binary delay register; After receiving the synchronization response ack signal from the sender, the synchronization request req unit pulls the synchronization request req signal low; and when the data to be synchronized is placed on the bus, it pulls the synchronization request req signal high. The request cross-clock domain synchronization unit is used to synchronize the synchronization request req signal to the destination clock domain and send it to the synchronization response register unit to ensure that the receiving unit detects the correct synchronization request req signal. The response cross-clock domain synchronization unit is used to synchronize the synchronization response ack signal sent by the synchronization response register unit to the source clock domain and send it to the synchronization request req signal unit to ensure that the receiving unit detects the correct synchronization response ack signal; The synchronization response register unit is used to pull the synchronization response ack signal high when the synchronization request req signal is high and the comparator output is 1, or to pull the synchronization response ack signal low when the synchronization request req signal is low. The inputs of the comparator are the lower n bits of the counter timing output (comparator input 0) and the lower n bits of the counter combination output (comparator input 1). When the lower n bits of the counter combination output are less than the lower n bits of the counter timing output, the comparator outputs 1; otherwise, it outputs 0. The low n-bit binary delay register is used to generate the low n-bit timing output of the counter based on the low n-bit output of the counter combination (i.e., combinational logic); the low n-bit timing output of the counter is the value of the low n-bit output of the counter combination delayed by one clock cycle. It can be understood that the low n-bit output of the counter combination here is the low n-bit of the counter after converting Gray code to binary.

[0012] Preferably, the high m-bit cross-clock domain processing module includes a first high m-bit register, a second high m-bit register, and a selector; The output of the first high m-bit register is sent to input 1 of the selector; The second high m-bit register takes the output of the selector as its input, and its output serves as the high m-bit of the counter timing output, and is simultaneously output to the input terminal 0 of the selector; The selector receives a signal from the high m-bit cross-clock domain control module and samples the high m bits of the counter on the data bus when the synchronization request req signal is pulled high and the comparator output is high.

[0013] Preferably, the synchronization request req signal unit further includes: a bitwise AND gate, a NOT gate, a second AND gate, a second OR gate, and a high m-bit synchronization request register; The bitwise AND gate receives the low n-bit counter value output from the low n-bit register of the counter, and sends the bitwise AND logic operation result to the second OR gate; further, the bitwise AND logic operation results in 1 when all the input bits are 1, which means that the low n-bit counter is about to carry over and the high m-bit counter is about to change.

[0014] The NOT gate receives the synchronization response ack signal from the response cross-clock domain synchronization unit, performs a NOT operation, and outputs it to the second AND gate; The other input to the second AND gate is the output of the high m-bit synchronization request register, and the result of its logical AND operation is used as the other input data of the second OR gate. The output of the second OR gate is sent to the input of the high m-bit synchronization request register; The output data of the high m-bit synchronization request register is the synchronization request req data, which also serves as the input data for requesting cross-clock domain synchronization units.

[0015] Preferably, the synchronization response register unit further includes: The high m-bit synchronization response register, the first OR gate, the first AND gate, the third AND gate, and the comparator; The inputs of the first AND gate are the output data of the comparator and the synchronization request req signal from the cross-clock domain synchronization unit, respectively; its outputs are sent to the input of the first OR gate and the selection terminal of the selector, respectively. The other input of the first OR gate is the output of the third AND gate, and its output is sent to the input of the high m-bit synchronization response register. The input data of the third AND gate are the synchronization response ack signal output from the high m-bit synchronization response register and the synchronization request req signal output from the request cross-clock domain synchronization unit. It should be further explained that the function here is to pull the output of the ack register low when the req signal is pulled low, and otherwise keep the output of the ack register unchanged. The synchronization response ack signal output from the high m-bit synchronization response register is simultaneously sent to the response cross-clock domain synchronization unit.

[0016] Preferably, the response cross-clock domain synchronization unit includes a high m-bit synchronization response level 1 register and a high m-bit synchronization response level 2 register connected in sequence.

[0017] Preferably, the request cross-clock domain synchronization unit includes a high m-bit synchronization request level 1 register and a high m-bit synchronization request level 2 register connected in sequence.

[0018] Preferably, the high m-bit synchronization response level 1 register, the high m-bit synchronization response level 2 register, the high m-bit synchronization request level 1 register, and the high m-bit synchronization request level 2 register are all D flip-flop synchronizers.

[0019] Preferably, the values ​​of n and m satisfy the following conditions: m+n is the total bit width of the counter; and the value of n must ensure that the n-bit counter cannot carry over again after the synchronization response ack signal is pulled low and sent to the source clock domain.

[0020] Preferably, the low n-bit cross-clock domain processing module further includes: a low n-bit Gray code converter connected to the low n-bit register of the counter, and subsequently connected in sequence to the low n-bit Gray code register, the first level register of the low n-bit Gray code of the counter, and the second level register of the low n-bit Gray code of the counter; the output of the second level register of the low n-bit Gray code of the counter is connected to the low n-bit binary converter of the counter.

[0021] On the other hand, the present invention also provides a counter cross-clock domain method, which is applied to the counter device described above, and the method includes: Step 1: In the source clock domain, the sender places the data to be synchronized on the bus and keeps it unchanged while the synchronization request req signal is high; Step 2: When the counter is about to carry from the lower n bits to the higher m bits, the synchronization request req signal is pulled high; Step 3: The high-pulled synchronization request (req) signal is synchronized through the receiver's clock domain to ensure that the receiver can correctly detect the signal; Step 4: When the receiver detects that the synchronization request req signal after synchronization has gone high and the comparator output is 1, it samples the high m bits of the data to be synchronized on the data bus. Step 5: When the synchronization request req signal goes high and the comparator output is 1, the synchronization response ack signal will go high. Step 6: The synchronization response ack signal is synchronized through the sender's clock domain and sent back to the sender's clock domain; Step 7: After the sender detects the high synchronization response ack signal, it pulls the synchronization request req signal low. Step 8: The pulled-down synchronization request (req) signal is synchronously sent to the receiver through the receiver's clock domain; Step 9: After the receiver detects that the synchronization request (req) signal has gone low after synchronization, it pulls the synchronization response (ack) signal low to complete synchronization and prepares for the next transmission.

[0022] Preferably, the selector selects data in the following way: when the lower n bits of the counter combination output are less than the lower n bits of the counter timing output, and the synchronization request req signal output by the cross-clock domain synchronization unit is high, the output of the first high m bit register is selected; otherwise, the output of the second high m bit register is selected. The first high m bit register and the second high m bit register are set in the high m bit cross-clock domain processing module.

[0023] Compared with the prior art, the technical solution of the present invention can efficiently realize the problem of cross-clock domain conversion of the counter, and avoid the potential problem of non-convergence of logic timing in the prior art, improve timing performance, reduce the number of register resources, and optimize the integrated circuit area. Attached Figure Description

[0024] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram illustrating the implementation of a block counter across clock domains according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the handshake-type cross-clock domain process according to an embodiment of the present invention; Figure 3 This is a schematic diagram illustrating the handshake-style cross-clock domain process correspondence in an embodiment of the present invention. Figure 4 This is a schematic diagram of the sender raising the synchronization request (req) signal according to an embodiment of the present invention; Figure 5 This is the implementation logic path for maintaining the synchronization request req signal in this embodiment of the invention; Figure 6 This is a schematic diagram of the data sampling and synchronization response ack signal generation structure according to an embodiment of the present invention; Figure 7 This is a schematic diagram of the control signal transmission path according to an embodiment of the present invention; Figure 8 This is a schematic diagram of the control path for pulling the synchronization request (req) signal low, according to an embodiment of the present invention. Figure 9 This is a schematic diagram of the control path for pulling the synchronization response ack signal low in an embodiment of the present invention. Detailed Implementation

[0026] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0028] Those skilled in the art should understand that the following specific embodiments or implementation methods are a series of optimized configurations listed to further explain the specific content of the invention. These configuration methods can be combined or used in conjunction with each other, unless the invention explicitly states that some or a specific embodiment or implementation method cannot be associated with or used in conjunction with other embodiments or implementation methods. Furthermore, the following specific embodiments or implementation methods are merely optimized configurations and are not intended to limit the scope of protection of the invention.

[0029] The present invention will be further explained below with reference to specific embodiments.

[0030] This solution proposes a block-based counter implementation structure across clock domains. By dividing the count value into two parts, the lower n bits and the higher m bits, only the lower n bits need to be Gray code-based across clock domains, while the higher m bits use a handshake-based cross-clock domain approach. This avoids the high logic complexity of large-bit-width counters. Compared with existing technologies, this solution improves timing performance, reduces register resource consumption, and optimizes area.

[0031] Combination Figure 1 As shown, in this embodiment, a block-based counter across clock domains is used. In the unit register, D is the input, Q is the output, and CLK is the bit-driving clock. The multi-bit counter group contains multiple independent unit registers.

[0032] Combined again Figure 1 As shown, the implementation of this scheme is mainly divided into three parts: low n-bit cross-clock domain processing, high m-bit cross-clock domain control, and high m-bit cross-clock domain processing. Each of these three parts is further divided into a source clock domain part and a destination clock domain part, as follows: 1. Low n bits of the counter cross-clock domain processing section The method for handling the lower n bits of the counter across clock domains is Gray code. The scheme selects only a subset of the lower bits of the counter for clock domain crossing, thereby controlling the complexity of the Gray code to binary conversion logic and avoiding timing risks.

[0033] In the low n-bit cross-clock domain processing section, the source clock domain includes the low n-bit counter register, the low n-bit counter Gray code converter connected to it, and the low n-bit counter Gray code register connected to the low n-bit Gray code converter; the low n-bit counter register receives the input signal from the external counter accumulation logic (i.e., the counter accumulator). The output of the low n-bit counter Gray code register is connected to the first stage register of the low n-bit counter Gray code.

[0034] The destination clock domain includes the first stage register of the lower n bits of the counter's Gray code, whose output is connected to the second stage register of the lower n bits of the counter's Gray code. The output of the second stage register of the Gray code is connected to the lower n bits of the counter's binary converter, which outputs the final lower n bits of the counter value.

[0035] 2. High m-bit cross-clock domain control section of the counter The high m bits of the control logic for crossing the clock domain are generated by using the low n bits of the counter before and after crossing the clock domain, namely the synchronization request req and the synchronization response ack.

[0036] The high m-bit cross-clock domain control section of the counter mainly receives two data from the low n-bit cross-clock domain processing section of the counter: the output data of the low n-bit register of the counter and the output data of the low n-bit binary converter of the counter (the low n-bit counter value output by the final counter combination).

[0037] In this section, in the destination clock domain, the low n-bit binary delay register of the counter receives the final low n-bit counter value as input, and outputs the final low n-bit timing output of the counter. The low n-bit timing output is used as the input data 0 of the comparator and combined with the low n-bit output (as the input data 1 of the comparator). The comparator compares and judges whether the value of input data 1 is less than the value of input data 0. When the value of input data 1 is less than the value of input data 0, the output value is 1; otherwise, the output value is 0. The output of the comparator is sequentially fed into the high m-bit synchronization response register of the counter through the first AND logic and the first OR logic.

[0038] In the destination clock domain, the output of the high m-bit synchronization response register is sent to the high m-bit synchronization response level 1 register in the source clock domain, and its output is sent to the high m-bit synchronization response level 2 register. The output of the high m-bit synchronization response level 2 register is then subjected to a NOT operation and an AND operation (i.e., a second AND operation) with the output data of the high m-bit synchronization request register. The result of the second AND operation is then subjected to an OR operation (i.e., an operation via a second OR operation) with the result of a bitwise AND operation with the output of the low n-bit counter register. The output of the second OR operation is then used as the input of the high m-bit synchronization request register.

[0039] The output of the high m-bit synchronization request register is sent to the high m-bit synchronization request level 1 register in the destination clock domain, and the output of the high m-bit synchronization request level 1 register is sent to the input of the high m-bit synchronization request level 2 register. The output of the high m-bit synchronization request level 2 register is ANDed with the output of the comparator (i.e., first AND logic). At the same time, the output of the high m-bit synchronization request level 2 register is ANDed with the output of the high m-bit synchronization response register (i.e., third AND logic). The result of the third AND logic operation is ORed with the result of the first AND logic operation (i.e., first OR logic). The result of the first OR logic operation is used as the input of the high m-bit synchronization response register.

[0040] Furthermore, the result of the first AND logic operation is synchronously used as the input of the selector in the high m-bit cross-clock domain processing section, that is, the input of the selector's selection terminal.

[0041] 3. High m bits of the counter cross-clock domain processing section This section, driven by the high m-bit cross-clock domain control logic, completes the high m-bit cross-clock domain operation. The counter accumulation logic is input to the first high m-bit register of this section. Figure 1 This is a commonly used accumulation logic in this field and is not within the scope of this solution.

[0042] The output of the first high m-bit register is sent to the selector as the input signal of the selector's input terminal 1; the output of the second high m-bit register is used as the input of the selector, and its output is used as the other input of the selector, namely input terminal 0.

[0043] The second high m-bit register uses the output of the selector as the high m bits of the final counter timing output; the output of the selector is used as the high m bits of the final counter combination output.

[0044] As can be seen from the above structural design of this embodiment, input 1 of the selector is the latest changed value on the source clock domain side; input 0 is the value held before the change.

[0045] After the synchronization request is sent to the destination clock domain, the new value of the high m bits cannot be sampled immediately because the low n bits may not have been synchronized yet. Since the path above is longer than the path of req, it is necessary to wait for the value of the low n bit combination output to be smaller than the value of the timing output. This means that the carry of the low n bits has been synchronized to the destination clock domain. At this time, the latest value of the high m bits should be selected, that is, the data at the input terminal 1 of the selector (i.e., the output of the first high m bit register) is used as the selected data and output; otherwise, the data at its input terminal 0 of the selector (i.e., the output of the second high m bit register) is used as the selected output.

[0046] The following section provides a more detailed explanation of the preferred control logic in this scheme.

[0047] In this embodiment, a handshake-style cross-clock domain scheme is adopted, consisting of two parts: control of the high m bits of the counter across clock domains and processing of the high m bits of the counter across clock domains. A schematic diagram of the handshake-style cross-clock domain scheme is shown below. Figure 2 As shown. The steps are described below: ① In the source clock domain, the sender places the data to be synchronized on the bus and keeps it unchanged during the synchronization process; preferably, this synchronization process is the period when req is high; ② The sender raises the synchronization request req; ③ The pulled-up req signal is synchronized through the receiver's clock domain using a two-stage D flip-flop synchronizer to ensure correct detection by the receiver; ④ After the receiver detects that req has gone high after synchronization, it samples the data content on the data bus. As mentioned in ①, the data on the bus remains unchanged, so reliable sampling can be guaranteed. Here, there are two conditions for sampling (i.e., switching of the selector): that is, the transition of req to a high level is satisfied at the same time, and the output of the comparator is 1.

[0048] ⑤ The receiver pulls the synchronization response ack signal high; ⑥ Synchronize the ack signal back to the sender's clock domain using a two-stage D flip-flop synchronizer to ensure correct detection by the receiver; ⑦ After the sender detects the synchronization response ack, it pulls req low and releases the data bus; ⑧ The pulled-down req signal is synchronized through the receiver's clock domain using a two-stage D flip-flop synchronizer to ensure correct detection by the receiver; ⑨ After the receiver detects that the synchronized req has gone low, it pulls the ack low to prepare for the next transmission.

[0049] The following, combined with Figure 2 , 3 As shown, the detailed implementation process of the scheme described in this paper and the "handshake-style cross-clock domain" procedure is explained. Combined with... Figure 2 The implementation locations of each step in the process are as follows: Figure 3 The corresponding number is shown in the figure.

[0050] ① In the source clock domain, the sender places the data to be synchronized on the bus and keeps it unchanged during the synchronization process; preferably, this synchronization process is the period when req is high; Figure 1 , 3 The first high m-bit register shown only changes when the low n-bit counter carries over, thus naturally satisfying the handshake-style cross-clock domain data retention requirement.

[0051] ② The sender pulls the synchronization request req high, that is, when the counter is about to carry from the low n bits to the high m bits, the synchronization request req signal is pulled high; Combination Figure 1 , 3 As shown in Figure 4, the sender sends a signal to the lower n bits of the counter register, and its output data is sent to the higher m bits of the synchronization request register via a bitwise AND operation. When the higher m bits of the synchronization request register send the request req, the response ack signal is low. Here, the response ack signal is sent by the second-stage synchronization response register of the higher m bits. When the lower n bits of the counter are all 1, that is, the nth bit will generate a carry to the higher m bits in the next cycle, the synchronization request req will go high in the next clock cycle; and at this time, the response ack signal is 0, so that the synchronization request req output by the register is maintained.

[0052] ③ The high-pulled synchronization request (req) signal is synchronized through the clock domain of the receiver (i.e., the destination clock domain), using a two-stage D flip-flop synchronizer to ensure correct detection by the receiver; combined with Figure 5 As shown, the gray path is the implementation path for holding the synchronization request req signal. In this embodiment, the two-stage D flip-flop synchronizer is the high m-bit synchronization request level 1 register and the high m-bit synchronization request level 2 register.

[0053] This step further explains how to ensure correct detection by the receiver: the `req` signal needs to be cleared by the `ack` signal (i.e., set the `req` signal to 0), and the `ack` signal needs to wait for the `req` signal to go high (i.e., set the `req` signal to 1) before it can become 1; therefore, the `req` signal is maintained during the back-and-forth process, and it needs to wait for the `req` signal to be received before generating the `ack` signal and synchronizing it to the point where the `req` signal was generated. For example... Figure 5 In this configuration, when the req signal output is 1, the input value below the AND gate is 1; at this time, the ack signal is 0, and after passing through the NOT gate, it becomes 1; both inputs of the AND gate are 1, so its output value is 1; after passing through the OR gate, the output is 1; register D is 1, thus maintaining the hold state. Only when the ack signal becomes 0 can this hold state be broken. This ensures that the receiver can correctly detect the req signal.

[0054] ④ After the receiver detects that the synchronized req becomes high and the comparator outputs 1, it samples the data content on the data bus.

[0055] The implementation logic for sampling bus content and generating ACK is as follows: Figure 6 , 7 As shown. Figure 7As shown in gray path 1, the comparator's input 1 is the lower n bits of the binary-converted count value, and input 0 is the value of the lower n bits of the binary-converted count value delayed by one clock cycle. When no carry occurs, the counter value accumulates, and input 1 is always greater than or equal to input 0. When a carry occurs, input 1 will be less than input 0. In this embodiment, the comparator selects its output value based on the comparison result between input 1 and input 0. When input 1 is less than input 0, the comparator output is 1; otherwise, the output is 0. Therefore, the comparator output is 1 at this time. The comparator output and the value of the synchronization request req signal after AND logic become high. Figure 6 , 7 The selector shown in the diagram selects input 1 at this time, which logically ensures that the selector will only select the data at input 1 as the output when a carry is detected in the destination clock domain. After the carry transition is complete, the comparator output will go low, causing the selector in the diagram to select input 0 as the value of the output Q of the second high m-bit register. The input D of the second high m-bit register also becomes "the high m bits of the counter to be synchronized" when the selector selects the data at input 1. After the selector switches to input 0, the selector output remains unchanged as the output Q of the second high m-bit register, thus achieving sampling of the high m bits of data on the data bus.

[0056] ⑤ The receiver pulls the synchronization response ack signal high.

[0057] like Figure 7 As shown in gray path 2, the comparator's input 1 is the low n-bit counter value after binary conversion, and input 0 is the low n-bit counter value after binary conversion delayed by one clock cycle. When no carry occurs, the counter value accumulates, and input 1 is always greater than or equal to input 0. When a carry occurs, input 1 will be less than input 0, and the comparator output value will be 1. The comparator output and the synchronization request req signal are ANDed together, and the result is high. After being ORed, the output value of the high m-bit synchronization response register is pulled high and becomes 1.

[0058] Combined Figure 7 As shown in gray path 3, after the output of the high m-bit synchronization response register becomes 1 (i.e., pulled high), the output of the second-level high m-bit synchronization request register is ANDed and becomes 1 (because the req signal is 1 at this time). After the OR logic, the D input of the high m-bit synchronization response register is driven to remain high. After the carry transition is completed and the comparator output goes low, the output Q of the high m-bit synchronization response register is still maintained at 1 (i.e., kept high). This achieves the purpose of the receiver pulling the synchronization response ack signal high, thus keeping the ack signal until the ack signal is sampled at the req signal.

[0059] ⑥ Synchronize the ack signal back to the transmitter's clock domain (i.e., the source clock domain) using a two-stage D flip-flop synchronizer to ensure correct detection by the receiver; such as Figure 3 As shown in ⑥.

[0060] ⑦ After the sender detects the synchronization response ack signal, it pulls the synchronization request req signal low. At this point, the data bus can be released. It should be noted that releasing the data bus at this time is not a necessary step in this scheme. The action of releasing the data bus can be inserted based on other external signals, that is, it is not an active release of the data bus.

[0061] Combination Figure 1 , 8 As shown, the logical path of this step is as follows: Figure 8 As shown in the gray path, after the synchronization response ack signal goes high, it becomes 0 after passing through the NOT gate logic, and then becomes 0 after passing through the second AND gate. At this time, the output of the bitwise AND operation of the low n-bit counter value has become 0 (a carry from the low bit to the high bit has already occurred). After passing through the second OR gate operation, its output becomes 0, and then the output Q of the high m-bit synchronization request register is pulled low, that is, the synchronization request req signal is pulled low at this time.

[0062] ⑧ The pull-down synchronization request (req) signal is synchronized through the receiver's clock domain, i.e., using a two-stage D flip-flop synchronizer. Figure 1 , 3 The high m-bit synchronization request level 1 register and the high m-bit synchronization request level 2 register ensure that the receiver detects correctly; such as Figure 3 As shown in ⑧.

[0063] ⑨ After the receiver (i.e., the destination clock domain) detects that the synchronization request (req) signal has gone low after synchronization, it pulls the synchronization response (ack) signal low to prepare for the next transmission, such as... Figure 3 As shown in part ⑨.

[0064] Combination Figure 1 as well as Figure 9 As shown in the gray path, when the synchronization request req signal is pulled low, the output of the second-stage synchronization request register of the high m bits becomes 0. This signal and the synchronization response ack signal become zero after passing through the third AND gate. At this time, the output of the comparator and the output of the second-stage synchronization request register of the high m bits are still 0 after passing through the first AND gate. After passing through the first OR gate for logical calculation, its output is 0. Therefore, the input D of the high m bits synchronization response register becomes 0, thus finally pulling the synchronization response ack signal output by the high m bits synchronization response register low.

[0065] The above completes the method for counters to cross clock domains in this scheme, ensuring synchronization in different clock domains.

[0066] More preferably, in this embodiment, the values ​​of n and m need to satisfy the following conditions: 1. m+n is the total bit width of the counter; 2. The smaller the number of n, the better. However, it is necessary to ensure that the n-bit counter cannot carry over again before the ack is pulled low and transmitted to the sending side (i.e., the source clock domain), that is, before step 9 in this embodiment is completed.

[0067] In another implementation, this solution can also be implemented on a chip, that is, the chip includes the cross-clock domain counter device described in the above embodiments, and can perform the cross-clock domain operation of the counter described in this embodiment when the chip is working.

[0068] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A cross-clock domain counter apparatus, characterized by, The device comprises: A low-n-bit cross-clock domain processing module adopts a Gray code cross-clock domain mode to process the cross-clock domain processing of the low-n-bit of the counter; the module receives the low-n-bit data sent from the counter accumulator through the low-n-bit register of the counter and generates the low-n-bit of the counter combination output through the low-n-bit binary converter of the counter; A high-m-bit cross-clock domain control module is used to determine whether the carry of the high-m-bit occurs according to the change of the value of the low-n-bit of the counter before and after the cross-clock domain, to generate the control logic of the high-m-bit cross-clock domain, and the control logic is realized through the synchronization request req signal and the synchronization response ack signal; the determination mode of the change is that the value of the low-n-bit before the cross-clock domain is determined whether it changes from all 1 to all 0, and the value of the low-n-bit after the cross-clock domain is compared with the size of the delayed value before and after the value; A high-m-bit cross-clock domain processing module is used to complete the cross-clock domain of the high-m-bit of the counter under the control of the control logic of the high-m-bit cross-clock domain control module; the high-m-bit data sent by the counter accumulator is input into the first high-m-bit register of the module; The cross-clock domain is the cross-domain from the source clock domain to the destination clock domain.

2. The apparatus of claim 1, wherein, The high-m-bit cross-clock domain control module comprises a synchronization request req signal unit, a request cross-clock domain synchronization unit, a response cross-clock domain synchronization unit, a synchronization response register unit and a low-n-bit binary delay register; After the synchronization request req unit receives the synchronization response ack signal of the sender, the synchronization request req signal is pulled low; And when the data to be synchronized is placed on the bus, the synchronization request req signal is pulled high; The request cross-clock domain synchronization unit is used to synchronize the synchronization request req signal to the destination clock domain and send it to the synchronization response register unit, to ensure that the correct synchronization request req signal is detected by the receiving unit; The response cross-clock domain synchronization unit is used to synchronize the synchronization response ack signal sent by the synchronization response register unit to the source clock domain and send it to the synchronization request req signal unit, to ensure that the correct synchronization response ack signal is detected by the receiving unit; The synchronization response register unit is used to pull the synchronization response ack signal high based on the pull-up of the synchronization request req signal and the output of the comparator being 1, or pull the synchronization response ack signal low based on the pull-down of the synchronization request req signal; the inputs of the comparator are the low-n-bit of the counter timing output and the low-n-bit of the counter combination output respectively, and when the low-n-bit of the counter combination output is less than the low-n-bit of the counter timing output, the output of the comparator is 1, otherwise, the output is 0; The low-n-bit binary delay register is used to generate the low-n-bit of the counter timing output based on the low-n-bit of the counter combination output; the low-n-bit of the counter timing output is the value after the low-n-bit of the counter combination output is delayed for one clock cycle.

3. The apparatus of claim 2, wherein, The high-m-bit cross-clock domain processing module comprises a first high-m-bit register, a second high-m-bit register and a selector; The output of the first high-m-bit register is sent to the input end 1 of the selector; The second high-m-bit register takes the output of the selector as the input, and outputs the high-m-bit of the counter timing output and simultaneously outputs to the input end 0 of the selector; The selection end of the selector receives a signal from the high m-bit cross-clock domain control module, and samples the high m-bit counter on the data bus when the pull-up of the synchronization request req signal and the high level of the comparator output.

4. The apparatus of claim 2, wherein, The synchronization request req signal unit further comprises a bit-by-bit AND gate, a NOT gate, a second AND gate, a second OR gate and a high m-bit synchronization request register; The bit-by-bit AND gate receives the low n-bit counter value from the output of the low n-bit counter register and sends the bit-by-bit AND operation result to the second OR gate; The NOT gate receives the synchronization response ack signal from the output of the response cross-clock domain synchronization unit, and outputs to the second AND gate after NOT operation; The other input of the second AND gate is the output of the high m-bit synchronization request register, and the logic AND operation result is the other input data of the second OR gate; The output of the second OR gate is sent to the input end of the high m-bit synchronization request register; The output data of the high m-bit synchronization request register is the synchronization request req data, which is also the input data of the request cross-clock domain synchronization unit.

5. The apparatus of claim 2, wherein, The synchronization response register unit further comprises: a high m-bit synchronization response register, a first OR gate, a first AND gate, a third AND gate and a comparator; The inputs of the first AND gate are the output data of the comparator and the synchronization request req signal output by the request cross-clock domain synchronization unit respectively; and the outputs thereof are sent to the inputs of the first OR gate and the selection end of the selector respectively; The other input of the first OR gate is the output of the third AND gate, and the output thereof is sent to the input end of the high m-bit synchronization response register; The input data of the third AND gate are the synchronization response ack signal output by the high m-bit synchronization response register and the synchronization request req signal output by the request cross-clock domain synchronization unit respectively; The synchronization response ack signal output by the high m-bit synchronization response register is also sent to the response cross-clock domain synchronization unit.

6. The apparatus of claim 2, wherein, The response cross-clock domain synchronization unit comprises a high m-bit synchronization response 1st register and a high m-bit synchronization response 2nd register connected in sequence.

7. The apparatus of claim 2, wherein, The request cross-clock domain synchronization unit comprises a high m-bit synchronization request 1st register and a high m-bit synchronization request 2nd register connected in sequence.

8. The apparatus of claim 1, wherein, The values of n and m satisfy the following conditions: m+n is the total bit width of the counter; and the value of n needs to ensure that the n-bit counter cannot count again before the synchronization response ack signal is pulled down and sent to the source clock domain.

9. A method for counter crossing clock domain, characterized in that, The method is applied to the counter device of any one of claims 2-8, and the method comprises: Step 1, in the source clock domain, the sender places the data to be synchronized on the bus and keeps it unchanged during the period when the synchronization request req signal is high; Step 2, when the counter is about to count from low n-bit to high m-bit, the synchronization request req signal is pulled up; Step 3, the pulled-up synchronization request req signal is synchronized through the clock domain of the receiver to ensure that the receiver can correctly detect the signal; Step 4, when the synchronized synchronization request req signal is high and the output of the comparator is 1, the high m-bit of the data to be synchronized on the data bus is sampled; Step 5, when the synchronization request req signal is high and the output of the comparator is 1, the synchronization response ack signal is pulled up; Step 6, the synchronous response ack signal is sent back to the clock domain of the sender through the clock domain synchronization of the sender; Step 7, the sender pulls down the synchronous request req signal after detecting the pulled-up synchronous response ack signal; Step 8, the pulled-down synchronous request req signal is sent to the receiver through the clock domain synchronization of the receiver; Step 9, the receiver pulls down the synchronous response ack signal after detecting the pulled-down synchronous request req signal, and the synchronization is completed, and the next transmission is prepared.

10. The method of claim 9, wherein, The selector selects the data in the following manner: when the low n-bit combined output of the counter is less than the low n-bit timing output of the counter, and the synchronous request req signal output by the request cross-clock domain synchronization unit is high, the output of the first high m-bit register is selected; otherwise, the output of the second high m-bit register is selected; the first high m-bit register and the second high m-bit register are arranged in the high m-bit cross-clock domain processing module.

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