High-efficiency and low-cost branch prediction circuit implementation method

Abstract

The invention relates to the technical field of branch prediction circuits, in particular to an efficient and low-cost branch prediction circuit implementation method and system. Branch target information and a physical Tag value are extracted from an SRAM (Static Random Access Memory) with a multi-bank structure by taking a low-order part of a PC (Personal Computer) program counter as an index, and the Tag bit width is reduced by adopting a Hash compression mode, so that rapid fuzzy matching prediction is realized, and the comparison logic complexity and the storage occupation of the SRAM are remarkably reduced. A multi-bank interleaving storage structure is utilized, physical bank partitions of update writing and prediction reading are judged by accessing coding bits, parallel operation is achieved, the read-write conflict rate is reduced, and the continuity of instruction fetching flow is improved. Meanwhile, a renaming conflict detection and redirection mechanism is introduced in an instruction decoding stage, consistency verification is carried out on predicted and real branch types, and the correctness of instruction fetching is redirected. Under the condition of not reducing the prediction performance, the circuit working frequency is obviously improved, the chip area and power consumption are reduced, the implementation is simple, the cost is low, and the circuit performance can be obviously improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of branch prediction circuit, in particular to a high-efficiency and low-cost branch prediction circuit implementation method and system. BACKGROUND

[0002] In modern high-performance processors, the branch prediction circuit plays a crucial role in overall performance. The traditional branch predictor is usually implemented with a large-capacity branch target buffer (BTB, Branch Target Buffer), which needs to store a large number of branch target addresses and corresponding physical tags (Tag) internally, and match with the program counter (PC) in the instruction fetch stage to determine the hit condition. In the prior art, the Tag matching method with complete physical address is usually used, that is, the Tag value with the same width as PC is stored in the BTB branch prediction area for accurate comparison. Although this can guarantee uniqueness and accuracy, it will cause two problems: first, the storage of complete bit width Tag requires a large amount of SRAM storage resources, resulting in significant increase in chip area and power consumption; second, the wide bit comparison circuit deepens the combinational logic depth, which becomes a timing bottleneck, limiting the running frequency of the circuit and reducing the continuity of the instruction fetch bandwidth.

[0003] In addition, the traditional BTB is mostly implemented with a single bank structure of SRAM (Static Random Access Memory), and the prediction reading and the backend update writing share the same storage channel, which is prone to read-write conflict under high frequency operation. It has to be solved by delay or pause, thereby interrupting the prediction pipeline and affecting the smoothness of instruction flow. On the other hand, when using hash compression to shorten the Tag bit width, address renaming conflicts are likely to occur, that is, multiple different addresses are mapped to the same BTB index and Tag. If there is no redirection instruction fetching mechanism, it will lead to incorrect branch prediction results entering the pipeline, which will destroy the execution correctness. SUMMARY

[0004] The present application overcomes the shortcomings of the prior art and provides a high-efficiency and low-cost branch prediction circuit implementation method and system.

[0005] To achieve the above purpose, the technical solution adopted by the present application is as follows: The present application provides a high-efficiency and low-cost branch prediction circuit implementation method in the first aspect, comprising the following steps: S102: Extract the BTB branch target information and the corresponding physical Tag value from the SRAM static random access memory by the low bit part of the PC program counter, align the PC program counter and the BTB branch target buffer in time sequence, hash compress the current instruction address to be fetched, compare the bit width of the hash compression circuit with the bit width of the physical Tag value, and predict the branch hit instruction to read and jump to the next branch target instruction PC address immediately; S104: Obtain the end low data encoding physical bank storage partition of the PC program counter pointer, obtain the access pointing encoding bit, detect the update write operation of the processor back end in the BTB branch target buffer and the prediction read operation of the branch hit instruction, judge whether the update write operation and the prediction read operation are in the same physical bank storage partition based on the access pointing encoding bit, and perform corresponding write permission and stop operation; S106: Decode the real branch target jump instruction of the current instruction address to be fetched, obtain the first branch instruction type, perform misdecode and rename conflict consistency analysis on the first branch instruction type based on the second branch instruction type of the branch prediction hit instruction, and output the rename conflict detection result; S108: Flush the rename conflict BTB instruction entry and invalidate the conflict content according to the rename conflict detection result, and correct the error and absence of the instruction fetch by performing the check bit calculation on the real branch target jump instruction of the current instruction address to be fetched, so as to initiate a new instruction fetch request action according to the redirected instruction fetch address.

[0006] Preferably, the S102 specifically comprises the following steps: Obtain the current instruction address to be fetched of the PC program counter in the target computer, and obtain the given bit width limit of the target computer; Based on the current instruction address to be fetched, construct an instruction fetch request subitem, and activate the access operation of the SRAM static random access memory and the BTB branch target buffer synchronously when the PC program counter sends the instruction fetch request subitem; During the access operation, a series of low index values are established using the low part of the PC program counter based on the given bit width limit, branch data is read in parallel from a plurality of physical bank storage partitions in the SRAM static random access memory according to the series of low index values, BTB branch target information and corresponding XOR hash compressed physical Tag values of each BTB branch target information are obtained; Obtain the read delay period threshold of the SRAM static random access memory, introduce a register based on the read delay period threshold, and construct the pipeline register step width of the register; Align the PC program counter when the current instruction address to be fetched is sent in time sequence with the access output of the BTB branch target buffer by the read rhythm of the pipeline register step width, process the key value pair of the current instruction address to be fetched in blocks after alignment, construct a hash mixing unit to perform XOR accumulation calculation for mixed compression of each key value address block, and output the hash compression circuit bit width of the current instruction address to be fetched; If the degree of coincidence between the bit width of the hash compression circuit and the bit width of the physical Tag value is greater than a preset degree of coincidence, the BTB branch target information corresponding to the physical Tag value is marked as a branch prediction hit instruction, a branch prediction result is output, and the PC address of the next branch target instruction is read and jumped based on the branch prediction result.

[0007] Preferably, the aligned block processes the key-value pair of the current instruction address to be fetched, constructs an XOR accumulation calculation of the hash mixing unit for mixing and compressing each key-value address block, and outputs the hash compression circuit bit width of the current instruction address to be fetched, specifically including the following steps: An XOR hash algorithm is introduced to construct a hash compression field, the current instruction address to be fetched is segmented into N key-value address blocks based on a given bit width limit, and each key-value address block is loaded into the hash compression field; A hash mixing unit is constructed, and the hash function between a certain key-value address block and another key-value address block is mixed and multiplied in the hash compression field driven by the hash mixing unit, and a Booth shift coding operation of mixed multiplication is performed to generate a mixed hash partial product matrix and a shift weight of each mixed hash partial product; According to the shift weight, align each mixed hash partial product, and perform parallel compression on the radix shift of each partial product column in the mixed hash partial product matrix from the lowest column after alignment, to generate a hash compression tree structure; Through the hash compression tree structure, the new partial product row after parallel compression of each partial product column is extracted and the corresponding hash compression leaf node layout is extracted, and the above parallel compression step is repeated to continue compression processing of the partial product column generated by the new partial product row; If the deviation between the hash compression leaf node layout and the preset hash compression leaf node layout is less than a preset deviation threshold, stop the continuous parallel compression operation, and output the XOR accumulation register product of the mixed and compressed key-value address block; The current hash accumulation value of the current instruction address to be fetched is obtained, the current hash accumulation value is fused with all key-value address blocks based on the XOR accumulation register product, and finally the hash compression circuit bit width of the current instruction address to be fetched is output.

[0008] Preferably, the S104 specifically includes the following steps: The end low bit data of the branch target jump instruction pointed to by the PC program counter pointer is obtained, the different physical bank storage partitions in the BTB branch target buffer are encoded according to the end low bit data, and the access pointing encoding bits of each physical bank storage partition are generated. The processor backend of the target computer detects whether there is a branch prediction hit instruction real jump result in the execution stage, if there is, actual branch target information is obtained, the actual branch target information is updated and written into the BTB branch target buffer at the current cycle timing, and a real-time update pulse signal is generated; A read-aware network based on a burst read access monitoring architecture is deployed in the BTB branch target buffer, the read-aware network is used for sensing and detecting the access of the processor front-end to the branch prediction hit instruction, and a real-time read pulse signal of the BTB branch target buffer at the current cycle timing is obtained; A signal analysis algorithm is introduced to transform and solve the response activation of the real-time update pulse signal and the real-time read pulse signal in different physical bank storage partitions, so as to determine the physical bank storage partition at the update write operation time, which is marked as a first type of physical bank storage partition, and the physical bank storage partition at the predicted read operation time, which is marked as a second type of physical bank storage partition; If the access pointing encoding bits cannot be simultaneously queried in the pointing encoding bits of the first type of physical bank storage partition and the second type of physical bank storage partition, the update write operation and the predicted read operation are allowed to be executed in parallel in the same cycle; If the access pointing encoding bits can be simultaneously queried in the pointing encoding bits of the first type of physical bank storage partition and the second type of physical bank storage partition, the update write operation is immediately stopped, a small-depth FIFO buffer queue is constructed, and the update write operation in conflict is stored in the FIFO buffer queue for delay buffering.

[0009] Preferably, the S106 specifically includes the following steps: A renaming conflict detection circuit is established and arranged in the late-stage pipeline of the processor corresponding to the target computer, and an instruction decoding algorithm is introduced to construct an instruction decoding dictionary conforming to the branch instruction encoding translation; The instruction decoding dictionary is used to perform preliminary decoding processing on the real branch target jump instruction of the current to-be-taken instruction address in the renaming conflict detection circuit, to obtain instruction type information of the real branch target jump instruction, which is defined as a first branch instruction type; In the preliminary decoding process, a decoding reference template is established by gradually decoding the instruction type of the real branch target jump instruction, and the instruction decoding dictionary is used again to decode the branch prediction hit instruction according to the decoding reference template, to obtain instruction type information of the branch prediction hit instruction, which is defined as a second branch instruction type; A decoding hash algorithm is introduced to calculate a decoding hash function that exists between the second branch instruction type and the first branch instruction type, and the decoding hash function is used to determine the decoding misalignment amplitude of the real branch target jump instruction and the branch prediction hit instruction. If the decoding error amplitude is greater than the preset decoding error amplitude, it is indicated that the branch prediction hit instruction has a high distortion rate compared with the real branch target jump instruction, is mispredicted, and the branch prediction hit instruction is calibrated as a rename conflict BTB instruction entry, and a rename conflict detection result is output.

[0010] Preferably, the S108 specifically comprises the following steps: The rename conflict BTB instruction entries in the BTB branch target buffer are extracted through the rename conflict detection result, and are added to a queue to be cleared. At this time, the address sequence chain of the real branch target jump instruction is obtained, the check bits of the bit errors are calculated, and different check bits are placed in the binary power position of the address sequence chain based on the first branch instruction type. The even check method is introduced, the sequence bit binary representation of all power positions is checked and calculated in the even check method according to the decoding error amplitude, the redundancy value of each check bit is obtained, the redundancy value of each check bit is combined with the sequence bit one by one to correct the error or the missing, and the directional compensation encoding character correcting the instruction fetch error of the real branch target jump instruction is generated. The above-mentioned check calculation step is repeated to calculate the branch prediction hit instruction in the BTB branch target buffer, the check bits of the branch prediction hit instruction are obtained, the check bits of the real branch target jump instruction are XORed with the check bits of the branch prediction hit instruction, and the XOR comprehensive value is obtained. At this time, the flush processing is performed on all the rename conflict BTB instruction entries in the queue to be cleared, and the conflict content stored in the BTB branch target buffer is invalidated. After the flush processing and invalidation, the error is corrected using the directional compensation encoding character according to the redundancy position indicated by the XOR comprehensive value, a redirected instruction fetch address is generated, and a new instruction fetch request action is initiated according to the redirected instruction fetch address.

[0011] The second aspect of the present application provides a high-efficiency and low-cost branch prediction circuit implementation system, which comprises a memory, a processor and a communication interface, the memory comprises a high-efficiency and low-cost branch prediction circuit implementation method program, the communication interface is used for data connection communication between the memory and the processor, and the branch prediction circuit implementation method program is executed by the processor to implement the branch prediction circuit implementation method steps.

[0012] The present application solves the technical defects in the background art, and has the beneficial technical effects that: This invention improves the structure and matching mechanism of the BTB branch prediction buffer by employing hash compression storage and fuzzy matching of physical address tags. This significantly reduces the physical tag width and comparison circuit complexity while maintaining high prediction accuracy. Compared to traditional full physical address matching, it effectively reduces SRAM storage resource usage and shortens the logic depth of the comparison path, thereby significantly increasing the upper limit of the circuit's operating frequency. Furthermore, by introducing a multi-bank interleaved storage structure, this invention allows for parallel reading and updating of the BTB branch prediction buffer, significantly reducing read / write conflict rates, minimizing prediction pipeline interruptions, and improving the continuity and bandwidth utilization of the processor's front-end instruction fetching. This invention also adds a renaming conflict detection and redirection mechanism during the instruction decoding stage, which can quickly correct minor address name misjudgments caused by tag compression, effectively ensuring the correctness of prediction results and system stability. In summary, this invention is low-cost and highly compatible, saving significant logic resources and chip area with only a 1% loss in prediction performance, while significantly improving clock frequency and energy efficiency, and optimizing circuit performance. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained from these drawings without creative effort.

[0014] Figure 1 A flowchart of the first method for implementing an efficient and low-cost branch prediction circuit is shown. Figure 2 A flowchart of a second method for implementing an efficient and low-cost branch prediction circuit is shown. Figure 3 A system framework diagram of a high-efficiency, low-cost branch prediction circuit implementation system is shown. Figure 4 A circuit topology diagram of an efficient and low-cost branch prediction circuit is shown. Detailed Implementation

[0015] To better understand the above-mentioned objectives, features, and advantages of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be combined with each other.

[0016] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and therefore the scope of protection of the invention is not limited to the specific embodiments disclosed below.

[0017] The first aspect of this invention provides a method for implementing a highly efficient and low-cost branch prediction circuit, such as... Figure 1 , 4 As shown, it includes the following steps: S102: Using the low-order part of the PC program counter as an index, the BTB branch target information and the corresponding physical tag value are extracted from the SRAM static random access memory. After aligning the PC program counter and the BTB branch target buffer in terms of timing, the address of the current instruction to be fetched is hashed and compressed. The bit width of the hash compression circuit is compared with the bit width of the physical tag value to predict the branch hit instruction. The instruction is immediately read and jumps to the PC address of the next branch target instruction. S104: Obtain the physical bank storage partition encoded by the last low bit of the PC program counter pointer, obtain the access pointer encoding bit, detect and locate the update write operation and the predictive read operation of the branch hit instruction in the BTB branch target buffer of the processor backend, and determine whether the update write operation and the predictive read operation are in the same physical bank storage partition based on the access pointer encoding bit, and execute the corresponding write permission and truncation operations. S106: Decode the actual branch target jump instruction at the address of the instruction to be fetched, obtain the first branch instruction type, perform a renaming conflict consistency analysis on the first branch instruction type based on the second branch instruction type of the branch prediction hit instruction, and output the renaming conflict detection result; S108: Based on the renaming conflict detection result, flush the renaming conflict BTB instruction entry and invalidate the conflict content. Then, correct the error and missing instruction fetch by calculating the check bit of the real branch target jump instruction of the current instruction fetch address. In this way, initiate a new instruction fetch request action based on the redirected instruction fetch address.

[0018] It should be noted that the BTB branch target buffer of the present invention adopts an optimized multi-physical bank interleaved storage structure, which is interleaved according to the format of 4 physical banks, and the read-write conflict rate can be effectively reduced to 1 / 16.

[0019] Preferably, S102, as Figure 2 As shown, the specific steps include: Obtain the address of the currently pending instruction from the PC program counter in the target computer, and at the same time obtain the target computer's current addressing grace period; Construct an instruction fetch request sub-item based on the current instruction address to be fetched, and simultaneously activate the access operations of the SRAM static random access memory and the BTB branch target buffer when the PC program counter sends the instruction fetch request sub-item. During the access operation, a series of low-order index values ​​are established based on the low-order portion of the PC program counter with a predetermined positioning tolerance. Based on the series of low-order index values, branch data is read in parallel from multiple physical bank storage partitions in the SRAM static random access memory to obtain the BTB branch target information and the corresponding XOR hash compressed physical tag value of each BTB branch target information. Obtain the read latency period threshold of the SRAM static random access memory, introduce a register based on the read latency period threshold, and construct the pipeline register stride of the register. By responding to the reading rhythm of the pipeline register step, the PC program counter when sending the current instruction address to be fetched is aligned in timing with the access output of the BTB branch target buffer. After alignment, the key-value pairs of the current instruction address to be fetched are processed in blocks. A hash mixing unit is constructed to perform XOR accumulation calculation on each key-value address block for mixing compression, and the hash compression circuit bit width of the current instruction address to be fetched is output. If the matching degree between the bit width of the hash compression circuit and the bit width of the physical tag value is greater than the preset matching degree, the BTB branch target information corresponding to the physical tag value is marked as a branch prediction hit instruction, the branch prediction result is output, and the PC address of the next branch target instruction is immediately read and jumped based on the branch prediction result.

[0020] It should be noted that by simultaneously initiating the reading of the instruction SRAM static random access memory and the BTB branch target buffer while issuing the instruction fetch request, i.e., triggering instruction fetch and prediction read synchronously, the reading of BTB branch target information and physical tag values ​​is parallelized with instruction fetch, effectively overlapping access latency, reducing front-end waiting time, and reducing the overall number of cycles from instruction fetch to prediction decision. Subsequently, the low-order bits of the PC program counter are used to generate physical bank indexes, and BTB entries and their already XOR hash-compressed physical tags are read in parallel from multiple physical banks according to this series of indexes. This significantly reduces the complexity of comparison logic and critical path length, maintains an acceptable hit rate and conflict probability, and effectively saves area and increases clock frequency. It is worth noting that this invention improves concurrent bandwidth and significantly reduces single-bank read / write conflicts through multi-physical-bank interleaved parallel reading, while storing compressed physical tags, reducing SRAM bit width occupation. Specifically, by using the SRAM read delay (typically one clock cycle) to insert registers and a set of pipeline stage register ticks at the front end to align the data flow, the PC program counter uses a register to tick and then aligns with the output of the BTB branch prediction buffer. This transforms timing uncertainty into a controllable pipeline depth, thereby controlling the time it takes for data to travel from the SRAM static random access memory and the BTB output to the comparison unit. This ensures that the PC register and the BTB branch prediction buffer output are parallel in the correct cycle, guaranteeing that hash compression and comparison are performed at the correct time. This achieves the minimum prediction delay per cycle and improves the throughput and stability of the processing front end.

[0021] It should be noted that the PC program counter, after one clock cycle, divides the address of the instruction to be fetched into blocks and sends them to the hash mixing unit. The XOR accumulation and mixing compression compresses the PC to the same bit width as the stored tag, thus obtaining a hash-compressed PC tag. Its actual bit width is smaller than the physical tag bit width stored in the BTB branch target information. For example, in a 64-bit physical address, the compressed physical tag bit width only needs 16 bits. The number of comparator logic resources for 16 bits is much smaller than that for 64 bits, greatly increasing circuit speed. This ensures savings in bit width comparison logic and, through reasonable hash compression design, controls the collision probability within an acceptable range, significantly accelerating circuit speed. If the degree of agreement between the hash compression circuit bit width and the physical tag value bit width is greater than a preset degree of agreement, it indicates that the branch target information is a target hit predicted by the PC program counter branch, considered a prediction hit. Due to the significant increase in circuit speed, the PC of the next instruction can be predicted immediately in the current comparison cycle. The instruction for the new jump target PC can be randomly fetched in the next clock cycle, ensuring that there are no gaps in the instruction output from the branch instruction to the branch target address. Therefore, when a prediction hits, the processor front-end can immediately use the prediction result to initiate a read or jump to the branch target PC, thereby fetching the target instruction in the next cycle. This effectively eliminates fetch bubbles caused by branches and ensures uninterrupted instruction fetch bandwidth. This method can reduce the bit width and logic depth of the SRAM static random access unit and comparator, thus significantly saving area and increasing the maximum frequency. The hash compression of the PC can speed up the circuit, and the parallel bank design effectively reduces read / write conflicts and improves the parallelizable update and read performance.

[0022] Preferably, the step of aligning and processing the key-value pairs of the current instruction address to be fetched in blocks, constructing a hash mixing unit to perform XOR accumulation calculation on each key-value address block for mixed compression, and outputting the hash compression circuit bit width of the current instruction address to be fetched, specifically includes the following steps: An XOR hash algorithm is introduced to construct a hash compression domain. Based on the established location tolerance, the address of the instruction to be fetched is divided into N key-value address blocks, and each key-value address block is loaded into the hash compression domain. Construct hash mixing units, and use hash mixing units as driving terms to mix and multiply the hash functions between one key-value address block and another key-value address block in the hash compression domain, and perform Booth shift encoding operation of mixed multiplication to generate a mixed hash partial product matrix and the shift weight of each mixed hash partial product; Align each hybrid hash partial product according to the shift weight, and then perform parallel compression of each partial product column in the hybrid hash partial product matrix starting from the lowest column to generate a hash compression tree structure. Extract the new partial product rows and corresponding hash compression leaf node layouts after parallel compression of each partial product column using the hash compression tree structure. Repeat the parallel compression steps described above to continue compressing the partial product columns generated by the new partial product rows. If the deviation between the hash compression leaf node layout and the preset hash compression leaf node layout is less than the preset deviation threshold, then stop continuing the parallel compression operation and output the XOR cumulative register product of the key-value address blocks after hybrid compression. Obtain the current hash accumulation value of the address to be fetched, and merge the current hash accumulation value with all key-value addresses in blocks based on the XOR accumulation register product, and finally output the hash compression circuit bit width of the address to be fetched.

[0023] It should be noted that by dividing the current instruction address to be fetched into blocks, discretizing it into N key-value address blocks, each key-value address block can be synchronously and parallelly computed within one time cycle of SRAM read latency, reducing critical path latency. The hash mixing unit is the processing space mainly used for hash function hybrid compression of the key-value address blocks. Within the hash mixing unit, each address bit of each key-value address block is multiplied one by one, thus decomposing the complex multi-bit address multiplication of the current instruction address to be fetched into multiple simple shifts, forming multiple hybrid hash partial products, which can reduce the compression cycle of the PC instruction. The Booth shift encoding operation is used to locate the position of the corresponding multiplier bit of each hybrid hash partial product, i.e., the shift weight, providing an alignment basis for subsequent parallel compression. Subsequently, according to the shift weight of each hybrid hash partial product, each row of partial products is shifted left by the corresponding number of bits, for example, the a-th row is shifted left by a bits, thus aligning bits with the same shift weight to the same column, forming a weighted addition matrix, which makes the parallel column compression of different initial PC instruction addresses more suitable and accurate. The parallel compression of each partial product column in the hybrid hash partial product matrix, starting from the lowest column, involves a base shift. Specifically, every 3 bits are compressed using a FA full adder of a 3:2 compressor. If 2 bits remain, they are compressed using a HA half adder of a 2:2 compressor. This allows multiple bits with the same weight to be compressed into two bits. With each layer of compression, the number of rows is reduced to about 2 / 3 of the original. This reduces the number of rows in the partial product matrix while preserving the accuracy of the values, achieving parallel compression rather than serial addition, and ultimately generating a tree structure for hash compression.

[0024] It should be noted that if the deviation between the hash compression leaf node layout and the preset hash compression leaf node layout is less than the preset deviation threshold, it means that the partial product rows generated by the current hash compression tree structure for compressing the current instruction address to be fetched have not yet reached the preset number of partial product rows. For example, if the preset is to retain only 2 partial product rows, and the current number of partial product rows is 3, it means that there is still hash compression space, so the compression process continues; otherwise, the compression process stops. This method can divide the current instruction address to be fetched by the PC program counter into blocks and perform layered hybrid compression on each block through a parallel compression tree structure. This allows the hash compression of the PC instruction address to be limited to a suitable bit width range, improving the accuracy of comparison with the physical tag and making the value retrieval and speed of circuit branch prediction more reliable.

[0025] Preferably, step S104 specifically includes the following steps: Obtain the last low-order data of the branch target jump instruction pointed to by the PC program counter pointer, encode the different physical bank storage partitions in the BTB branch target buffer according to the last low-order data, and generate the access pointer encoding bit for each physical bank storage partition. The system detects whether there is a true jump result of the branch prediction hit instruction during the execution phase by checking the back-end of the processor of the target computer. If there is, it obtains the actual branch target information, updates the actual branch target information and writes it into the BTB branch target buffer on the current cycle timing, and generates a real-time update pulse signal. A read-aware network based on a burst read access monitoring architecture is deployed in the BTB branch target buffer. The read-aware network is used to detect access to the processor front-end read branch prediction hit instruction and obtain the real-time read pulse signal of the BTB branch target buffer in the current cycle timing. A signal analysis algorithm is introduced to transform and solve the response activation of the real-time update pulse signal and the real-time read pulse signal located in different physical bank storage partitions, so as to determine the physical bank storage partition when the update write operation is performed and label it as a type I physical bank storage partition; and predict the physical bank storage partition when the read operation is performed and label it as a type II physical bank storage partition. If the access pointer bit cannot be found simultaneously in the pointer bit sets of the Type I physical bank storage partition and the Type II physical bank storage partition, then update write operations and predictive read operations are allowed to be executed in parallel within the same cycle. If the access pointer bit can be found simultaneously in the pointer bit sets of both the Type I and Type II physical bank storage partitions, the update write operation is immediately stopped, a small-depth FIFO buffer queue is built, and the conflicting update write operations are stored in the FIFO buffer queue for delayed buffering.

[0026] It should be noted that traditional BTB SRAM implementations typically use a single-port SRAM structure. When updating the BTB branch instruction content at the processor backend, conflicts may occur with the predicted read operation. This usually requires delaying the update operation or interrupting the predicted read operation, both of which significantly impact the branch prediction output. To address this, this method uses the low-order bits of the PC program counter pointer to encode each physical bank storage partition, generating a lightweight, parallel-queryable encoded bit vector. This allows for the rapid determination of the potential target physical bank currently being accessed by the frontend, providing low-complexity pointing information for multi-bank interleaving structures. This facilitates real-time conflict detection and parallel access decisions, reducing query overhead and latency. The confirmed actual branch target during execution is then fed back to the BTB partition prediction buffer. Upon confirming the branch result, the BTB immediately updates the corresponding entry and generates a monitorable real-time write pulse on the BTB side to identify the timing of the write operation, providing timing information for subsequent concurrent conflict detection. Synchronously, a perception layer network is deployed within the BTB partition prediction buffer to capture read access events from the front end in real time and generate corresponding read pulses. Unlike relying solely on static index analysis, the read perception network provides online dynamic observation capabilities, enabling it to detect burst reads and hot banks, thus improving the sensitivity and accuracy of instantaneous predicted read responses of physical banks in the BTB partition prediction buffer. Subsequently, by converting the temporal pulse events into a time-frequency domain representation using short-time Fourier transform, the temporal spectrum curves of update write operations and predicted read operations are obtained, namely the first and second temporal spectrum curves. This reveals the periodicity, burstiness, and spectral peaks of read and write events. That is, periodically recurring update or read hotspots will form obvious peaks in the spectrum. Therefore, using frequency domain "peaks" as a more robust hotspot indicator facilitates subsequent conflict trend detection based on spectral characteristics, effectively detecting temporal clustering and periodic conflicts, rather than just instantaneous overlap.

[0027] It should be noted that this method establishes a spike tracking space based on the multi-bank interleaved storage structure of the BTB partition prediction buffer as an analysis and attribution tool. The extracted spikes (spectral point clusters) are mapped back to their specific physical bank storage partitions according to the spike spectral response attributes of different physical bank storage partitions. This identifies the physical bank target that update write operations and predictive read operations favor, achieving finer-grained bank role identification through spectrum attribution. Type I physical bank storage partitions are primarily triggered by update write operations, while Type II physical bank storage partitions are primarily triggered by predictive read operations. If the access pointer code bits cannot be simultaneously found in the pointer code bit sets of both Type I and Type II physical bank storage partitions, it indicates that neither Type I nor Type II physical bank storage partitions point to the target bank. This means that update write operations and predictive read operations do not access the same physical bank storage partition, thus allowing update write operations and predictive read operations to execute in parallel within the same cycle. If the access pointer bit can be found simultaneously in the pointer bit sets of both Type I and Type II physical bank storage partitions, the update write operation should be immediately stopped. This indicates that both operations are pointing to the target bank, meaning that the update write operation and the predictive read operation are accessing the same physical bank storage partition at the same time, which may lead to a conflict. Therefore, the update write operation should be stopped immediately and queued into a small-depth FIFO buffer queue to delay execution and avoid polluting reads or causing race conditions, greatly reducing the interruption of the predictive pipeline caused by update writes. The small-depth FIFO buffer queue can provide a bounded, low-latency write buffer, which can smooth short-term burst write pressure and avoid unlimited waiting.

[0028] Preferably, step S106 specifically includes the following steps: A renaming conflict detection circuit is established and deployed in the subsequent pipeline of the corresponding processor of the target computer, and an instruction decoding algorithm is introduced to construct an instruction decoding dictionary that conforms to the branch instruction encoding and translation. The instruction decoding dictionary performs preliminary decoding on the actual branch target jump instruction at the current instruction address to be fetched in the renaming conflict detection circuit, obtains the instruction type information of the actual branch target jump instruction, and defines it as the first branch instruction type. In the initial decoding process, a decoding reference template is established by progressively parsing the decoding output of the actual branch target jump instruction. The instruction decoding dictionary is then used again to decode the branch prediction hit instruction in accordance with the decoding reference template to obtain the instruction type information of the branch prediction hit instruction, which is defined as the second branch instruction type. A decoding hash algorithm is introduced to calculate the decoding hash function where there is an inconsistency in the encoded characters between the second branch instruction type and the first branch instruction type. The decoding misalignment magnitude between the actual branch target jump instruction and the predicted branch hit instruction is determined based on the decoding hash function. If the decoding misalignment magnitude is greater than the preset decoding misalignment magnitude, it indicates that the branch prediction hit instruction has a higher distortion rate than the actual branch target jump instruction, which is a false prediction. The branch prediction hit instruction is marked as a rename conflict BTB instruction entry, and the rename conflict detection result is output.

[0029] It should be noted that, due to the hash compression of physical tags during branch prediction, address renaming conflicts inevitably occur, meaning multiple different addresses map to the same BTB index address and have the same physical tag. To address this, this method adds a dedicated microcode-supported renaming conflict detection circuit to the processor backend to detect renaming conflicts caused by physical hash compression. Simultaneously, a decoding dictionary is established to map binary codes to instruction semantic fields. The hardware has the ability to acquire and parse instruction codes in real time, and the decoding dictionary provides a stable semantic layer reference. Next, the actual branch target instruction is decoded, and its type fields (such as condition codes, target addressing modes, call / return flags, delay slot attributes, etc.) are extracted. Instruction decoding provides accurate semantic-level instruction type information, which is used as a standard to determine whether the BTB branch prediction entry matches the actual instruction in terms of type semantic encoding. By using the accurate first branch instruction type to calibrate the prediction information of the previous BTB comparison output, the decoding hash algorithm converts the two type decoding outputs into hash vector representations and calculates the inconsistency between them, i.e., the decoding misalignment magnitude, thereby quantifying the degree of misalignment or distortion in type decoding. This method enables renaming conflict detection in subsequent pipeline stages for address renaming conflicts occurring in hash-compressed physical tags, thus preventing instructions with incorrectly predicted addresses from entering the back-end pipeline and improving the branch prediction accuracy of the circuit.

[0030] Preferably, step S108 specifically includes the following steps: Extract all rename conflicting BTB instruction entries from the BTB branch target buffer based on the rename conflict detection results, and add them to the queue to be cleared. At this point, the address sequence chain of the actual branch target jump instruction is obtained and the check bits for bit errors are calculated. Based on the type of the first branch instruction, different check bits are placed at the binary power positions of the address sequence chain. Even parity is introduced. Based on the decoding misalignment magnitude, the sequence bits of the binary representation of all power positions are checked in the even parity method to obtain the redundancy value of each parity bit. The redundancy value of each parity bit is combined with the sequence bits one by one to correct the misalignment or missing value, and the directional compensation code character for correcting the instruction fetch error of the real branch target jump instruction is generated. Repeat the above verification calculation steps to calculate the branch prediction hit instruction in the BTB branch target buffer to obtain the check bit of the branch prediction hit instruction. XOR the check bit of the real branch target jump instruction with the check bit of the branch prediction hit instruction to obtain the XOR composite value. At this point, all rename conflict BTB instruction entries in the queue to be cleared are flushed and the conflicting content stored in the BTB branch target buffer is invalidated. After flushing and invalidation, the error is corrected using directional compensation encoded characters based on the redundant position indicated by the XOR composite value, a redirected instruction fetch address is generated, and a new instruction fetch request is initiated based on the redirected instruction fetch address.

[0031] It should be noted that by locating and clearing all entries identified as renaming conflicts in the BTB branch prediction buffer, the reuse of erroneous branch predictions based on these entries is prevented in the future. Simultaneously, these entries are invalidated, awaiting subsequent correct write-back or refill, directly improving the accuracy of branch prediction and pipeline stability. After clearing conflict entries, the sequence of the true branch target address is extracted, and check bits are calculated bit by bit. These check bits construct redundant information for error correction, generating a set of check / redundancy bits associated with the true address sequence. These bits are mapped according to a predetermined power, forming an encoding structure for identifying and locating bit misalignments or missing bits, thus providing locatable redundant information for automatic redirection error correction of the true instruction. Next, based on the decoding misalignment magnitude calculated from the previous renaming conflict, even parity is used as input to calculate and generate redundant check values ​​bit by bit. When bit flips, misalignments, or missing bits are detected, the check redundancy can be used to quickly locate the erroneous bits and generate compensation characters, thereby restoring the correct true branch target address or at least generating corrective codes for redirection, i.e., directional compensation code characters. Then, the same format of check bits is calculated for the predicted entries in the queue to be cleared, and an XOR operation is performed with the check bits of the real branch target (reference) to generate an XOR composite value to identify the difference position or difference pattern. This XOR composite value can directly point to the difference between the detected predicted entry and the real entry in the check field. If the XOR result is zero, the check is consistent; if it is non-zero, a 1 indicates a difference in the sequence field. This method can issue a redirect fetch instruction address after conflict detection in the subsequent pipeline. Once a renaming conflict detection result is found to be inconsistent and a jump target PC has been issued, the instruction of the wrong path is flushed and the conflict content stored in the BTB is invalidated. Then, a new redirect fetch instruction address is initiated. When a new fetch instruction is initiated by redirection, since the conflict storage content in the BTB has been cleared, the new read will not match the physical tag. The information of the correct physical tag will be updated and written to the BTB storage SRAM in the branch prediction stage after the instruction enters the back-end execution stage. When the instruction is executed again, the correct BTB prediction information can be obtained and the hit is accurate. Since the probability of conflict cannot be completely eliminated, it will inevitably have some impact on the efficiency of branch prediction. Actual benchmark tests show that the impact of using this circuit on branch prediction performance is less than 1%, but the actual saving of SRAM resource area and the increase in chip clock frequency are very significant. The overall benefits far outweigh the impact on prediction performance.

[0032] A second aspect of the present invention provides a high-efficiency, low-cost branch prediction circuit implementation system, such as... Figure 3As shown, the system includes: a memory 301, a processor 302, and a communication interface 303. The memory 301 includes a program for implementing a high-efficiency and low-cost branch prediction circuit. The communication interface 303 is used for data connection and communication between the memory 301 and the processor 302. When the program for implementing the branch prediction circuit is executed by the processor 302, it implements any of the steps of the branch prediction circuit implementation method described above.

[0033] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A high-efficiency low-cost branch prediction circuit implementation method, characterized in that, The method comprises the following steps: S102: extracting BTB branch target information and corresponding physical Tag value from SRAM static random access memory by using low bit part of PC program counter as index, aligning PC program counter and BTB branch target buffer in time sequence, compressing current instruction address to be fetched by using hash compression circuit, comparing bit width of hash compression circuit and bit width of physical Tag value to predict branch hit instruction, immediately reading and jumping to next branch target instruction PC address; S104: obtaining end low bit data coding physical bank storage partition of PC program counter pointer, obtaining access pointing coding bit, detecting update write operation of processor back end in BTB branch target buffer and prediction read operation of branch hit instruction, judging whether update write operation and prediction read operation are in same physical bank storage partition based on access pointing coding bit to perform corresponding write permission and stop operation; S106: decoding real branch target jump instruction of current instruction address to be fetched, obtaining first branch instruction type, performing decoding misalignment and renaming conflict consistency analysis on first branch instruction type based on second branch instruction type of branch prediction hit instruction, and outputting renaming conflict detection result; S108: flushing renaming conflict BTB instruction item and invalidating conflict content according to renaming conflict detection result, and correcting errors and omissions of fetched instructions by performing check bit calculation on real branch target jump instruction of current instruction address to be fetched, so as to initiate new instruction fetch request action according to redirected instruction fetch address.

2. The method of claim 1, wherein, The S102 specifically comprises the following steps: obtaining current instruction address to be fetched of PC program counter in target computer, and obtaining predetermined bit width limit of target computer; based on current instruction address to be fetched, constructing instruction fetch request subitem, and synchronously activating access operation of SRAM static random access memory and BTB branch target buffer when PC program counter sends the instruction fetch request subitem; during the access operation, using low bit part of PC program counter to establish a series of low index values based on the predetermined bit width limit, and reading branch data from a plurality of physical bank storage partitions in the SRAM static random access memory in parallel according to the series of low index values to obtain BTB branch target information and physical Tag value corresponding to each BTB branch target information and corresponding XOR hash compression; obtaining read delay period threshold of SRAM static random access memory, introducing a register based on the read delay period threshold, and constructing pipeline register step width of the register; aligning PC program counter when current instruction address to be fetched is sent in time sequence with access output of BTB branch target buffer by using read rhythm of pipeline register step width, processing key-value pair of current instruction address to be fetched after alignment in blocks, constructing hash mixing unit to perform XOR accumulation calculation for mixed compression of each key-value address block, and outputting hash compression circuit bit width of current instruction address to be fetched; If the degree of coincidence between the bit width of the hash compression circuit and the bit width of the physical Tag value is greater than a preset degree of coincidence, the BTB branch target information corresponding to the physical Tag value is marked as a branch prediction hit instruction, a branch prediction result is output, and a PC address of a next branch target instruction is read and jumped based on the branch prediction result.

3. The method of claim 2, wherein, The aligned key-value address blocks are processed, an exclusive-OR accumulation calculation of a hash mixing unit is constructed to mix and compress each key-value address block, and a hash compression circuit bit width of the current instruction address to be fetched is output, specifically including the following steps: An exclusive-OR hash algorithm is introduced to construct a hash compression field, the current instruction address to be fetched is segmented into N key-value address blocks based on a given bit width limit, and each key-value address block is loaded into the hash compression field; A hash mixing unit is constructed, the hash mixing unit is taken as a driving item to mix and multiply a hash function between a certain key-value address block and another key-value address block in the hash compression field, a Booth shift coding operation of the mixed multiplication is performed, a mixed hash partial product matrix and a shift weight of each mixed hash partial product are generated; According to the shift weight, each mixed hash partial product is aligned, and after the alignment, a radix shift of each partial product column in the mixed hash partial product matrix is parallel compressed from the lowest column to generate a hash compression tree structure; The new partial product row after the parallel compression of each partial product column is extracted through the hash compression tree structure, and the corresponding hash compression leaf node layout is extracted, and the above parallel compression step is repeated to continue the compression processing of the partial product column generated by the new partial product row; If the deviation degree between the hash compression leaf node layout and a preset hash compression leaf node layout is less than a preset deviation threshold, the parallel compression operation is stopped, and an exclusive-OR accumulation register product of the mixed and compressed key-value address block is output; A current hash accumulation value of the current instruction address to be fetched is obtained, the current hash accumulation value is fused with all key-value address blocks based on the exclusive-OR accumulation register product, and finally a hash compression circuit bit width of the current instruction address to be fetched is output.

4. The method of claim 1, wherein, The S104 specifically includes the following steps: Low-bit data at the end of the branch target jump instruction pointed to by the PC program counter pointer is obtained, different physical bank storage partitions in the BTB branch target buffer are encoded according to the low-bit data at the end, and an access pointing encoding bit of each physical bank storage partition is generated; Whether there is a real jump result of a branch prediction hit instruction in the execution stage is detected through the processor back end of the target computer, if there is, actual branch target information is obtained, the actual branch target information is updated and written into the BTB branch target buffer at the current cycle timing, and a real-time update pulse signal is generated; A read-aware network based on a burst read access monitoring architecture is deployed in the BTB branch target buffer, the read-aware network is used to detect the access of the processor front end reading the branch prediction hit instruction, a real-time read pulse signal of the BTB branch target buffer at the current cycle timing is obtained, and The signal analysis algorithm is introduced to transform and solve the response activation of the real-time update pulse signal and the real-time read pulse signal located in different physical bank storage partitions, so as to determine the physical bank storage partition in the update write operation, which is marked as a type of physical bank storage partition; and the physical bank storage partition in the predicted read operation, which is marked as a type of physical bank storage partition; If the access pointing code bits cannot be simultaneously queried in the pointing code bits of the type of physical bank storage partition and the type of physical bank storage partition, the update write operation and the predicted read operation are allowed to be executed in parallel in the same cycle; If the access pointing code bits can be simultaneously queried in the pointing code bits of the type of physical bank storage partition and the type of physical bank storage partition, the update write operation is immediately stopped, a small-depth FIFO buffer queue is constructed, and the update write operation in conflict is stored in the FIFO buffer queue for delay buffering.

5. The method of claim 1, wherein, The S106 specifically includes the following steps: A renaming conflict detection circuit is established and arranged in the back-stage pipeline of the processor corresponding to the target computer, and an instruction decoding algorithm is introduced to construct an instruction decoding dictionary conforming to the branch instruction code translation; The real branch target jump instruction at the current instruction address is preliminarily decoded in the renaming conflict detection circuit through the instruction decoding dictionary, the instruction type information of the real branch target jump instruction is obtained, and the real branch target jump instruction is defined as a first branch instruction type; In the preliminary decoding process, a decoding reference template is established according to the instruction type of the real branch target jump instruction, and the branch prediction hit instruction is decoded again according to the decoding reference template through the instruction decoding dictionary, the instruction type information of the branch prediction hit instruction is obtained, and the branch prediction hit instruction is defined as a second branch instruction type; A decoding hash algorithm is introduced to calculate a decoding hash function that the second branch instruction type and the first branch instruction type have inconsistent encoding characters, and the decoding error amplitude of the real branch target jump instruction and the branch prediction hit instruction is determined according to the decoding hash function; If the decoding error amplitude is greater than a preset decoding error amplitude, it is indicated that the branch prediction hit instruction has a high distortion rate compared with the real branch target jump instruction, is a misprediction, and is marked as a renaming conflict BTB instruction entry, and a renaming conflict detection result is output.

6. The method of claim 1, wherein, The S108 specifically includes the following steps: All the renaming conflict BTB instruction entries in the BTB branch target buffer area are extracted through the renaming conflict detection result and added to a queue to be cleared; At this time, the address sequence chain of the real branch target jump instruction is obtained and the check bits of the bit error are calculated, different check bits are placed in the binary power position of the address sequence chain based on the first branch instruction type; An even check method is introduced, the sequence bit binary representation of all the power positions is checked and calculated in the even check method according to the decoding error amplitude, the redundancy value of each check bit is obtained, the redundancy value of each check bit is combined with the sequence bit one by one to correct the error, and the directional compensation encoding character of the real branch target jump instruction fetch error is generated. The above-mentioned check calculation step is repeated to calculate the branch prediction hit instruction in the BTB branch target buffer to obtain the check bit of the branch prediction hit instruction, and the check bit of the real branch target jump instruction is XORed with the check bit of the branch prediction hit instruction to obtain an XOR comprehensive value; At this time, all the renamed conflict BTB instruction entries in the to-be-cleared queue are flushed and the conflict content stored in the BTB branch target buffer is invalidated; After the flushing and invalidation, error correction is performed on the redundant position indicated by the XOR comprehensive value using a directional compensation code character to generate a redirected instruction address, and a new instruction request action is initiated according to the redirected instruction address.

7. A high performance low cost branch prediction circuit implementation system, characterized by, The system comprises a memory, a processor, and a communication interface, the memory comprises a high-efficiency and low-cost branch prediction circuit implementation method program, the communication interface is used for data connection and communication between the memory and the processor, and the branch prediction circuit implementation method program is executed by the processor to implement the branch prediction circuit implementation method steps in any one of claims 1-6.

Images