Word line decoding circuit and static random access memory

Abstract

The invention provides a word line decoding circuit and a static random access memory. Comprising a coding latch module, a first decoding module, a plurality of second decoding modules and a first decoding latch module, the coding latch module receives an address signal and a first clock signal, and codes the address signal to obtain a first group of coded signals; the first decoding module receives the second clock signal and the corresponding signal segment, and decodes the received signal segment according to the second clock signal to obtain a first decoded signal; the second decoding module receives the corresponding signal segment and decodes the received signal segment to obtain a second decoding signal; the first decoding latch module is connected with the first decoding module and the plurality of second decoding modules, and opens the selected word line according to the second decoding signal; the data length of the first address signal representing the row address in the address signals represents the number of the enabled word lines. According to the scheme, the adjustability of the number of word lines can be improved.

Description

Word line decoding circuit and static random access memory Technical Field

[0001] This application relates to the field of integrated circuits, and more particularly to a word line decoding circuit and a static random access memory. Background Technology

[0002] Static random access memory (SRAM) has the advantages of fast read / write speed, high stability, high process compatibility and low static power consumption. Therefore, it is widely used as an embedded memory in the on-chip cache and temporary storage of processor chips.

[0003] In practical applications, word-line decoding circuits need to adjust the number of decoders according to changes in the capacity of the static random access memory (SRAM) array. Therefore, a word-line decoding circuit with highly adjustable word line count is required to achieve this. Summary of the Invention

[0004] This application provides a word line decoding circuit and a static random access memory to improve the adjustability of the number of word lines.

[0005] In a first aspect, this application provides a word line decoding circuit, comprising: an encoding latch module, a first decoding module, and a plurality of second decoding modules. The encoding latch module receives an address signal and a first clock signal, and is used to encode the address signal in response to the first clock signal, and output a first set of encoded signals. The first set of encoded signals represents a row encoding signal and its inverted signal. The first set of encoded signals includes a plurality of signal segments, which are input one-to-one to the first decoding module and the plurality of second decoding modules. The first decoding module is connected to the encoding latch module and receives a second clock signal and a corresponding signal segment, and is used to decode the received signal segment according to the second clock signal to obtain a first decoded signal. The second decoding module is connected to the encoding latch module and receives a corresponding signal segment, and is used to decode the received signal segment to obtain a second decoded signal. The first decoding latch module is connected to the first decoding module and the plurality of second decoding modules, and is used to enable a selected word line according to the second decoded signal. The address signal includes a first address signal representing a row address, and the data length of the first address signal represents the number of enabled word lines.

[0006] In one possible implementation, the circuit further includes: a redundancy start determination module, a third decoding module, and a second decoding latch module; the redundancy start determination module receives a first clock signal, a first address signal, a preset address reference signal, and a repair enable signal, and is used to determine whether to perform repair and output a selection signal and a redundancy signal based on the first address signal and the preset address reference signal when the repair enable signal is valid; the selection signal and the redundancy signal indicate whether repair is currently being performed, the preset address reference signal indicates the row address to be repaired, and the repair enable signal indicates whether the repair function is enabled. The first decoding module is specifically used to decode the received signal segment according to the clock signal to obtain the first decoded signal when the selected signal indicates that no repair is performed; the encoding latch module is also used to encode the address signal and output the second set of encoded signals, the second set of encoded signals representing the column encoded signal and the inverted signal of the column encoded signal; the third decoding module is connected to the encoding latch module and is used to decode the second set of encoded signals to obtain the third decoded signal; the second decoding latch module is connected to the third decoding module and is used to enable the selected redundant word line according to the third decoded signal when the redundant signal indicates that repair is performed.

[0007] In one possible implementation, the redundancy start determination module includes: a signal determination unit and a latching unit; the signal determination unit receives a first address signal, a preset address reference signal, and a repair enable signal, and compares the first address signal with the preset address reference signal and outputs a determination signal; wherein, if the first address signal and the preset address reference signal are the same, the determination signal indicates that repair is performed; if they are different, the determination signal indicates that repair is not performed; the latching unit is connected to the signal determination unit and is used to respond to a first clock signal, and output and latch a selection signal and a redundancy signal according to the determination signal; the selection signal and the redundancy signal have opposite logic level states.

[0008] In one possible implementation, the signal determination unit includes an XNOR gate and a NAND gate; the XNOR gate receives a first address signal and a preset address reference signal, and the output of the XNOR gate is connected to the first input of the NAND gate; the second input of the NAND gate receives a repair enable signal; and the output of the NAND gate is connected to the input of the latch unit.

[0009] In one possible implementation, the latch unit includes: a first tri-state gate, a first inverter, a second inverter, and a first transmission gate; the input of the first tri-state gate is connected to the output of the NAND gate, and the output of the first tri-state gate is connected to the input of the first inverter; the control terminal of the first tri-state gate receives a clock signal; the output of the first inverter is connected to the input of the second inverter; the output of the second inverter is connected to one end of the first transmission gate, the other end of the first transmission gate is connected to the input of the first inverter, and the control terminal of the first transmission gate receives the first clock signal.

[0010] In one possible implementation, the encoding latch module includes: multiple encoding latch units, each corresponding one-to-one with a bit signal of the address signal; each encoding latch unit includes: a second tri-state gate, a fourth inverter, a fifth inverter, and a second transmission gate; the second tri-state gate receives the address signal, its output is connected to the input of the fourth inverter, and its control terminal receives a first clock signal; the output of the fourth inverter is connected to the input of the fifth inverter; the output of the fifth inverter is connected to one end of the third transmission gate, and the other end of the second transmission gate is connected to the input of the fourth inverter, and the control terminal of the second transmission gate receives the first clock signal.

[0011] In one possible implementation, the first decoding module includes: a first decoding unit; the input of the first decoding unit receives a second clock signal, each bit signal in the signal segment corresponding to the first decoding module in the first group of encoded signals, and the inverted signal of the bit signal; the output of the first decoding unit is used to output a first decoded signal.

[0012] In one possible implementation, the second decoding module includes: a second decoding unit; the input of the second decoding unit receives each bit signal of the signal segment corresponding to the second decoding module in the first set of encoded signals and the inverted signal of the bit signal; the output of the second decoding unit is used to output the second decoded signal.

[0013] In one possible implementation, the third decoding module includes: a third decoding unit; the input of the third decoding unit receives the second set of encoded signals and the inverted signal of the second set of encoded signals; the output of the third decoding unit is used to output the third decoded signal.

[0014] In one possible implementation, a decoding latch module includes: a first decoding latch unit corresponding to each word line; the first decoding latch unit includes a third transmission gate, a first switch, and a first buffer; the input of the third transmission gate receives the bit signal of the first decoding signal, the control terminal of the third transmission gate receives the bit signal of the second decoding signal, the output of the third transmission gate is connected to the input of the first buffer and one end of the first switch; the other end of the first switch is grounded, and the control terminal of the first switch receives the inverted signal of the bit signal of the second decoding signal; the output of the first buffer is connected to the corresponding word line.

[0015] In one possible implementation, the second decoding latch module includes: a second decoding latch unit corresponding to each redundant word line; the second latch unit includes a second buffer, a third buffer, a fourth transmission gate, a second switch, and a fourth buffer; the input of the second buffer receives a first clock signal, the output of the second buffer is connected to the input of the third buffer, and the control terminal of the third buffer receives a redundant signal; the output of the third buffer is connected to the input of the fourth transmission gate, the control terminal of the fourth transmission gate receives the bit signal of the third decoding signal, the output of the fourth transmission gate is connected to the input of the fourth buffer and one end of the second switch; the other end of the second switch is grounded, and the control terminal of the second switch receives the inverted signal of the redundant signal; the output of the fourth buffer is connected to the corresponding redundant word line.

[0016] In one possible implementation, the circuit further includes: a switching module; the switching module is connected to the first decoding module, receives a selection signal and a first clock signal, and is used to transmit a second clock signal to the first decoding module when the selection signal indicates that repair is not performed.

[0017] In one possible implementation, the switch module includes: a fifth transmission gate and a third switch; one end of the fifth transmission gate receives a clock signal, the other end of the fifth transmission gate is connected to one end of the third switch and serves as the output of the switch module, and the control end of the fifth transmission gate receives a selection signal; the other end of the third switch is grounded, and the control end of the third switch receives the inverted signal of the selection signal.

[0018] Secondly, this application provides a static random access memory, including the word line decoding circuit described above.

[0019] In the word line decoding circuit and static random access memory of this application, the word line decoding circuit includes: an encoding latch module, a first decoding module, multiple second decoding modules, and the first decoding latch module; wherein the encoding latch module receives an address signal and a first clock signal, and in response to the first clock signal, encodes the address signal and outputs a first set of encoded signals; the first set of encoded signals represents a row encoding signal and its inverted signal; the first set of encoded signals includes multiple signal segments, which are input one-to-one to the first decoding module and the multiple second decoding modules; the first decoding module and the second decoding modules are respectively connected to the encoding latch module, receive a second clock signal and their respective corresponding signal segments, and decode the received signal segments according to the second clock signal to obtain a first decoded signal and a second decoded signal; the first decoding latch module is connected to the first decoding module and the multiple second decoding modules, and enables the selected word line according to the second decoded signal; the address signal includes a first address signal representing the row address, and the data length of the first address signal represents the number of enabled word lines. The solution of this application encodes the address signal transmitted to the encoding latch module to obtain a first set of encoded signals. Then, the signal segments from the first set of encoded signals corresponding to those in the first decoding module and multiple second decoding modules are transmitted to the first and second decoding modules respectively for decoding to obtain the corresponding decoded signals. The obtained decoded signals are then transmitted to the first decoding latch module to enable the selected word lines. The data length of the first address signal, which represents the row address in the address signals, represents the number of enabled word lines. This solution improves the adjustability of the number of word lines, simplifies the circuitry, and increases the decoding speed. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0021] Figure 1 is a schematic diagram of the word line decoding circuit of this application;

[0022] Figure 2 is a schematic diagram of the redundant startup determination module of this application;

[0023] Figure 3 is a schematic diagram of the structure of the encoding latch module of this application;

[0024] Figure 4 is a schematic diagram of the structure of the first decoding module of this application;

[0025] Figure 5 is a schematic diagram of the structure of the second decoding module of this application;

[0026] Figure 6 is a schematic diagram of the structure of the first decoding latch module of this application;

[0027] Figure 7 is a schematic diagram of the structure of the third decoding module of this application;

[0028] Figure 8 is a schematic diagram of the structure of the second decoding latch module of this application;

[0029] Figure 9 is a schematic diagram of the switch module of this application;

[0030] Figure 10 is a structural example of the static random access memory of this application.

[0031] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concepts of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0032] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0033] The terms "comprising" and "having" in this disclosure are used to indicate an open-ended meaning of inclusion, and refer to the existence of additional elements / components / etc. besides those listed; the logical symbol " / " is used to indicate the logical meaning of "or"; the terms "first" and "second," etc., are used only as markings or distinctions, and are not intended to limit the order or quantity of the objects. Furthermore, the different elements and areas in the accompanying drawings are only schematic and are therefore not limited to the dimensions or distances shown in the drawings. The term "connection" in this disclosure can refer to a direct connection or an indirect connection.

[0034] Static random access memory (SRAM) has the advantages of fast read / write speed, high stability, high process compatibility and low static power consumption. Therefore, it is widely used as an embedded memory in the on-chip cache and temporary storage of processor chips.

[0035] In practical applications, word-line decoding circuits need to adjust the number of decoding lines according to changes in the capacity of the static random access memory (SRAM) array. Therefore, a word-line decoding circuit with highly adjustable word line count is required.

[0036] The technical solutions of this application will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. In the description of this application, unless otherwise expressly specified and limited, the terms should be broadly understood within the art. The embodiments of this application will now be described with reference to the accompanying drawings.

[0037] Example 1

[0038] The word line decoding circuit of this application includes: an encoding latch module 11, a first decoding module 12, multiple second decoding modules 13, and a first decoding latch module 14;

[0039] The encoding latch module 11 receives the address signal and the first clock signal, and is used to encode the address signal in response to the first clock signal and output the first set of encoded signals. The first set of encoded signals represents the row encoded signal and the inverted signal of the row encoded signal. The first set of encoded signals includes multiple signal segments, and the multiple signal segments are input to the first decoding module 12 and the multiple second decoding modules 13 in a one-to-one correspondence.

[0040] The first decoding module 12 is connected to the encoding latch module 11, and receives the second clock signal and the corresponding signal segment. It is used to decode the received signal segment according to the second clock signal to obtain the first decoded signal.

[0041] The second decoding module 13 is connected to the encoding latch module 11, receives the corresponding signal segment, and is used to decode the received signal segment to obtain the second decoded signal.

[0042] The first decoding latch module 14 is connected to the first decoding module 12 and multiple second decoding modules 13, and is used to enable the selected word line according to the second decoding signal; the address signal includes a first address signal representing the row address, and the data length of the first address signal represents the number of enabled word lines.

[0043] In practical applications, the word-line decoding circuit provided in this example can be used in static random access memory. The encoding latch module 11 receives the address signal and the first clock signal from the controller, and in response to the first clock signal, encodes the received address signal and outputs the first set of encoded signals. Specifically, the first clock signal is the initial clock signal input to the encoding latch module; the address signal includes row address signal and column address signal; as an example, if the address signal is A[n:0], then the corresponding row address signal is represented as [x:0], and the corresponding column address signal is [x+1:0], that is, the column address signal can be represented as [y:0]. [x+1:0] and [y:0] correspond to each other, representing the column address signal; when the address signal is input to the encoding latch module, the corresponding row address signal is encoded and outputs the corresponding first group of encoded signals. The first group of encoded signals includes multiple groups of row encoded signals and the inverted signal of the row encoded signal; at the same time, the corresponding column address signal is encoded and outputs the corresponding second group of encoded signals. The second group of encoded signals includes multiple groups of column encoded signals and the inverted signal of the column encoded signal, which is subsequently input to the third decoding module 16. The first group of encoded signals is input to the subsequent first decoding module 12 for decoding; the first group of encoded signals corresponds to multiple encoded signal segments, and the multiple signal segments correspond one-to-one with the first decoding module 12 and the multiple second decoding modules 13. The first decoding module 12 is connected to the encoding latch module 11. It receives a second clock signal and a corresponding signal segment, and decodes the received encoded signal segment according to the second clock signal to obtain a first decoded signal. The second clock signal represents the clock signal input to the first decoding module. In this example, the signal segment input to the first decoding module 12 is a two-bit signal, which is decoded to generate a four-bit decoded signal. The second decoding module 13 is connected to the encoding latch module 11. It receives the encoded signal of the corresponding signal segment generated by the encoding latch module 11 and decodes it to obtain the second decoded signal. The first decoding module 12 and multiple second decoding modules 13 are connected to the first decoding latch module 14. The first decoding latch module 14 activates the selected word line according to the second decoded signal. In practical applications, the number of word lines is represented by the signal length of the first address signal, which represents the row address signal in the address signal. The word line decoding circuit in this example activates the selected word line by transmitting the signal segments of the first group of encoded signals to the corresponding first decoding module and multiple second decoding modules for decoding. The number of word lines is represented by the signal length of the first address signal representing the row address signal in the address signal. The word line is highly adjustable, while also taking into account the decoding speed.

[0044] Based on the foregoing example, in one example, the word line decoding circuit of this application further includes: a redundancy start determination module 15, a third decoding module 16, and a second decoding latch module 17;

[0045] The redundancy start determination module 15 receives a first clock signal, a first address signal, a preset address reference signal, and a repair enable signal. When the repair enable signal is valid, it determines whether to perform repair based on the first address signal and the preset address reference signal and outputs a selection signal and a redundancy signal. The selection signal and the redundancy signal indicate whether repair is currently being performed, the preset address reference signal indicates the row address to be repaired, and the repair enable signal indicates whether the repair function is enabled.

[0046] The first decoding module 12 is specifically used to decode the received signal segment according to the second clock signal to obtain the first decoded signal when the selected signal representation does not perform repair.

[0047] The encoding latch module 11 is also used to encode the address signal and output a second set of encoded signals, the second set of encoded signals representing the column encoded signal and the inverted signal of the column encoded signal; the third decoding module 16 is connected to the encoding latch module 11 and is used to decode the second encoded signal to obtain a third decoding signal; the second decoding latch module 17 is connected to the third decoding module 16 and is used to enable the selected redundant word line according to the third decoding signal when the redundant signal represents the performance of repair.

[0048] Specifically, the redundancy start determination module 15 receives a first clock signal, a first address signal, a pre-set address reference signal, and a repair enable signal. When the repair enable signal is valid, it determines whether repair needs to be performed based on the first address signal and the pre-set address reference signal, and outputs a selection signal and a redundancy signal. The selection signal and redundancy signal indicate whether repair needs to be performed, the pre-set address reference signal indicates the row address that needs repair, and the repair enable signal indicates whether the repair function is enabled. It should be noted that the pre-set address reference signal is a pre-configured reference signal. In practical applications, as an example, it may be necessary to perform factory testing on the static random access memory (SRAM) to obtain its relevant parameters. Based on these parameters, a pre-configured address reference signal is written into the SRAM as a reference signal for the word line decoding circuit during operation. This reference signal is a known signal of the SRAM.

[0049] Specifically, based on the selection signal and redundancy signal output by the redundancy start determination module 15, when the selection signal is activated and valid, no repair is required. At this time, the first decoding module 12 decodes the received signal segment according to the second clock signal to obtain the first decoded signal. Furthermore, the aforementioned encoding latch module 11 is also used to encode the address signal and output a second set of encoded signals. The second set of encoded signals represents the column encoded signal and its inverted signal. The third decoding module 16 is connected to the encoding latch module 11, and decodes the received second encoded signal to obtain the third decoded signal. The second decoding latch module 17 is connected to the third decoding module 16. When the redundancy signal is activated and valid, repair is required. At this time, the second decoding latch module 17 activates the selected redundant word line according to the third decoded signal. In practical applications, the number of redundant word lines is represented by the signal length representing the column address signal in the address signal. In this example, by designing a redundant start-up determination module, a third decoding module, and a second decoding latch module, the word line decoding circuit of this example has both normal addressing and redundant addressing functions, thereby improving the performance of the static random access memory.

[0050] Based on the foregoing example, in one example the circuit also includes: a switch module 18;

[0051] The switch module 18 is connected to the first decoding module 12 and receives a selection signal and a clock signal. When the selection signal indicates that repair is not performed, the clock signal is transmitted to the first decoding module 12.

[0052] Specifically, the switch module 18 is connected to the first decoding module 12. When the selection signal output by the redundancy start determination module 15 is in an active state, the switch module 18 receives the selection signal and the first clock signal, and transmits the second clock signal to the first decoding module 12. In this example, the switch module can manage the power consumption of the circuit, improve the energy efficiency of the system, and ensure that the second clock signal is transmitted to the decoding circuit at the correct time, thereby maintaining the timing stability of the entire system.

[0053] Figure 1 is a schematic diagram of the word line decoding circuit of this application. As shown in Figure 1, the redundancy start determination module 15 receives the first clock signal CLK_S, the first address signal A[x:0], the address reference signal Rep[x:0], and the repair enable signal Repair; it is used to output the selection signal SE_EN and the redundancy signal RE_EN, and determine whether to enable the repair function.

[0054] When the selection signal SE_EN is in a valid state, the repair function does not need to be enabled. At this time, the selection signal SE_EN is transmitted to the switching module 18. The switching module 18 receives the clock signal CLK_S and transmits the second clock signal CLK_D to the first decoding module 12. CLK_D represents the clock signal transmitted to the first decoding module 12.

[0055] The encoding latch module 11 receives the address signal A[n:0] and the first clock signal CLK_S. In response to the first clock signal CLK_S, it encodes the address signal A[n:0] to obtain the first set of encoded signals AX&AXB[x:0] and the second set of encoded signals AY&AYB[y:0].

[0056] When the second clock signal CLK_D is transmitted to the first decoding module 12, the first decoding module 12 receives the corresponding signal segment from the first set of encoded signals AX&AXB[x:0] generated by the encoding latch module 11 and decodes it to obtain the first decoded signal D1. Multiple second decoding modules 13 receive the signal segments corresponding to each second decoding module from the first set of encoded signals AX&AXB[x:0] generated by the encoding latch module 11 and decode them to obtain the second decoded signal D2. D2 is obtained by the joint decoding of multiple second decoding modules 13. The first decoding module 12 and the multiple second decoding modules 13 are connected to the first decoding latch module 14, transmitting the first decoded signal D1 and the second decoded signal D2 to the first decoding latch module 14. The first decoding latch module 14 then activates the selected word line according to the second decoded signal D2.

[0057] When the redundancy signal RE_EN is in a valid state, the repair function needs to be enabled; the third decoding module 16 receives the second set of encoded signals AY&AYB[y:0] generated by the encoding latch module 11, and decodes them to obtain the third decoding signal D3; the third decoding module 16 is connected to the second decoding latch module 17, and transmits the third decoding signal D3 to the second decoding latch module 17. The second decoding latch module 17 receives the first clock signal CLK_S and the selection signal RE_EN, and enables the selected redundant word line according to the second decoding signal D3.

[0058] As another example, Figure 2 is a schematic diagram of the redundant startup determination module of this application; as shown in Figure 2, the redundant startup determination module 15 includes: a signal determination unit 151 and a latch unit 152; wherein, the signal determination unit 151 includes an XOR gate 1511 and a NAND gate 1512; the latch unit 152 includes a first tri-state gate 1521, a first inverter 1522, a second inverter 1523 and a first transmission gate 1524; and a clock signal delay unit 153, the clock signal delay unit 15... 3 includes a NOR gate 1531 and a third inverter 1532. In one example, the NOR gate 1531 is connected to the third inverter 1532. The NOR gate 1531 receives the chip select signal CEN and the first clock signal CLK_S. The chip select signal CEN is active when it is low. When the first clock signal CLK_S is low, the third inverter 1532 outputs a high level. The high-level signal passes through the third inverter 1532, at which point the first clock signal is transmitted to the subsequent circuit unit module. When the first clock signal CLK_S is high, the third inverter 1532 outputs a low level. The low-level signal passes through the third inverter 1532, at which point the first clock signal is transmitted to the subsequent circuit unit module. CKB represents the signal output by the first clock signal after passing through the NOR gate 1531, and CKI represents the signal output by CKB after passing through the third inverter 1532.

[0059] In another example, the redundant start determination module 15 includes: a signal determination unit 151 and a latch unit 152;

[0060] The signal determination unit 151 receives a first address signal A[x:0], an address reference signal Rep[x:0], and a repair enable signal Repair, and compares the first address signal A[x:0] and the address reference signal Rep[x:0] and outputs a judgment signal; wherein, if the first address signal A[x:0] and the address reference signal Rep[x:0] are the same, the judgment signal indicates that repair is performed; if they are different, the judgment signal indicates that repair is not performed.

[0061] The latch unit 152 is connected to the signal determination unit 151 and is used to respond to the first clock signal, output and latch the selection signal and the redundant signal according to the determination signal; the logic level states of the selection signal and the redundant signal are opposite.

[0062] Specifically, the signal determination unit 151 receives a first address signal, an address reference signal, and a repair enable signal. The signal determination unit 151 compares the first address signal and the address reference signal, and outputs a judgment signal based on the comparison result. If the first address signal and the address reference signal are the same, repair is performed; if they are different, repair is not performed. The latch unit 152 is connected to the signal determination unit 151, responds to the first clock signal, and outputs and latches a selection signal and a redundancy signal based on the judgment signal output by the signal determination unit 151. The selection signal and the redundancy signal have opposite logic level states. The clock signal in this example is generated by the aforementioned clock signal generation module.

[0063] Furthermore, the signal determination unit 151 includes an XOR gate 1511 and a NAND gate 1512;

[0064] The XOR gate 1511 receives the first address signal and the address reference signal, and the output of the XOR gate 1511 is connected to the first input of the NAND gate 1512.

[0065] The second input of NAND gate 1512 receives the repair enable signal; the output of NAND gate 1512 is connected to the input of latch unit 152.

[0066] Specifically, the signal determination unit 151 includes an XOR gate 1511 and a NAND gate 1512; the XOR gate 1511 receives a first address signal and an address reference signal, and the output of the XOR gate 1511 is connected to the first input of the NAND gate 1512 for comparing whether the first address signal and the address reference signal are the same; the second input of the NAND gate 1512 receives a repair enable signal, and the output of the NAND gate 1512 is connected to the input of the latch unit 152.

[0067] The latch unit 152 includes: a first tri-state gate 1521, a first inverter 1522, a second inverter 1523, and a first transmission gate 1524;

[0068] The input of the first tri-state gate 1521 is connected to the output of the NAND gate 1512, and the output of the first tri-state gate 1521 is connected to the input of the first inverter 1522; the control terminal of the first tri-state gate 1521 receives the first clock signal.

[0069] The output of the first inverter 1522 is connected to the input of the second inverter 1523; the output of the second inverter 1523 is connected to one end of the first transmission gate 1524, the other end of the first transmission gate 1524 is connected to the input of the first inverter 1522, and the control terminal of the first transmission gate 1524 receives the first clock signal.

[0070] Specifically, the latch unit 152 in the redundant start determination module 15 includes: the input terminal of the first tri-state gate 1521 is connected to the output terminal of the NAND gate 1512, and the output terminal of the first tri-state gate 1521 is connected to the input terminal of the first inverter 1522; the control terminal of the first tri-state gate 1521 receives the aforementioned CKI signal. When the CKI signal is valid, the first tri-state gate 1521 is turned on; when the CKI signal is invalid, the first tri-state gate 1521 is turned off.

[0071] The output of the first inverter 1522 is connected to the input of the second inverter 1523; the output of the second inverter 1523 is connected to one end of the first transmission gate 1524, and the other end of the first transmission gate 1524 is connected to the input of the first inverter 1522. One end of the control terminal of the first transmission gate 1524 receives the CKI signal, and the other end receives the CKB signal. In practical applications, the latch unit 152 outputs and latches the selection signal and the redundancy signal. One end of the control terminal of the first transmission gate 1524 receives the clock signal, and the other end receives the inverted signal of the clock signal. In practical applications, the redundancy start determination module needs to establish paired signals during the time when the clock signal is "0". When the clock signal changes from "0" to "1", the selection signal and the redundancy signal enter the latched state. In this example, the redundancy start determination module, through the XOR gate and NAND gate in the signal determination unit, compares the address signal and the address reference signal when the repair enable signal is valid, so that the circuit can determine whether the repair function needs to be executed, thereby improving storage performance.

[0072] Based on the foregoing example, in one example, the encoding latch module 11 includes: a plurality of encoding latch units 111, each corresponding one-to-one with the bit signals of the address signal; the encoding latch unit 111 includes: a second tri-state gate 1111, a fourth inverter 1112, a fifth inverter 1113, a second transmission gate 1114; and the aforementioned clock signal delay unit 153; the second tri-state gate 1111 receives the address signal, the output terminal of the second tri-state gate 1111 is connected to the input terminal of the fourth inverter 1112, and the control terminal of the second tri-state gate 1111 receives the first clock signal;

[0073] The output of the fourth inverter 1112 is connected to the input of the fifth inverter 1113; the output of the fifth inverter 1113 is connected to one end of the second transmission gate 1114, the other end of the second transmission gate 1114 is connected to the input of the fourth inverter 1112, and the control terminal of the second transmission gate 1114 receives the first clock signal.

[0074] Specifically, Figure 3 is a schematic diagram of the structure of the encoding latch module of this application; the encoding latch module 11 includes multiple encoding latch units 111 as shown in Figure 3, and the multiple encoding latch units 111 correspond one-to-one with the bits of the address signal. As shown in Figure 3, the second tri-state gate 1111 in the encoding latch unit 111 receives the address signal A[n:0], and the output terminal of the second tri-state gate 1111 is connected to the input terminal of the fourth inverter 1112; the control terminal of the second tri-state gate 1111 receives the clock signal CKI, and similarly, the clock signal CKI is the clock signal transmitted by the signal delay unit 153. The output of the fourth inverter 1112 is connected to the input of the fifth inverter 1113. The input of the fourth inverter 1112 is the encoded address signal AQ[n:0], and its output is its inverted signal AQB[n:0]. The output of the fifth inverter 1113 is connected to one end of the second transmission gate 1114, and the other end of the second transmission gate 1114 is connected to the input of the fourth inverter 1112. One end of the control terminal of the second transmission gate 1114 receives the clock signal CKI, and the other end receives the inverted clock signal CKB. In this example, the encoding and latching module encodes and latches the address signal, improving the efficiency and accuracy of data transmission.

[0075] Based on the foregoing example, in one example, Figure 4 is a schematic diagram of the structure of the first decoding module of this application. As shown in Figure 4, the first decoding module 12 includes: a first decoding unit 121;

[0076] The input terminal of the first decoding unit 121 receives a second clock signal, each bit signal in the signal segment corresponding to the first decoding module in the first encoded signal, and the inverted signal of that bit signal;

[0077] The output terminal of the first decoding unit 121 is used to output the first decoding signal.

[0078] Specifically, the first decoding module 12 includes a first decoding unit 121. The first input terminal of the first decoding unit 121 receives a clock signal CLK_D, the second input terminal receives each bit signal AX[x1:0] of the signal segment corresponding to the first decoding module 12, and the third input terminal receives the inverted signal AXB[x1:0] of each bit signal of the signal segment corresponding to the first decoding module 12. The first decoding unit 121 decodes the signals received from these three input terminals to obtain a first decoded signal D1, and the output terminal of the first decoding unit 121 outputs the first decoded signal. In this example, decoding is performed based on the clock signal, each bit signal of the signal segment corresponding to the first decoding module in the first encoded signal, and the inverted signal of that bit signal to output the first decoded signal, thus improving the efficiency of the word line decoding circuit.

[0079] Based on the foregoing example, in one example, the second decoding module 13 includes: a second decoding unit 131;

[0080] The input terminal of the second decoding unit 131 receives each bit signal in the first encoded signal corresponding to the second decoding module and the inverted signal of that bit signal.

[0081] The output terminal of the second decoding unit 131 is used to output the second decoding signal.

[0082] Specifically, Figure 5 is a schematic diagram of the structure of the second decoding module of this application. As shown in Figure 5, the first decoding unit 131 includes: a decoder, a NAND gate, and a NOT gate; the second decoding module 13 includes the first decoding unit 131. The input terminal of the first decoding unit 131 receives each bit signal AX of the signal segment corresponding to the second decoding module 13 in the first encoded signal and the inverted signal AXB of that bit signal; the second decoding unit 131 decodes the signal received at the input terminal to obtain the second decoded signal D2, and the output terminal of the second decoding unit 131 outputs the second decoded signal D2. In practical applications, since the results of the redundancy start determination module and the encoding latch module are completed during the time when the first clock signal CLK_S is "0" in the entire word line decoding circuit operation, the delay of the word line decoding circuit mainly depends on the delay of the second decoding module plus the pulse propagation delay of the clock signal CLK_S in the first decoding module. This can be viewed as a combination of logical AND +, logical NAND +, and buffer delay. Therefore, the second decoding module is designed with a NAND gate so that after the aforementioned redundant start-up determination module and encoding latch module establish the signal, it cooperates with the subsequent first decoding latch module to enable the selected word line. In this example, each bit signal in the signal segment corresponding to the second decoding module in the first encoded signal, along with its inverted signal, is decoded to output a second decoded signal. Subsequently, the selected word line is enabled based on this second decoded signal, improving the efficiency of the word line decoding circuit.

[0083] Based on the foregoing example, in one example, the first decoding latch module 14 includes: a first decoding latch unit 141 corresponding to each word line; the first decoding latch unit 141 includes a third transmission gate 1411, a first switch 1412 and a first buffer 1413.

[0084] The input terminal of the third transmission gate 1411 receives the bit signal of the first decoded signal, the control terminal of the third transmission gate 1411 receives the bit signal of the second decoded signal, and the output terminal of the third transmission gate 1411 is connected to the input terminal of the first buffer 1413 and one end of the first switch 1412.

[0085] The other end of the first switch 1412 is grounded, and the control terminal of the first switch 1412 receives the inverted signal of the bit signal of the second decoding signal; the output terminal of the first buffer 1413 is connected to the corresponding word line.

[0086] Figure 6 is a schematic diagram of the structure of the first decoding latch module of this application; as shown in Figure 6, the first decoding latch unit 141 includes a sixth inverter 1414, one end of the sixth inverter 1414 receives the second decoding signal D2, and the other end of the sixth inverter 1414 receives the inverted signal D2B of the second decoding signal; the input terminal of the third transmission gate 1411 receives the bit signal D1 of the first decoding signal, one end of the control terminal of the third transmission gate 1411 receives the bit signal D2 of the second decoding signal, and the other end of the control terminal of the third transmission gate 1411 receives the inverted signal D2B of the bit signal of the second decoding signal; the output terminal of the third transmission gate 1411 is connected to the input terminal of the first buffer 1413 and one end of the first switch 1412; the other end of the first switch 1412 is grounded, and the control terminal of the first switch 1412 receives the inverted signal D2B of the bit signal of the second decoding signal; the output terminal of the first buffer 1413 is connected to the corresponding word line WL. Specifically, when the third transmission gate 1141 is closed, to ensure that the clock signal is no longer transmitted, the first switch 1412 is turned off, further preventing the clock signal from being transmitted backward; the function of the first buffer 1413 is to provide sufficient drive for the opening and holding of word lines. In practical applications, each word line corresponds to a first decoding latch unit 141, and each first decoding latch unit 141 is used to select to open the corresponding word line according to the first decoding signal and the second decoding signal; the total number of word lines is obtained by multiplying the number of bits of the first decoding signal and the second decoding signal. In this example, the first decoding latch module selects to open the corresponding word line according to the first decoding signal and the second decoding signal, and the total number of word lines is related to the number of bits of the first decoding signal and the second decoding signal. This example improves the adjustability of the number of word lines.

[0087] Based on the foregoing examples, in one example, Figure 7 is a schematic diagram of the structure of the third decoding module of this application; as shown in Figure 7, the third decoding module 16 includes: a third decoding unit 161;

[0088] The input terminal of the third decoding unit 161 receives the second encoded signal AY and the inverted signal AYB of the second encoded signal;

[0089] The output of the third decoding unit 161 is used to output the third decoding signal D3.

[0090] Specifically, the second decoding module 16 includes a first decoding unit 161. The input of the first decoding unit 161 receives the second set of encoded signals AY and the inverse signal AYB of the second set of encoded signals. The third decoding unit 161 decodes the signals received at its input to obtain a third decoding signal D3, and the output of the second decoding unit 161 outputs the first decoding signal D3. In this example, the third decoding unit decodes the received second set of encoded signals to obtain the third decoding signal, which is then used to enable the selected redundant word lines, improving the efficiency of the word line decoding circuit and enhancing the performance of the static random access memory.

[0091] Based on the foregoing examples, in one example, Figure 8 is a structural schematic diagram of the second decoding latch module of this application; as shown in Figure 8, the second decoding latch module 17 includes: a second decoding latch unit 171 corresponding to each redundant word line; the second decoding latch unit 171 includes a second buffer 1711, a third buffer 1712, a fourth transmission gate 1713, a second switch 1714, and a fourth buffer 1715;

[0092] The input of the second buffer 1711 receives a clock signal, and the output of the second buffer 1711 is connected to the input of the third buffer 1712. The control terminal of the third buffer 1712 receives a redundant signal. The output of the third buffer 1712 is connected to the input of the fourth transmission gate 1713. The control terminal of the fourth transmission gate 1713 receives the bit signal of the third decoded signal. The output of the fourth transmission gate 1713 is connected to the input of the fourth buffer 1715 and one end of the second switch 1714.

[0093] The other end of the second switch 1714 is grounded, and the control terminal of the second switch 1714 receives the inverted signal of the redundant signal; the output terminal of the fourth buffer 1715 is connected to the corresponding redundant word line.

[0094] Specifically, Figure 8 is a schematic diagram of the structure of the second decoding latch unit of this application; as shown in Figure 8, the second decoding latch unit includes a seventh inverter 1716 and an eighth inverter 1717; one end of the seventh inverter 1716 receives the third decoding signal D3, and the other end of the seventh inverter 1716 receives the inverted signal D3B of the third decoding signal; one end of the eighth inverter 1717 receives the redundant signal RE_EN, and the other end of the eighth inverter 1717 receives the inverted signal RE_ENB of the redundant signal; the input terminal of the second buffer 1711 receives the clock signal CLK_S, and the output terminal of the second buffer 1711 is connected to the input terminal of the third buffer 1712. The control terminal of 1712 receives the redundant signal RE_EN; the output terminal of the third buffer 1712 is connected to the input terminal of the fourth transmission gate 1713. One end of the control terminal of the fourth transmission gate 1713 receives the bit signal D3 of the third decoded signal, and the other end receives the inverted signal D3B of the bit signal D3B of the third decoded signal; the output terminal of the fourth transmission gate 1713 is connected to the input terminal of the fourth buffer 1715 and one end of the second switch 1714; the other end of the second switch 1714 is grounded, and the control terminal of the second switch 1714 receives the inverted signal RE_ENB of the redundant signal; the output terminal of the fourth buffer 1715 is connected to the corresponding redundant word line RE_WL. Specifically, when the third transmission gate 1713 is closed, the second switch 1714 is closed to prevent the redundant word line from being enabled; the second buffer 1711 is used to generate a certain delay so that the clock signal is transmitted after the redundant signal is established. The third buffer 1715 is used to buffer to generate enough drive to enable the redundant word line.

[0095] In practical applications, each redundant word line corresponds to a second decoding latch unit 171, and each first decoding latch unit 171 is used to select and enable the corresponding redundant word line according to the third decoding signal; the total number of redundant word lines is obtained based on the number of bits in the third decoding signal. In this example, the second decoding latch module enables the corresponding redundant word line according to the third selection, and the total number of redundant word lines is related to the third decoding signal. This example improves the redundant addressing performance of the memory and enhances the scalability of the memory.

[0096] Furthermore, the switch module 18 includes: a fifth transmission gate 181 and a third switch 182;

[0097] One end of the fifth transmission gate 181 receives the first clock signal, and the other end of the fifth transmission gate 181 is connected to one end of the third switch 182 and serves as the output of the switch module 18. The control end of the fifth transmission gate 181 receives the selection signal.

[0098] The other end of the third switch 182 is grounded, and the control terminal of the third switch 182 receives the inverted signal of the selection signal.

[0099] Specifically, Figure 9 is a schematic diagram of the switch module of this application. As shown in Figure 9, the switch module 18 includes a ninth inverter 183. One end of the ninth inverter 183 receives the selection signal SE_EN, and the other end receives the inverted signal SE_ENB of the selection signal. The clock signal CLK_S first passes through the fifth buffer 184 and is transmitted to the fifth transmission gate 181. One end of the fifth transmission gate 181 receives the clock signal CLK_S, and the other end of the fifth transmission gate 181 is connected to one end of the third switch 182 as the output terminal of the switch module 18. One end of the control terminal of the fifth transmission gate 181 receives the selection signal, and the other end of the control terminal of the fifth transmission gate 181 receives the inverted signal of the selection signal. The other end of the third switch 182 is grounded, and the control terminal of the third switch 182 receives the inverted signal of the selection signal. In practical applications, the third switch 182 is used to close the third switch when the fifth transmission gate 181 is not open, ensuring that the clock signal CLK_D is "0" and avoiding accidental opening of the word line.

[0100] The switching module in this example receives a selection signal and transmits the clock signal to the subsequent first-stage decoding circuit. By precisely controlling the transmission of the clock signal, the switching circuit helps reduce signal interference and timing conflicts, thereby improving the stability of the entire system.

[0101] Example 2

[0102] Based on the previous example, this example illustrates the aforementioned word line decoding circuit with a specific example. The implementation of the word line decoding circuit is illustrated by incorporating a 32K SRAM with 4 32-bit CMUX (number of serial ports) into the circuit. There are 256 word lines, each carrying 128 memory cells, i.e., 128 columns. Additionally, 4 rows of redundant word lines are needed to ensure that one normal memory cell in each column can be replaced by a redundant memory cell. 256 can be written in the form of 2^8, therefore 8 bits of address bits are needed for word line decoding. Furthermore, 2 bits are needed to implement the 4-to-1 serial port selection, resulting in a total of 10 bits for the address signal, i.e., A[9:0], where A[1:0] is allocated to column decoding and A[9:2] is allocated to row decoding. The redundancy start-up determination module can be built according to the circuit module shown in Figure 2. The external inputs are the first address signal A[9:2], the address reference signal Rep[7:0], the chip select signal, and the repair enable signal. The encoding latch module can be built using the circuit module shown in Figure 3 above. The input signals are the chip select signal and the address signal A[9:0], which are encoded to obtain the first encoding signal AX&AXB[7:0] for row decoding and the second encoding signal AY&AYB[1:0] for column decoding. The switching module can be built using the circuit module shown in Figure 9 above. The first decoding module can be implemented using a three-input first decoding unit. One input clock signal is used to transmit the clock signal for word line activation. The other two inputs are the signal segments AX[1:0] and the inverted signal AXB[1:0] of the encoding signal corresponding to the first decoding module, which generate a 4-bit first decoding signal D1[3:0]. The third decoding module uses a two-input third decoding unit. The inputs are the second encoding signal AY[1:0] and the inverted signal AYB[1:0] of the second encoding signal, which generate a 4-bit third decoding signal D3 for redundant word line decoding. Multiple second decoding modules can use the structure shown in Figure 5 above. The signal segments of the encoded signal input to the multiple second decoding modules are AX[7:2] & AXB[7:2]. The remaining 6 bits of data can be allocated to two 3-8 decoders to decode a 64-bit second decoding signal D2. The first decoding signal D1 and the second decoding signal D2 are used as inputs to the structure of the first decoding latch module shown in Figure 6 above for each word line, resulting in 256 word lines. The third decoding signal D3, the clock signal, and the redundant signal corresponding to each redundant word line are used as inputs to the structure of the second decoding latch module shown in Figure 8 above, resulting in 4 redundant word lines.

[0103] In this embodiment, the word line decoding circuit includes: an encoding latch module, a first decoding module, multiple second decoding modules, and the first decoding latch module. The encoding latch module receives an address signal and a first clock signal, and in response to the first clock signal, encodes the address signal to output a first set of encoded signals. The first set of encoded signals represents a row encoding signal and its inverted signal. The first set of encoded signals includes multiple signal segments, which are input one-to-one to the first decoding module and the multiple second decoding modules. The first decoding module and the second decoding modules are respectively connected to the encoding latch module, receive a second clock signal and their respective corresponding signal segments, and decode the received signal segments according to the second clock signal to obtain a first decoded signal and a second decoded signal. The first decoding latch module is connected to the first decoding module and the multiple second decoding modules, and activates the selected word line according to the second decoded signal. The address signal includes a first address signal representing the row address, and the data length of the first address signal represents the number of activated word lines. The solution of this application encodes the address signal transmitted to the encoding latch module to obtain a first set of encoded signals. Then, the signal segments from the first set of encoded signals corresponding to those in the first decoding module and multiple second decoding modules are transmitted to the first and second decoding modules respectively for decoding to obtain the corresponding decoded signals. The obtained decoded signals are then transmitted to the first decoding latch module to enable the selected word lines. The data length of the first address signal, which represents the row address in the address signals, represents the number of enabled word lines. This solution improves the adjustability of the number of word lines, simplifies the circuitry, and increases the decoding speed.

[0104] Example 3

[0105] Figure 10 is a structural example of the static random access memory of this application. As shown in Figure 10, the memory includes word line decoding circuitry as in any of the previous examples.

[0106] Specifically, in conjunction with the aforementioned scheme, the memory includes the word line decoding circuit provided in the aforementioned embodiments. The encoding latch module 11 receives the address signal and clock signal from the controller, and in response to the clock signal, encodes the received address signal, outputting a first encoded signal. The first encoded signal is used for subsequent row address decoding; the first encoded signal corresponds to multiple encoded signal segments, each corresponding one-to-one with the first decoding module 12 and multiple second decoding modules 13. The first decoding module 12 is connected to the encoding latch module 11, receives the clock signal and the corresponding signal segment, and decodes the received encoded signal segment according to the clock signal to obtain the first decoded signal; in this example, the signal segment input to the first decoding module 12 is a two-bit signal, which is decoded to generate a four-bit decoded signal. The second decoding module 13 is connected to the encoding latch module 11, receives the encoded signal of the corresponding signal segment generated by the encoding latch module 11, and decodes it to obtain the second decoded signal. The first decoding module 12 and multiple second decoding modules 13 are connected to the first decoding latch module 14. The first decoding latch module 14 activates the selected word line according to the second decoding signal. In practical applications, the number of word lines is represented by the signal length of the first address signal that represents the row address signal in the address signal.

[0107] In the static random access memory provided in this embodiment, the word line decoding circuit includes: an encoding latch module, a first decoding module, a plurality of second decoding modules, and the first decoding latch module; wherein the encoding latch module receives an address signal and a first clock signal, and in response to the first clock signal, encodes the address signal and outputs a first set of encoded signals; the first set of encoded signals represents a row encoding signal and its inverted signal; the first set of encoded signals includes a plurality of signal segments, which are input one-to-one to the first decoding module and the plurality of second decoding modules; the first decoding module and the second decoding modules are respectively connected to the encoding latch module, receive a second clock signal and their respective corresponding signal segments, and decode the received signal segments according to the second clock signal to obtain a first decoding signal and a second decoding signal; the first decoding latch module is connected to the first decoding module and the plurality of second decoding modules, and enables the selected word line according to the second decoding signal; the address signal includes a first address signal representing the row address, and the data length of the first address signal represents the number of enabled word lines. The solution of this application encodes the address signal transmitted to the encoding latch module to obtain a first set of encoded signals. Then, the signal segments from the first set of encoded signals corresponding to those in the first decoding module and multiple second decoding modules are transmitted to the first and second decoding modules respectively for decoding to obtain the corresponding decoded signals. The obtained decoded signals are then transmitted to the first decoding latch module to enable the selected word lines. The data length of the first address signal, which represents the row address in the address signals, represents the number of enabled word lines. This solution improves the adjustability of the number of word lines, simplifies the circuitry, and increases the decoding speed.

[0108] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only.

[0109] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope.

Claims

1. A word-line decoding circuit, characterized in that, include: Encoding latch module, first decoding module, multiple second decoding modules, and first decoding latch module; The encoding latch module receives an address signal and a first clock signal, and encodes the address signal in response to the first clock signal to output a first set of encoded signals. The first set of encoded signals represents a row encoding signal and its inverted signal. The first set of encoded signals includes multiple signal segments, which are input one-to-one to the first decoding module and multiple second decoding modules. The first decoding module is connected to the encoding latch module and receives a second clock signal and a corresponding signal segment. It decodes the received signal segment according to the second clock signal to obtain a first decoded signal. The second decoding module is connected to the encoding latch module and receives a corresponding signal segment. It decodes the received signal segment to obtain a second decoded signal. The first decoding latch module is connected to the first decoding module and the multiple second decoding modules and enables the selected word line according to the second decoded signal. The address signal includes a first address signal representing the row address, and the data length of the first address signal represents the number of enabled word lines.

2. The circuit according to claim 1, characterized in that, The circuit further includes: a redundancy start determination module, a third decoding module, and a second decoding latch module; the redundancy start determination module receives the first clock signal, the first address signal, a preset address reference signal, and a repair enable signal, and is used to determine whether to perform repair and output a selection signal and a redundancy signal based on the first address signal and the preset address reference signal when the repair enable signal is valid; the selection signal and the redundancy signal indicate whether repair is currently being performed, the preset address reference signal indicates the row address to be repaired, and the repair enable signal indicates whether the repair function is enabled; the first decoding module, Specifically, when the selected signal indicates that repair is not performed, the received signal segment is decoded according to the second clock signal to obtain a first decoded signal; the encoding latch module is also used to encode the address signal and output a second set of encoded signals, the second set of encoded signals representing a column encoded signal and its inverted signal; the third decoding module is connected to the encoding latch module and is used to decode according to the second set of encoded signals to obtain a third decoded signal; the second decoding latch module is connected to the third decoding module and is used to enable the selected redundant word line according to the third decoded signal when the redundant signal indicates that repair is performed.

3. The circuit according to claim 2, characterized in that, The redundancy start determination module includes a signal determination unit and a latching unit. The signal determination unit receives the first address signal, the preset address reference signal, and the repair enable signal, and compares the first address signal with the preset address reference signal to output a determination signal. If the first address signal and the preset address reference signal are the same, the determination signal indicates that repair is performed; if they are different, the determination signal indicates that repair is not performed. The latching unit is connected to the signal determination unit and responds to the first clock signal to output and latch the selection signal and the redundancy signal according to the determination signal. The selection signal has the opposite logic level to the redundancy signal.

4. The circuit according to claim 3, characterized in that, The signal determination unit includes an XNOR gate and a NAND gate; the XNOR gate receives the first address signal and the preset address reference signal, and the output of the XNOR gate is connected to the first input of the NAND gate; the second input of the NAND gate receives the repair enable signal; and the output of the NAND gate is connected to the input of the latch unit.

5. The circuit according to claim 4, characterized in that, The latch unit includes: a first tri-state gate, a first inverter, a second inverter, and a first transmission gate; the input of the first tri-state gate is connected to the output of the NAND gate, and the output of the first tri-state gate is connected to the input of the first inverter; the control terminal of the first tri-state gate receives the first clock signal; the output of the first inverter is connected to the input of the second inverter; the output of the second inverter is connected to one end of the first transmission gate, and the other end of the first transmission gate is connected to the input of the first inverter; the control terminal of the first transmission gate receives the first clock signal.

6. The circuit according to claim 1, characterized in that, The encoding latch module includes: multiple encoding latch units, each corresponding one-to-one with a bit signal of the address signal; each encoding latch unit includes: a second tri-state gate, a fourth inverter, a fifth inverter, and a second transmission gate; the second tri-state gate receives the address signal, its output is connected to the input of the fourth inverter, and its control terminal receives the first clock signal; the output of the fourth inverter is connected to the input of the fifth inverter; the output of the fifth inverter is connected to one end of the second transmission gate, the other end of the second transmission gate is connected to the input of the fourth inverter, and the control terminal of the second transmission gate receives the first clock signal.

7. The circuit according to claim 1, characterized in that, The first decoding module includes: a first decoding unit; the input terminal of the first decoding unit receives the second clock signal, each bit signal in the signal segment corresponding to the first decoding module in the first group of encoded signals, and the inverted signal of the bit signal; the output terminal of the first decoding unit is used to output the first decoded signal.

8. The circuit according to claim 1, characterized in that, The second decoding module includes: a second decoding unit; the input terminal of the second decoding unit receives each bit signal in the signal segment corresponding to the second decoding module in the first group of encoded signals and the inverted signal of the bit signal; the output terminal of the second decoding unit is used to output the second decoded signal.

9. The circuit according to claim 2, characterized in that, The third decoding module includes: a third decoding unit; the input terminal of the third decoding unit receives the second set of encoded signals and the inverted signal of the second set of encoded signals; the output terminal of the third decoding unit is used to output the third decoded signal.

10. The circuit according to claim 1, characterized in that, The first decoding latch module includes: a first decoding latch unit corresponding to each word line; the first decoding latch unit includes a third transmission gate, a first switch, and a first buffer; the input terminal of the third transmission gate receives the bit signal of the first decoding signal, the control terminal of the third transmission gate receives the bit signal of the second decoding signal, the output terminal of the third transmission gate is connected to the input terminal of the first buffer and one end of the first switch; the other end of the first switch is grounded, and the control terminal of the first switch receives the inverted signal of the bit signal of the second decoding signal; the output terminal of the first buffer is connected to the corresponding word line.

11. The circuit according to claim 2, characterized in that, The second decoding latch module includes: a second decoding latch unit corresponding to each redundant word line; the second decoding latch unit includes a second buffer, a third buffer, a fourth transmission gate, a second switch, and a fourth buffer; the input terminal of the second buffer receives the first clock signal, the output terminal of the second buffer is connected to the input terminal of the third buffer, and the control terminal of the third buffer receives the redundant signal; the output terminal of the third buffer is connected to the input terminal of the fourth transmission gate, the control terminal of the fourth transmission gate receives the bit signal of the third decoded signal, the output terminal of the fourth transmission gate, the input terminal of the fourth buffer, and one end of the second switch are connected; the other end of the second switch is grounded, and the control terminal of the second switch receives the inverted signal of the redundant signal; the output terminal of the fourth buffer is connected to the corresponding redundant word line.

12. The circuit according to any one of claims 1-11, characterized in that, The circuit further includes a switch module; the switch module is connected to the first decoding module, receives the selection signal and the first clock signal, and is used to transmit the second clock signal to the first decoding module when the selection signal indicates that repair is not performed.

13. The circuit according to claim 12, characterized in that, The switching module includes a fifth transmission gate and a third switch; one end of the fifth transmission gate receives the first clock signal, the other end of the fifth transmission gate is connected to one end of the third switch and serves as the output terminal of the switching module, and the control terminal of the fifth transmission gate receives the selection signal; the other end of the third switch is grounded, and the control terminal of the third switch receives the inverted signal of the selection signal.

14. A static random access memory, characterized in that, include: The word line decoding circuit as described in any one of claims 1-13.

Images