Data transmission method and apparatus, chip and electronic device

Abstract

The application discloses a data transmission method, device, chip and electronic equipment. The method comprises the following steps: reading a first descriptor stored in a local device; generating a first data queue management strategy based on the first descriptor; reading local data and caching the local data based on the first data queue management strategy; generating a first data write request based on the local data, and sending the first data write request and the local data to a second interface of a remote device through a first interface, so that the remote device performs the following processing: generating a second data queue management strategy based on packet header information of the local data, caching the local data based on the second data queue management strategy, generating a first data write signal according to a preset parameter, and writing the cached local data into the remote device according to the first data write signal. The preset parameter comprises any one of the following: a preset data amount, a preset data aging time and a preset data type. In this way, the efficiency of point-to-point data transmission can be improved.

Description

Data transmission methods, devices, chips and electronic equipment Technical Field

[0001] This application relates to the fields of communication and chip technology, and in particular to a data transmission device, method, chip and electronic device. Background Technology

[0002] In related technologies, Remote Direct Memory Access (RDMI) transfers data directly from the memory of one computer to another without the intervention of the operating systems of both computers. RDMI technology allows for high-throughput, low-latency network communication, making it particularly suitable for use in large-scale parallel computer clusters. However, RDMI relies on smart network interface card (NIC) hardware, and the mainstream supported protocols are InfiniBand, RoCE, and iWARP. These protocols all implement remote memory access via Ethernet, but their underlying protocols and hardware requirements differ, leading to limitations in end-device compatibility. When one end of the point-to-point transmission (such as an edge device or a regular server) is not equipped with a RDMI smart NIC, a RDMI connection cannot be established, requiring additional hardware upgrades for all nodes. Traditional network monitoring tools (such as Wireshark) have limited ability to parse RDMI protocols, necessitating the use of specialized tools (such as Mellanox VMA and perfquery) to troubleshoot problems. Summary of the Invention

[0003] This application proposes a data transmission method, apparatus, chip, and electronic device that can improve the efficiency of point-to-point data transmission.

[0004] To achieve the above objectives, the technical solution of this application is implemented as follows:

[0005] This application provides a data transmission method, the method including:

[0006] Read the first descriptor stored on the local device;

[0007] A first data queue management strategy is generated based on the first descriptor;

[0008] Read local data and cache the local data based on the first data queue management strategy;

[0009] A first data write request is generated based on the local data. The first data write request and the local data are sent to a second interface of a remote device through a first interface, so that the remote device performs the following processing: a second data queue management strategy is generated based on the packet header information of the local data; the local data is cached based on the second data queue management strategy; a first data write signal is generated according to preset parameters; and the cached local data is written to the remote device according to the first data write signal. The preset parameters include any one of the following: preset data volume, preset data aging time, and preset data type.

[0010] This application provides a data transmission device, the device comprising:

[0011] The memory access module is used to read the first descriptor stored on the local device.

[0012] The memory access module is used to generate a first data queue management strategy based on the first descriptor;

[0013] The data read / write module is used to read local data and cache the local data based on the first data queue management strategy.

[0014] The data read / write module is configured to generate a first data write request based on the local data, and send the first data write request and the local data to a second interface of a remote device through a first interface, so that the remote device performs the following processing: generating a second data queue management strategy based on the packet header information of the local data, caching the local data based on the second data queue management strategy, generating a first data write signal according to preset parameters, and writing the cached local data to the remote device according to the first data write signal, wherein the preset parameters include any one of the following: preset data volume, preset data aging time, and preset data type.

[0015] This application provides a chip, which includes a data transmission device as described in this application.

[0016] This application provides an electronic device, the electronic device comprising:

[0017] Memory is used to store executable instructions or computer programs.

[0018] The processor is configured to execute computer-executable instructions or computer programs stored in the memory to implement the data transmission method described in the embodiments of this application, or the processor includes the data transmission apparatus described in the embodiments of this application.

[0019] The embodiments of this application have the following beneficial effects:

[0020] By reading the first descriptor of the local device and generating a cache management strategy based on the descriptor, the local data to be transmitted is cached before transmission. The local data is then transmitted to the remote device via an interface. The local data output rhythm matches the interface transmission capacity, avoiding congestion or idleness in the transmission link. The header information of the local data received by the remote device contains relevant information about the local data. Cache management based on this information optimizes caching, reduces remote data processing overhead, and generates write signals using various preset parameters to determine whether to write. Large amounts of data can be broken down into different data granularities for writing. This adapts to the data characteristics of different applications, avoids bandwidth waste in different application scenarios, and maximizes the actual bandwidth utilization during data transmission. Attached Figure Description

[0021] Figure 1 is a schematic diagram of an application scenario of the data transmission method provided in the embodiments of this application;

[0022] Figure 2 is a schematic diagram of the structure of the electronic device provided in an embodiment of this application;

[0023] Figure 3 is a flowchart illustrating the data transmission method provided in an embodiment of this application;

[0024] Figure 4 is a schematic flowchart of the data transmission method provided in an embodiment of this application;

[0025] Figure 5 is a schematic diagram of the data transmission device provided in an embodiment of this application;

[0026] Figure 6 is a second structural schematic diagram of the data transmission device provided in an embodiment of this application;

[0027] Figure 7 is a schematic diagram of the structure of the data transmission device provided in the embodiment of this application.

[0028] It should be noted that the terms "first" and "second" mentioned above are only used to distinguish between different options and do not represent the degree of superiority or inferiority of the options or their priority in the implementation process. Detailed Implementation

[0029] In order to gain a more detailed understanding of the features and technical content of the embodiments of this application, the implementation of the embodiments of this application will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this application.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0031] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0032] It should also be noted that the terms "first," "second," and "third" used in the embodiments of this application are only used to distinguish similar objects and do not represent a specific order of objects. It is understood that "first," "second," and "third" can be interchanged in a specific order or sequence where permissible, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein. In the embodiments of this application, the terms "module" or "unit" refer to a computer program or part of a computer program with a predetermined function, which works together with other related parts to achieve a predetermined goal, and can be implemented wholly or partially using software, hardware (such as processing circuitry or memory), or a combination thereof. Similarly, a processor (or multiple processors or memory) can be used to implement one or more modules or units. Furthermore, each module or unit can be part of a larger module or unit that includes the functionality of that module or unit.

[0033] It should be noted that the data collection and processing in this application should strictly comply with the requirements of relevant laws and regulations, obtain the informed consent or separate consent of the personal information subject, and carry out subsequent data use and processing within the scope of laws and regulations and the authorization of the personal information subject.

[0034] To facilitate understanding of the technical solutions of the embodiments of this application, the relevant terms and technologies of the embodiments of this application are described below. The following related technologies are optional solutions and can be combined with the technical solutions of the embodiments of this application in any way, and they all fall within the protection scope of the embodiments of this application.

[0035] 1) Remote Direct Memory Access (RDMA): This is a direct memory access technology that transfers data directly from the memory of one computer to another without the intervention of the operating systems of both computers. This allows for high-throughput, low-latency network communication, making it particularly suitable for use in large-scale parallel computer clusters.

[0036] 2) Central Processing Unit (CPU) Core: This is the core chip in the middle of the central processing unit (hereinafter referred to as CPU). It is made of single-crystal silicon and is used to complete all calculations, store commands, process data, etc. It is the core of digital processing.

[0037] 3) Collective Communication: This is a data transmission and interaction mode for multi-node groups. It is characterized by multiple communication entities (such as servers, terminals, and sensors) working together around a unified goal to complete the distribution, aggregation, exchange, or computation of data.

[0038] 4) Sub-channel: This is a concept in the design of fifth-generation Double Data Rate Synchronous Dynamic Random Access Memory (DDR5), mainly used to solve the problem of matching data transfer bandwidth with CPU cache line size. Each sub-channel has a bandwidth of 32 bits, and two sub-channels can be combined to form a 64-bit data transfer channel.

[0039] 5) Chip (DIE): Also known as a die, it is the core physical unit of a semiconductor chip. It refers to a miniature semiconductor block formed on a silicon wafer through wafer manufacturing processes (such as photolithography, etching, and doping) that contains complete circuit functions (such as computing units, storage units, and logic control units). It is the smallest entity that enables the chip to perform its functions.

[0040] 6) System Direct Memory Access (SDMA): In computer systems, embedded chips, or server architectures, SDMA is a core technology that enables high-speed data transfer between different hardware components within a system. This is driven by a hardware module (direct memory access controller) and requires no direct involvement from the central processing unit (CPU / MCU). These hardware components include peripherals, memory, on-chip networks (NOCs), and remote nodes. The essence of SDMA is to offload repetitive, high-volume data transfer tasks from the CPU to dedicated hardware, preventing the CPU from getting bogged down in inefficient data copying and thus improving the overall system throughput and real-time performance.

[0041] 7) Peripheral Component Interconnect Express (PCIE): This is a serial computer bus technology designed to replace traditional Peripheral Component Interconnect (PCI) and Accelerated Graphics Port (AGP) interfaces, unifying the connection standard for internal computer devices. It is primarily used for high-speed data transmission from hardware such as graphics cards and storage devices. PCIE has become the mainstream interface standard for graphics cards and is also applied to chipset interconnects, server modularization, and other fields.

[0042] 8) Network-On-Chip (NoC): This is a communication method for System-on-a-Chip (SoC). As a key component of multi-core technology, it achieves concurrent communication through distributed routing nodes and time-division multiplexing links, replacing the traditional bus architecture to solve scalability and performance bottlenecks. NoC architectures are divided into Electronic On-Chip Networks (ENoC) based on electronic technology and Optical On-Chip Networks (ONoC) based on optical technology, employing a globally asynchronous and locally synchronous clock mechanism to reduce power consumption. NoC bandwidth is two orders of magnitude higher than bus architecture, with dynamic power consumption accounting for less than 40%, supporting scenarios such as multi-core processors and AI accelerators.

[0043] In related technologies, Remote Direct Memory Access (RDM) transfers data directly from the memory of one computer to another without the intervention of the operating systems of both computers. RDM technology allows for high-throughput, low-latency network communication, making it particularly suitable for use in large-scale parallel computer clusters. It changes the role of the central processing unit (CPU) in traditional network transmission, significantly reducing the CPU's load and optimizing its resource allocation efficiency. However, RDM relies on smart network interface card (NIC) hardware, supporting mainstream protocols such as InfiniBand, RoCE, and iWARP. These protocols all implement remote memory access via Ethernet, but their underlying protocols and hardware requirements differ, leading to limitations in end-device compatibility. When one end of the point-to-point transmission (such as an edge device or a regular server) is not equipped with a RDM smart NIC, a RDM connection cannot be established, requiring additional hardware upgrades for all nodes, resulting in poor flexibility. Traditional network monitoring tools (such as Wireshark) have limited ability to parse RDM protocols, necessitating the use of specialized tools (such as Mellanox VMA and perfquery) to troubleshoot problems.

[0044] Based on this, embodiments of this application provide a data transmission method, a data transmission device, an electronic device, a computer-readable storage medium, and a computer program product, which can improve the efficiency of point-to-point data transmission.

[0045] The following describes exemplary applications of the electronic devices provided in the embodiments of this application. These electronic devices can be implemented as terminal devices, such as laptops, tablets, desktop computers, set-top boxes, smart TVs, in-vehicle terminals, smartwatches, and other various types of terminals, or as servers. The following will describe exemplary applications when the electronic devices are implemented as terminal devices or servers.

[0046] Referring to Figure 1, which is a schematic diagram of the application mode of the data transmission method provided in the embodiments of this application; for example, Figure 1 involves terminal device 102, network 103 and terminal device 104. Terminal device 104 is connected to terminal device 102 through network 103, which can be a wide area network or a local area network, or a combination of both.

[0047] For example, terminal device 104 acts as the local device and terminal device 102 acts as the remote device. Terminal device 104 calls the data transmission method provided in the embodiments of this application to read local data and send the local data to terminal device 102, which acts as the remote device, via the network; or terminal device 104 calls the data transmission method provided in the embodiments of this application to send a data request to terminal device 102, which acts as the remote device, to obtain remote data sent by the remote device and write the remote data into the memory of terminal device 104.

[0048] Referring to Figure 2, which is a schematic diagram of the structure of an electronic device provided in an embodiment of this application, the electronic device may be the terminal device 104 in Figure 1. The terminal device 104 shown in Figure 2 includes at least one processor 410, a memory 450, at least one network interface 420, and a user interface 430. The various components in the terminal device 104 are coupled together through a bus system 440. It is understood that the bus system 440 is used to realize the connection and communication between these components. In addition to a data bus, the bus system 440 also includes a power bus, a control bus, and a status signal bus. However, for clarity, all buses are labeled as bus system 440 in Figure 2.

[0049] Processor 410 can be an integrated circuit chip with signal processing capabilities, such as a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among them, the general-purpose processor can be a microprocessor or any conventional processor, etc.

[0050] User interface 430 includes one or more output devices 431 that enable the presentation of media content, including one or more speakers and / or one or more visual displays. User interface 430 also includes one or more input devices 432, including user interface components that facilitate user input, such as a keyboard, mouse, microphone, touch screen display, camera, other input buttons and controls.

[0051] The memory 450 may be removable, non-removable, or a combination thereof. Exemplary hardware devices include solid-state storage, hard disk drives, optical disk drives, etc. The memory 450 may optionally include one or more storage devices physically located away from the processor 410.

[0052] The memory 450 may include volatile memory or non-volatile memory, or both. The non-volatile memory may be read-only memory (ROM), and the volatile memory may be random access memory (RAM). The memory 450 described in this application embodiment is intended to include any suitable type of memory.

[0053] In some embodiments, memory 450 is capable of storing data to support various operations, examples of which include programs, modules, and data structures or subsets or supersets thereof, as illustrated below.

[0054] Operating system 451 includes system programs for handling various basic system services and performing hardware-related tasks, such as the framework layer, core library layer, driver layer, etc., for implementing various basic business functions and handling hardware-based tasks;

[0055] The network communication module 452 is used to reach other electronic devices via one or more (wired or wireless) network interfaces 420, exemplary network interfaces 420 including: Bluetooth, WiFi, and Universal Serial Bus (USB), etc.

[0056] Presentation module 453 is configured to enable the presentation of information (e.g., a user interface for operating peripheral devices and displaying content and information) via one or more output devices 431 associated with user interface 430 (e.g., a display screen, a speaker, etc.).

[0057] The input processing module 454 is used to detect and translate one or more user inputs or interactions from one or more input devices 432.

[0058] In some embodiments, the apparatus provided in this application can be implemented in software. FIG2 shows a data transmission device 455 stored in memory 450, which can be software in the form of programs and plug-ins, including the following software modules: memory access module 4551 and data read / write module 4552. These modules are logical, so they can be arbitrarily combined or further divided according to the functions they implement. The functions of each module will be described below.

[0059] In other embodiments, the data transmission device provided in this application can be implemented in hardware. As an example, the data transmission device provided in this application can be a processor in the form of a hardware decoding processor, which is programmed to execute the data transmission method provided in this application. For example, the processor in the form of a hardware decoding processor can be one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), or other electronic components.

[0060] The data transmission method provided in this application will be described in conjunction with exemplary applications and implementations of the terminal devices provided in the embodiments of this application. The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0061] The data transmission method provided in the embodiments of this application will be described below. As mentioned above, the electronic device implementing the data transmission method of the embodiments of this application can be a terminal device or a server, or a combination of both. Therefore, the executing entity of each step will not be described again below.

[0062] It should be noted that the data transmission examples below are illustrated using the case where both the remote device and the local device are terminal devices. Based on the understanding of the following text, those skilled in the art can apply the data transmission method provided in the embodiments of this application to the processing of data transmission for other types of electronic devices, such as between a server and a terminal device, or between servers.

[0063] Referring to Figure 3, which is a flowchart illustrating the data transmission method provided in an embodiment of this application, the steps shown in Figure 3 will be explained in conjunction with the steps illustrated in Figure 3. The entity executing the steps in Figure 3 is the terminal device 104 in Figure 1.

[0064] In step 301, the first descriptor stored in the local device is read.

[0065] For example, the data transmission method provided in this application embodiment is applied in point-to-point transmission. The following description takes terminal device 102 as the local device. The descriptor is used to describe the metadata structure of the data transmission task, including key information such as data buffer address, length, operation type, and completion status. The descriptor is stored in the memory of the local device.

[0066] To facilitate understanding, the data transmission device configured in the terminal device 104 will be explained. Referring to Figure 5, which is a schematic diagram of the data transmission device provided in an embodiment of this application, the data transmission device 500 includes: a high-performance computing center module 501, a register 502, an on-chip network 503, a system direct memory access module 504, and a data interface 505. The remote device is also equipped with the same data transmission device 500 to realize data transmission between the local device and the remote device. Taking Figure 5 as an example, in the scenario where the local device reads its own data and sends it to the remote device so that the remote device can write the local data, the first descriptor is stored in the register 502.

[0067] In some embodiments, step 301 can be implemented in the following ways: generating a data interface read descriptor signal for the local register, wherein the register is used to store descriptors; reading descriptor information from the register based on the data interface read descriptor signal; parsing the descriptor information to obtain a first descriptor, wherein the parameters represented by the first descriptor include: the source address, the destination address, and the data length of the local data to be read.

[0068] For example, the data interface read descriptor signal is a hardware-level control signal used to trigger a descriptor read operation. The descriptor information stored in the register includes: an address pointer or control information for the descriptor queue. The address pointer of the descriptor queue is used to enable fast hardware access to descriptors. The descriptor information is parsed to obtain a first descriptor. The first descriptor represents at least one of the following parameters: the source address, the destination address, and the data length of the local data to be read. The source address represents the physical location of the local data in memory / storage. The destination address refers to the storage location of the local data on the remote device. The data length represents the number of bytes of local data to be read and can be used to define the corresponding cache space for the local data and the corresponding storage space on the remote device.

[0069] For example, referring to Figure 6, Figure 6 is a second structural schematic diagram of the data transmission device provided in an embodiment of this application. Figure 6 is a schematic diagram showing that the data transmission device (local chip 610 and remote chip 620) in Figure 5 are respectively installed on the local device and the remote device. The local chip 610 includes: an on-chip network 611, system direct memory access modules 0 to 3, registers 0 to 3, high-performance computing (HPC) modules 0 to 4, and high-speed serial computer expansion bus interfaces 0 to 3.

[0070] The high-performance computing center configures the descriptor address register of this module through the on-chip network control interface (CTRL NOC). The descriptors are stored at addresses in Dynamic Random Access Memory (DRAM), and corresponding trigger signals are configured (the data interface read descriptor signal mentioned above). A maximum of 64 descriptor addresses can be configured. Upon receiving the descriptor address register trigger signal, the local initiator module selects a descriptor through polling. Based on the selected descriptor address, the local initiator module generates a read request command for the on-chip network data interface (DATA NOC) and sends it to the on-chip network data interface. The local initiator module waits for the read data returned by the on-chip network data interface and parses the detailed information contained in the descriptor (source address, destination address, data length, etc.) from the read data.

[0071] In this embodiment, by reading the descriptor, the data can be accurately located based on the source address in the descriptor, thus improving the local reading efficiency; by using the data length, the transmission boundary is clearly defined, ensuring data integrity and improving point-to-point transmission efficiency.

[0072] In step 302, a first data queue management strategy is generated based on the first descriptor.

[0073] For example, data queue management strategies include data enqueue strategies and data dequeue strategies. A data queue is a queue that temporarily buffers data or tasks to be transmitted. The source address, destination address, and data length represented by the first descriptor can be used to generate the corresponding enqueue or dequeue strategy.

[0074] In some embodiments, the first data queue management strategy includes: a data enqueue strategy and a data dequeue strategy; step 302 can be implemented in the following ways: generating the following data enqueue strategy based on the first descriptor: reading local data according to the source address; determining the integrity of local data according to the data length, and adding local data to the first data queue of local data when local data is complete; generating the following data dequeue strategy according to a preset data volume: extracting cached local data from the first data queue according to the preset data volume.

[0075] For example, during the generation of the data queue management policy, the corresponding policy has not yet been executed. Subsequent steps will be executed based on the generated first data queue management policy. Regarding the enqueue policy, assume: the local initiator module has read management modules for two on-chip network data interfaces. When the descriptor is valid and a read management module is idle, the descriptor executes the read management finite state machine (FSM) process; the finite state machine configures the single read data length based on the total data length of the descriptor. A read on-chip network data interface command is generated. Each read management module includes two sub-channels. When a sub-channel is idle, the generated read on-chip network data interface command is enqueued, and the sub-channel identifier (sub-channel ID) is recorded. Regarding the dequeue policy, when the read data corresponding to the read on-chip network data interface command returns, it is stored in the read data cache; the read data management finite state machine generates the AXI write command corresponding to the PCIe port based on the read data cache. When all generated AXI write responses for a single read of on-chip network data interface data return, the sub-channel with the corresponding ID is dequeued.

[0076] In step 303, local data is read and cached based on the first data queue management strategy.

[0077] For example, local data is read from the source address, and the integrity of local data is determined based on the data length according to the data enqueue strategy in the first data queue management strategy. When local data is complete, it is added to the local first data queue.

[0078] In some embodiments, reading local data in step 303 can be achieved by: generating an on-chip network data read signal for the local on-chip network; and reading local data based on the on-chip network data read signal and the on-chip network data interface.

[0079] For example, the on-chip network data read signal is a hardware-level control signal used to trigger local data read operations. Continuing with the example in Figure 5, the system direct memory access module 504 in Figure 5 includes an initiator module, an on-chip network control interface (CTRL NOC interface), an on-chip network data interface (DATA NOC interface), and a target module. The on-chip network data interface and on-chip network control interface are memory access modules used to complete on-chip network data reads or control processing. The on-chip network data interface reads local data from the local device's memory based on the on-chip network data read signal. The on-chip network data interface is an internal interface, such as a high-speed serial computer expansion bus interface (PCIE5) x8 interface, supporting a 4096-bit width.

[0080] For example, the read management finite state machine generates a new on-chip network data interface read command corresponding to the local data, based on the total length of data read from the descriptor, in a single data read scenario where both sub-channels are idle. The data length maintained by the read management finite state machine is subtracted from the sub-data length of the data being read after each on-chip network data interface read command is sent. If the maintained data length is non-zero, it continues to wait for the next on-chip network data interface read command; if the maintained data length is zero, it indicates that the on-chip network data interface read command required by the descriptor has been completed.

[0081] In step 304, a first data write request is generated based on the local data, and the first data write request and the local data are sent to the second interface of the remote device through the first interface, so that the remote device performs the following processing: a second data queue management strategy is generated based on the packet header information of the local data, the local data is cached based on the second data queue management strategy, a first data write signal is generated according to preset parameters, and the cached local data is written to the remote device according to the first data write signal.

[0082] Here, the preset parameters include any of the following: preset data volume, preset data aging time, and preset data type.

[0083] For example, the first data write request is sent to a remote device to instruct the remote device to write received data into its memory. The first data write request carries control instructions to request that specific data be written to a target location. The first interface can be the local device's Advanced eXtensible Interface (AXI) interface, and the second interface is the remote device's AXI interface, which supports a 512-bit width. Both the first and second interfaces are external interfaces of the device; data conversion between the PCIe5 x8 interface and the AXI interface is performed before the local data is sent.

[0084] The packet header is a metadata fragment appended to the block of raw data (local or remote data in this embodiment). The header includes data description fields (e.g., data length, data type (e.g., command / file / stream data)) and identification fields (e.g., device identifier of the local device, device identifier of the remote device). The data description field represents the information or content of the transmitted data, and the identification field represents the identity of the data sender and the identity of the data receiver. In the scenario where the local device reads data written by the remote device, the device identifier of the local device is the sender's identity, and the device identifier of the remote device is the receiver's identity.

[0085] In some embodiments, the second data queue management strategy includes: a data enqueue strategy and a data dequeue strategy. The second data queue management strategy is generated based on the packet header information of the local data, which can be implemented in the following ways: parsing the packet header information of the local data to obtain the data length and target address of the local data; generating the following data enqueue strategy: determining the integrity of the local data based on the data length, and adding the local data to the remote second data queue when the local data is complete, wherein the data in the second data queue is empty before adding the local data, or the address of the data in the second data queue is continuous with the address of the local data before adding the local data; generating the following data dequeue strategy based on a preset data volume: extracting cached local data from the first data queue according to the preset data volume, and storing the extracted local data at the target address.

[0086] For example, the target address is the address in the remote device's memory used to write local data. The data length can be referred to above and will not be repeated here. Regarding the enqueue strategy, for example, the read management finite state machine module will generate a header with descriptor information (data length, etc.) and write it to the remote end through the on-chip network data interface. When the remote target module receives the header information, it processes the address of the new descriptor. When the remote target module receives input data through the PCIe AXI port, it enqueues the data according to the continuous mode or an empty queue. That is, if the new address is continuous with the address of a certain queue, it continues to be enqueued in that queue; if the continuous mode is not satisfied, it determines that the local data will be stored in an empty queue.

[0087] In some embodiments, generating a first data write signal according to preset parameters and writing the cached local data to the remote device according to the first data write signal can be achieved in the following ways:

[0088] Method (1) When the preset parameter is a preset data amount, when the data amount in the data queue reaches the preset data amount, the first data write signal is generated, the local data in the data queue is dequeued according to the first data write signal, and the dequeued local data is written into the target address of the remote device.

[0089] For example, the preset data volume is used to represent the granularity of data dequeued in the data queue. The preset data volume can be set according to the actual application requirements. For example, when the total amount of data enqueued in the queue reaches the preset data volume (16K / 8K, etc.), the queue will not allow enqueueing and will start the dequeueing process.

[0090] In this embodiment, batch dequeueing is performed by setting a preset data volume. On the one hand, multiple small batches of data are merged into one batch processing, reducing the number of hardware operations and saving bandwidth and energy consumption. On the other hand, triggering dequeueing and writing by setting a preset data volume can fully adapt to the hardware characteristics of the storage and improve the overall data writing speed.

[0091] Method (2) When the preset parameter is the preset data aging time, when the duration of the cached local data in the data queue is less than the preset data aging time, at least one first data write signal is generated, the cached local data is dequeued according to the first data write signal, and the dequeued local data is written into the target address of the remote device.

[0092] For example, the preset data aging time refers to the maximum retention threshold set for local data in the cache. It represents the maximum allowed time (e.g., 50ms, 1s) from when data enters the cache queue of the remote device until it must be dequeued and written to the target storage location. The preset data aging time is used to prevent data from remaining in the cache indefinitely through time constraints, ensuring data timeliness. In response to the generation of at least one first data write signal within the preset data aging time, the cached local data is dequeued according to the first data write signal. For example, when the queue enters the enqueue process, the aging counter starts counting. If the counter reaches the configured threshold, the queue stops enqueuing and enters the dequeue process.

[0093] In this embodiment, the aging time ensures that cached data is dequeued and written within a set time, thereby improving data transmission efficiency and write efficiency.

[0094] Method (3) When the preset parameter is packet tail information, when the data added to the data queue includes the packet tail information, the enqueueing is stopped and the first data write signal is generated. According to the first data write signal, the local data in the data queue is dequeued and the dequeued local data is written to the target address of the remote device.

[0095] For example, the default data type is packet header information. When data added to the data queue includes the packet tail information, queuing stops. Based on the packet tail information, it can be determined that the local data packet in the data queue is a complete data packet. A first data write signal is generated, and the local data in the data queue is dequeued according to the first data write signal. The dequeued local data is then written to the target address of the remote device. The packet header information is set at the beginning of the data packet, and the packet tail information is set at the end of the data packet. If a data queue contains both the packet header information and the packet tail information of a data packet, it indicates that the data packet is complete in the data queue, and the complete local data packet is written to the target address of the remote device.

[0096] In this embodiment, by performing dequeueing and writing when both packet header and packet tail information are present, it is ensured that the local data stored at the target address of the remote device is complete, and data can be written in batches in units of data packets, thereby improving the efficiency of data transmission and data writing.

[0097] In some embodiments, in the application scenario of reading data from a remote device and writing it to a local device, the following processes are performed: receiving a second descriptor, generating a second data write request based on the second descriptor; sending the second data write request to the remote device, so that the remote device performs the following processes: reading remote data, caching the remote data based on a first data queue management strategy, and sending the remote data to a first interface through a second interface; generating a second data queue management strategy based on the packet header information of the remote data, caching the remote data based on the second data queue management strategy, generating a second data write signal according to preset parameters, and writing the cached remote data to the local device according to the second data write signal.

[0098] For example, the application scenarios of reading data from a remote device and writing it to the local device are inverses of those of reading data from the local device and writing it to a remote device. The indications of the second descriptor and the first descriptor are inverses of each other. The information for reading data from a remote device and writing it to the local device is obtained based on the second descriptor. When the local device detects a need to read data from a remote device, it executes the process of generating a second data write request based on the second descriptor. The second data write request carries control instructions for requesting remote data and the device identifier of the local device. The principle of the remote device reading remote data is the same as the principle of the local device reading local data, and the principle of the local device writing remote data is the same as the principle of the remote device writing local data. Please refer to the above; they will not be repeated here. For example, the local initiator module's finite state machine, when resolving the received descriptor information as reading from the remote end and writing to the local end, generates AXI read commands sequentially based on the starting address and data length in the descriptor and sends them to the remote end through the PCIe port. The remote target module generates an on-chip network data interface read command from the received AXI read commands. When the remote target module receives the read data from the on-chip network data interface, it stores it in the read data buffer. Simultaneously, it generates AXI read data and returns it to the local end via the PCIe port. The local initiator module receives the AXI read data and stores it in the read data buffer. It also generates an on-chip network data interface write command and write data.

[0099] In this embodiment, by reading the first descriptor of the local device and generating a cache management strategy based on the descriptor, the read local data to be transmitted is cached before data transmission. The local data is then transmitted to the remote device via an interface. The local data output rhythm matches the interface transmission capacity, avoiding congestion or idleness in the transmission link. The header information of the local data received by the remote device contains relevant information about the local data. Cache management based on this information optimizes caching, reduces remote data processing overhead, and generates write signals using various preset parameters to determine whether to write. This allows large amounts of data to be split into different data granularities for writing. This adapts to the data characteristics of different applications, avoids bandwidth waste in different application scenarios, and maximizes the actual bandwidth utilization during data transmission.

[0100] The following will describe an exemplary application of the data transmission method of this application in a practical application scenario.

[0101] In the field of Collective Communication, data transmission can be handled in the following ways: point-to-point data transmission using Remote Direct Memory Access (RDA) bypasses the central processing unit (CPU) core and is zero-copy memory access. However, RDA requires smart network interface card (NIC) hardware. Supported mainstream protocols include InfiniBand, RoCE, and iWARP (all three protocols implement remote memory access via Ethernet, but their underlying protocols and hardware requirements differ). NVLink uses a point-to-point structure and serial transmission for connections between the CPU and the graphics processing unit (GPU), and can also be used for interconnections between multiple GPUs. The fifth-generation NVLink has a single-channel bandwidth of 100GB / s, with a single Blackwell chip supporting 18 channels, but requires NVIDIA GPU hardware support. Generations 1-3 of NVLink use Non-Return-to-Zero (NRZ) modulation, while generations 4-5 use Pulse Amplitude Modulation 4 (PAM4) modulation.

[0102] In related technologies, remote direct memory access solutions rely on dedicated smart network cards to bypass the CPU, leading to increased costs; achieving zero-copy requires designing special protocols (InfiniBand / RoCE / iWARP), increasing compatibility and deployment complexity; and stable transmission necessitates a lossless, low-latency network environment, further limiting application scenarios. NVLink suffers from incompatibility with GPUs from other manufacturers, such as AMD and Intel, and cannot be directly supported. For non-GPU heterogeneous hardware such as Neural Processing Units (NPUs) and Field-Programmable Gate Arrays (FPGAs) within a node, communication via NVLink is impossible. Instead, the relatively inefficient Fast Peripheral Interconnect standard protocol must be used, with the CPU acting as an intermediary, which limits the collaborative efficiency between heterogeneous hardware to some extent.

[0103] This application provides a data transmission method that, based on the Quick Peripheral Interconnect Standard Protocol Interface (QPI), enables point-to-point data transmission via system direct memory access. This bypasses limitations of remote direct memory access and NVLink, while also meeting the data transmission requirements within a clustered communication node and supporting on-chip network interface protocols.

[0104] For ease of understanding, the following describes a data transmission device used to implement the data transmission method provided in the embodiments of this application. The data transmission device can be installed in the terminal device 104, which serves as the local device. Referring to FIG5, FIG5 is a schematic diagram of the structure of the data transmission device provided in the embodiments of this application. The data transmission device 500 includes: a high-performance computing center module 501, a register 502, an on-chip network 503, a system direct memory access module 504, and a data interface 505. The remote device is also provided with the same data transmission device 500 to realize data transmission between the local device and the remote device.

[0105] Referring to Figure 6, Figure 6 is a second structural schematic diagram of the data transmission device provided in an embodiment of this application. Figure 6 is a schematic diagram showing the data transmission device (local chip 610 and remote chip 620) in Figure 5 respectively installed on the local device and the remote device. The local chip 610 includes: an on-chip network 611, system direct memory access modules 0 to 3, registers 0 to 3, high-performance computing (HPC) modules 0 to 4, and high-speed serial computer expansion bus interfaces 0 to 3. The registers can be DRAM registers used to store address descriptors. Each system direct memory access module includes: an initiator module, an on-chip network control interface (CTRL NOC interface), an on-chip network data interface (DATA NOC interface), and a target module. The high-speed serial computer expansion bus interface can be a PCIE5 x8 system interface, supporting non-return-to-zero modulation (NRZ). The system direct memory access module has external interfaces, such as the Advanced eXtensible Interface (AXI), which can perform conversion between PCIe5 and AXI.

[0106] The remote chip 620 includes an on-chip network 621, system direct memory access modules 0 to 3, registers 0 to 3, high-performance computing center modules 0 to 4, and high-speed serial computer expansion bus interfaces 0 to 3. The differential line between the local chip 610 and the remote chip 620 is used for data transmission. The local chip 610 and the remote chip 620 have the same structure and function; the local chip 610 will be used as an example for explanation. The high-performance computing center at the data transmission (local to remote, or remote to local) request initiating end configures and starts the system direct memory access descriptor address register (DAR) through the on-chip network control interface. The system direct memory access module generates a read request for the on-chip network data interface based on the descriptor address register and parses the source address, destination address, data length, read / write type, and other information required for this data transfer based on the returned data.

[0107] In the System Direct Memory Access (SDRAM) module of the 610 chip, the on-chip network data interface and on-chip network control interface are memory access modules used to complete on-chip network data reading or control processing. The SDRAM module also includes a data read / write module, which can be an advanced extensible interface. The data read / write module is used for conversion between the SDRAM module and the PCIe 5 x8 AXI interface, with a data width of 512 bits.

[0108] The initiator module is used for the direct memory access controller, as well as for local descriptor acquisition and parsing. In a read-to-write-to-remote scenario, the initiator module is used for generating read commands and buffering read data for the local on-chip network interface; it is also used for generating packet headers and write commands for the remote AXI interface. In a read-to-remote-write-to-local scenario, the initiator module is used for generating packet headers and read commands for the remote AXI interface, buffering read data; and it is also used for generating write commands for the local on-chip network interface. The target module is used for passively responding to bus requests. In a read-to-remote scenario, the target module is used for parsing packet headers, buffering and scheduling write data for the remote AXI interface; it is also used for generating write commands for the local on-chip network interface, etc. In a read-to-remote-write-to-local scenario, the target module is used for parsing packet headers and reading commands and scheduling for the remote AXI interface; it is also used for generating read commands for the local on-chip network interface, buffering read data, etc.

[0109] In some embodiments, the read / write granularity of a single channel of the local chip 610 is configurable, for example: 8KB, 4KB, 2KB. The external interface is fixed at 512 bits wide, while the on-chip network data interface within the internal interface is 4096 bits wide. To maximize bandwidth utilization, the read / write granularity of the on-chip network data interface is configurable. The read granularity is configurable at 8KB / 4KB / 2KB, meaning that a single on-chip network data interface read request can send 4096*16, 4096*8, or 4096*4 granularities. The returned read data is fixed at 512 bits wide and sent to the PCIe5 x8 interface, improving the utilization of the on-chip network data interface bus. The write granularity is configurable at 8KB / 4KB / 2KB, meaning that a single on-chip network data interface write request can collect multiple 512-bit wide PCIe5 x8 interface write data in granularities of 4096*16, 4096*8, or 4096*4, and generate one on-chip network data interface write request to send, thereby improving the utilization of the on-chip network data interface bus.

[0110] Referring to Figure 4, which is a second schematic flowchart of the data transmission method provided in an embodiment of this application, the terminal device 104 in Figure 1 will be used as the execution subject for explanation.

[0111] In step 401, a first data read request is generated based on the descriptor information.

[0112] For example, the first data read request is a data read request in a scenario where the local end writes to the remote end. The system direct memory access module generates a local on-chip network data interface read request (the first data read request) based on the descriptor information in the register.

[0113] In step 402, packet header information is sent to the remote device so that the remote device can parse the packet header information.

[0114] For example, the packet header information is sent to the remote device, which receives it through the PCIe 5 x8 interface. The remote device parses the header information to obtain the data's metadata, such as the total data length, sequence number, checksum, and target processing module. The total data length can be used to determine how many bytes of packet body data need to be received subsequently.

[0115] In step 403, local data is read based on the first data read request, and the local data is sent to the second interface of the remote device through the first interface so that the remote device can receive the local data.

[0116] For example, the first interface refers to the PCIe 5 x8 interface of the local chip, and the second interface of the remote device is the PCIe 5 x8 interface of the remote chip. The local chip reads data from its memory via its on-chip network data interface (ISP) and retrieves the local data through the ISP's ISP ...

[0117] For example, when local data is transmitted to a remote device, the data transmission length may be a long packet or a short packet (less than the smallest segmentation granularity). To enable direct memory access management of the remote system from receiving PCIe5 x8 interface read / write requests to generating on-chip network data interface read / write requests, a flexible and configurable data dequeue strategy is set: data is dequeued according to data granularity, data is dequeued according to a preset aging time, and data is dequeued according to packet header and footer.

[0118] When data is dequeued at the data granularity level, the system direct memory access module (DMI) can dequeue the data and generate the corresponding on-chip network data interface (ISP) read or write request after receiving a PCIe5 x8 request that meets the granularity of the ISP. The PCIe5 x8 read or write request is generated based on the descriptor information in the register. When data is dequeued according to a preset aging time, the DMI module can dequeue the data and generate the corresponding ISP read or write request after receiving a preset number of PCIe5 x8 read or write requests within the set aging time. When data is dequeued according to packet header and trailer information, the DMI module can dequeue the data and generate the corresponding ISP read or write request upon recognizing that the PCIe5 x8 read or write request contains packet header and trailer information.

[0119] In step 404, a second data read request is generated based on the descriptor information.

[0120] For example, the second data read request is a data read request in a scenario where the remote end is read and the local end is written. The system direct memory access module of the local chip generates a read request (the second data read request) based on the descriptor information.

[0121] In step 405, a second data read request is sent to the second interface of the remote device, so that the remote device reads the remote data based on the second data read request and sends the remote data to the first interface through the second interface.

[0122] For example, the local chip sends a read request (second data read request) to the PCIe5 x8 interface corresponding to the remote system's direct memory access module through the first interface. The remote device's system direct memory access module generates an on-chip network data interface read request according to a preset data amount. After waiting for the on-chip network data interface to return the read data, it sends the data to the local device's PCIe5 x8 interface (first interface) according to the preset data amount.

[0123] In step 406, a first data write request is generated based on the pre-configured data volume, and the remote data is stored in memory based on the first data write request.

[0124] For example, when the system direct memory access module of the local device receives data from the PCIe5 x8 interface, it generates an on-chip network data interface write request according to the preset data amount. After waiting for the on-chip network data interface to return all the remote data, it generates a corresponding interrupt signal to inform the micro control unit that the system direct memory access is complete.

[0125] Referring to Figure 7, Figure 7 is a schematic diagram of the data transmission device provided in the embodiment of this application. Figure 7 is used to characterize the data flow of the local chip and the remote chip in the scenario of reading from the local end and writing to the remote end in Figure 6. (1) The high-performance computing center module of the local chip configures the system direct memory access internal register (the descriptor is located in the DRAM address) through the on-chip network control interface bus and wakes up the system direct memory access module to work. (2) The initiator module of the system direct memory access module of the local chip can be the direct memory access controller. The direct memory access controller combines the descriptor information in the above register to generate on-chip network data interface read descriptor related signals and waits for the descriptor content fed back from the local memory controller to the local memory, and parses the specific content of the descriptor (source address, destination address, data length, etc.). (3) The initiator module of the system direct memory access module of the local chip performs data enqueue management information according to the descriptor content, and generates data dequeue management information according to the configured granularity. (4) The initiator module of the system direct memory access module of the local chip generates the relevant signals of the local on-chip network data interface read interface and caches the returned on-chip network data interface read data. (5) The initiator module of the system direct memory access module of the local chip generates the write command of the remote AXI interface according to the returned on-chip network data interface read data. The write command expresses the write address, data length and data content of the local data to be written. (6) The target module of the system direct memory access module of the remote chip completes the enqueue management according to the received packet header information (cache the data into the data queue according to the preset data enqueue order and data granularity). At the same time, it completes the cache management according to the received AXI interface write data. Cache management includes: recording the physical address of the data in the cache; releasing the occupied cache space after the data is retrieved and processed; pausing data reception when the cache utilization rate is close to full capacity. (7) The target module of the system direct memory access module of the remote chip generates the write interface signal of the remote on-chip network data interface according to the configured dequeue granularity. The write interface signal is the electrical signal that implements the write command on the physical layer. (8) When the target module of the system direct memory access of the remote chip completes all the data in the packet header, it generates an interrupt message of the remote on-chip network control interface to the remote high-performance computing center module to indicate that the data transmission is complete.

[0126] The data transmission method provided in this application has the following effects: (1) A single die (DIE) supports up to 4 system direct memory access transmissions. Each system direct memory access architecture supports two sub-channels. Each system direct memory access architecture supports a theoretical bandwidth of 32GB / s. It can meet the high bandwidth requirements of data-intensive scenarios such as training large models of artificial intelligence technology (such as large model parameter transfer) and high-performance computing (such as fluid dynamics simulation). These scenarios require continuous and high-speed data transmission between memory and computing units (such as GPU / CPU cores). In the case of dual sub-channels, the two operate in parallel without interference. For example, one sub-channel is responsible for reading the original data from memory, while the other sub-channel simultaneously writes the calculation results back to memory, further improving the actual data transmission efficiency. (2) The transmission read and write granularity of each channel supports configurable 8KB, 4KB, and 2KB granularity. Appropriate data segmentation granularity can be selected according to application requirements to improve bandwidth utilization. It adapts to the data characteristics of different applications, avoids bandwidth waste in different application scenarios, and maximizes the actual bandwidth utilization. (3) Supports a 4096-bit wide on-chip network protocol interface; ultra-high interconnect bandwidth, matching the performance of direct memory access and computing units. (4) Each system direct memory access architecture in a single die (DIE) supports up to 8 high-performance computing centers (HPCs) simultaneously initiating 64 transmission requests; improves the concurrent processing capability of direct memory access, avoids waiting caused by multiple computing units competing for direct memory access resources, and maximizes the utilization of computing units. (5) Supports flexible dequeue strategies for a single transmission: supports according to data granularity, according to configurable aging time, according to packet header and packet tail, etc. Allows direct memory access transmission scheduling to adapt to the latency and throughput requirements of different applications, avoiding the limitations of a single scheduling strategy.

[0127] The following description continues to illustrate the exemplary structure of the data transmission device 455 provided in the embodiments of this application as a software module. In some embodiments, as shown in FIG2, the software module stored in the data transmission device 455 in the memory 450 may include:

[0128] The memory access module 4551 is used to read a first descriptor stored in the local device; the memory access module 4551 is used to generate a first data queue management policy based on the first descriptor; the data read / write module 4552 is used to read local data and cache the local data based on the first data queue management policy; the data read / write module 4552 is used to generate a first data write request based on the local data, and send the first data write request and the local data to a second interface of the remote device through a first interface, so that the remote device performs the following processing: generating a second data queue management policy based on the packet header information of the local data, caching the local data based on the second data queue management policy, generating a first data write signal according to preset parameters, and writing the cached local data to the remote device according to the first data write signal, wherein the preset parameters include any one of the following: preset data volume, preset data aging time, and preset data type.

[0129] In some embodiments, the memory access module 4551 is configured to generate a data interface read descriptor signal for a local register, wherein the register is used to store descriptors; read descriptor information from the register based on the data interface read descriptor signal; parse the descriptor information to obtain a first descriptor, wherein the parameters represented by the first descriptor include: the source address, the destination address, and the data length of the local data to be read.

[0130] In some embodiments, the first data queue management strategy includes: a data enqueue strategy and a data dequeue strategy; the memory access module 4551 is configured to generate the following data enqueue strategy based on the first descriptor: read local data according to the source address; determine the integrity of the local data according to the data length, and add the local data to the first data queue of the local end when the local data is complete; generate the following data dequeue strategy according to a preset data volume: extract the cached local data from the first data queue according to the preset data volume.

[0131] In some embodiments, the data read / write module 4552 is used to generate an on-chip network data read signal for the local on-chip network; and read the local data based on the on-chip network data read signal and the on-chip network data interface.

[0132] In some embodiments, the second data queue management strategy includes: a data enqueue strategy and a data dequeue strategy; a data read / write module 4552 is used to parse the header information of the local data to obtain the data length and target address of the local data; generate the following data enqueue strategy: determine the integrity of the local data based on the data length, and add the local data to the remote second data queue when the local data is complete, wherein the data in the second data queue is empty before adding the local data, or the address of the data in the second data queue is continuous with the address of the local data before adding the local data; generate the following data dequeue strategy based on a preset data volume: extract the cached local data from the first data queue based on the preset data volume, and store the extracted local data at the target address.

[0133] In some embodiments, the data read / write module 4552 is configured to: when the preset parameter is the preset data volume, generate a first data write signal when the data volume in the data queue reaches the preset data volume; dequeue the local data in the data queue according to the first data write signal; and write the dequeueed local data to the target address of the remote device; when the preset parameter is the preset data aging time, generate at least one first data write signal when the duration of the cached local data in the data queue is less than the preset data aging time; dequeue the cached local data according to the first data write signal; and write the dequeueed local data to the target address of the remote device; when the preset parameter is packet tail information, stop enqueuing when the data added to the data queue includes the packet tail information; generate the first data write signal; dequeue the local data in the data queue according to the first data write signal; and write the dequeueed local data to the target address of the remote device.

[0134] In some embodiments, the data read / write module 4552 is configured to receive a second descriptor, generate a second data write request based on the second descriptor, and send the second data write request to a remote device so that the remote device performs the following processes: reading remote data, caching the remote data based on the first data queue management policy, and sending the remote data to the first interface through the second interface; generating a second data queue management policy based on the packet header information of the remote data, caching the remote data based on the second data queue management policy, generating a second data write signal according to the preset parameters, and writing the cached remote data to the local device according to the second data write signal.

[0135] In another embodiment of this application, a chip is provided, which may include: the data transmission device as described in any of the foregoing embodiments, or the data transmission device method as described in any of the foregoing embodiments.

[0136] In another embodiment of this application, an electronic device is provided, the electronic device including a processor, wherein the processor includes: a data transmission device as described in any of the foregoing embodiments, or a data transmission device method as described in any of the foregoing embodiments.

[0137] In summary, the above embodiments have provided a detailed explanation of the specific implementation of the aforementioned embodiments. It can be seen that the technical solutions of the aforementioned embodiments, by reading the first descriptor of the local device and generating a cache management strategy based on the descriptor, cache the local data to be transmitted before data transmission. The local data is then transmitted to the remote device via an interface, ensuring that the local data output rhythm matches the interface transmission capacity, avoiding congestion or idleness in the transmission link. The header information of the local data received by the remote device contains relevant information about the local data. Cache management based on this information optimizes caching, reduces remote data processing overhead, and generates write signals using various preset parameters to determine whether to write. This allows large amounts of data to be split into different data granularities for writing. This adapts to the data characteristics of different applications, avoids bandwidth waste in different application scenarios, and maximizes the actual bandwidth utilization during data transmission.

[0138] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed in this application can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0139] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the above-described apparatus and unit can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0140] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0141] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0142] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. If the functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium.

[0143] It should be noted that, in this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0144] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0145] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0146] The features disclosed in the several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0147] The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0148] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A data transmission method, characterized in that, The method includes: reading a first descriptor stored on the local device; generating a first data queue management policy based on the first descriptor; reading local data and caching the local data based on the first data queue management policy; generating a first data write request based on the local data, and sending the first data write request and the local data to a second interface of a remote device through a first interface, so that the remote device performs the following processing: generating a second data queue management policy based on the packet header information of the local data, caching the local data based on the second data queue management policy, generating a first data write signal according to preset parameters, and writing the cached local data to the remote device according to the first data write signal; wherein, the preset parameters include any one of the following: preset data volume, preset data aging time, and preset data type; when the preset parameter is the preset data aging time, when the cached local data is in the preset data aging time, ... preset data aging time, and generating a first data write signal according to preset parameters, and generating a first data write signal according to preset parameters, and generating a first data write signal according to preset parameters, and generating a first data write signal according to preset parameters, and generating a first data write signal according to preset parameters, and generating a first data write signal according to preset parameters, and generating a first data write signal according to preset parameters, and generating a second data write signal according to preset parameters, and generating a second data write signal according to preset parameters, and generating a second data write signal according to preset parameters, and generating a second data write signal according to preset parameters, If the duration in the queue is less than the preset data aging time, at least one first data write signal is generated. Based on the first data write signal, the cached local data is dequeued, and the dequeued local data is written to the target address of the remote device. If the preset parameter is the preset data volume, when the data volume in the data queue reaches the preset data volume, the first data write signal is generated. Based on the first data write signal, the local data in the data queue is dequeued, and the dequeued local data is written to the target address of the remote device. If the preset parameter is packet tail information, when the data added to the data queue includes the packet tail information, enqueuing stops, and the first data write signal is generated. Based on the first data write signal, the local data in the data queue is dequeued, and the dequeued local data is written to the target address of the remote device.

2. The method according to claim 1, characterized in that, The step of reading the first descriptor stored in the local device includes: generating a data interface read descriptor signal for the local register, wherein the register is used to store descriptors; reading descriptor information from the register based on the data interface read descriptor signal; parsing the descriptor information to obtain the first descriptor, wherein the parameters represented by the first descriptor include: the source address, the destination address, and the data length of the local data to be read.

3. The method according to claim 2, characterized in that, The first data queue management strategy includes: a data enqueue strategy and a data dequeue strategy; the step of generating the first data queue management strategy based on the first descriptor includes: generating the following data enqueue strategy based on the first descriptor: reading local data according to the source address; determining the integrity of the local data according to the data length, and adding the local data to the first data queue of the local end when the local data is complete; generating the following data dequeue strategy according to a preset data volume: extracting the cached local data from the first data queue according to the preset data volume.

4. The method according to claim 1, characterized in that, The process of reading local data includes: generating an on-chip network data read signal for the local on-chip network; and reading the local data based on the on-chip network data read signal and the on-chip network data interface.

5. The method according to claim 1, characterized in that, The second data queue management strategy includes: a data enqueue strategy and a data dequeue strategy; the step of generating the second data queue management strategy based on the packet header information of the local data includes: parsing the packet header information of the local data to obtain the data length and target address of the local data; generating the following data enqueue strategy: determining the integrity of the local data based on the data length, and adding the local data to the remote second data queue when the local data is complete, wherein the data in the second data queue is empty before adding the local data, or the address of the data in the second data queue is continuous with the address of the local data before adding the local data; generating the following data dequeue strategy based on a preset data volume: extracting the cached local data from the first data queue according to the preset data volume, and storing the extracted local data at the target address.

6. The method according to claim 1, characterized in that, The method further includes: receiving a second descriptor, generating a second data write request based on the second descriptor; sending the second data write request to a remote device, so that the remote device performs the following processing: reading remote data, caching the remote data based on the first data queue management policy, and sending the remote data to the first interface through the second interface; generating a second data queue management policy based on the packet header information of the remote data, caching the remote data based on the second data queue management policy, generating a second data write signal according to the preset parameters, and writing the cached remote data to the local device according to the second data write signal.

7. A data transmission device, characterized in that, The device includes: a memory access module for reading a first descriptor stored on the local device; the memory access module for generating a first data queue management policy based on the first descriptor; a data read / write module for reading local data and caching the local data based on the first data queue management policy; and the data read / write module for generating a first data write request based on the local data, sending the first data write request and the local data to a second interface of a remote device through a first interface, so that the remote device performs the following processing: generating a second data queue management policy based on the packet header information of the local data, caching the local data based on the second data queue management policy, generating a first data write signal according to preset parameters, and writing the cached local data to the remote device according to the first data write signal, wherein the preset parameters include any one of the following: preset data volume, preset data aging time, and preset data type; when the preset parameters are the preset data volume, the data aging time is specified in the original text. When the aging time is specified, if the duration of the cached local data in the data queue is less than the preset data aging time, at least one first data write signal is generated. The cached local data is then dequeued according to the first data write signal, and the dequeued local data is written to the target address of the remote device. When the preset parameter is the preset data volume, if the data volume in the data queue reaches the preset data volume, the first data write signal is generated. The local data in the data queue is then dequeued according to the first data write signal, and the dequeued local data is written to the target address of the remote device. When the preset parameter is packet tail information, if the data added to the data queue includes the packet tail information, queuing is stopped, and the first data write signal is generated. The local data in the data queue is then dequeued according to the first data write signal, and the dequeued local data is written to the target address of the remote device.

8. A chip for data transmission, characterized in that, The chip includes: the data transmission device as described in claim 7.

9. An electronic device, characterized in that, The electronic device includes: a memory for storing computer-executable instructions or computer programs; and a processor for implementing the data transmission method according to any one of claims 1 to 6 when executing the computer-executable instructions or computer programs stored in the memory, or the processor includes the data transmission device according to claim 7.

Images