Image transmission system based on ZYNQ chip

Abstract

The invention provides an image transmission system based on a ZYNQ chip, a PS end is provided with a GVCP processing module and a DDR controller I which are connected with each other, and the DDR controller I is used for performing read-write operation on a DDR chip I; the PL end is provided with an AXIDMA IP core, an FIFO cache region I, a network processing module, a GVSP processing module, a DDR controller II and a data transmission module which are connected in sequence; the GVSP processing module is also communicated with the data transmission module; the DDR controller II is used for performing read-write operation on the DDR chip II; an FIFO (First In First Out) cache region II is also arranged between the network processing module and the AXIDMA IP core; according to the scheme, the GVCP is realized at the PS end, and the GVSP is realized at the PL end, so that the real-time performance of data transmission is improved; real-time control of multiple cameras and synchronous receiving and processing of data can be realized, and the transmission efficiency is high.

Description

Technical Field

[0001] This invention relates to the field of image transmission, and more specifically to an image transmission system based on a ZYNQ chip. Background Technology

[0002] GigE Vision is a communication protocol developed by AIA to enable high-speed image transmission via Gigabit Ethernet interfaces in the field of machine vision. This standard is based on the UDP protocol, but differs from ordinary network data packets in its application layer protocols. The application layer protocols employ GVCP (GigE Vision Control Protocol) and GVSP (GigE Vision Streaming Protocol) to configure the camera and transmit data streams, respectively. The software implementation of the image acquisition system is based on these two protocols.

[0003] In the existing technology, image transmission schemes based on ZYNQ chips include the following two types:

[0004] Option 1: Both GVCP (GigE Vision Control Protocol) and GVSP (GigE Vision Streaming Protocol) are implemented by the PL side. This option can only realize device lookup and some register configuration functions; it has missing functions and is difficult to debug devices.

[0005] Option 2: Both GVCP (GigE Vision Control Protocol) and GVSP (GigE Vision Streaming Protocol) are implemented on the PS side, and image data is then transmitted to the PL side via VDMA. However, VDMA requires buffering at least one frame, which takes 10.3ms for a 1080P image at a 200MHz transmission clock, resulting in poor real-time performance. Furthermore, the PS side only has one interface, allowing data transmission from only one camera at a time, leading to low transmission efficiency. Summary of the Invention

[0006] To address the aforementioned technical issues, this invention provides an image transmission system based on a ZYNQ chip. This solution implements GVCP at the PS end and GVSP at the PL end, reducing the VDMA transmission step and improving real-time transmission performance. Furthermore, the PL end has abundant I / O resources, enabling real-time control and synchronous data reception and processing of multiple GigE Vision cameras, significantly improving transmission efficiency.

[0007] The technical solution is as follows:

[0008] An image transmission system based on a ZYNQ chip, wherein the ZYNQ chip includes a PS end and a PL end that communicate with each other, the PS end is provided with a connected GVCP processing module and a DDR controller I, and the DDR controller I is used to perform read and write operations on the DDR chip I;

[0009] The PL terminal is provided with an AXI_DMA IP core, a FIFO buffer area I, a network processing module, a GVSP processing module, a DDR controller II, and a data transmission module connected in sequence; the GVSP processing module also communicates with the data transmission module; the DDR controller II is used to perform read and write operations on the DDR chip II; a FIFO buffer area II is also provided between the network processing module and the AXI_DMA IP core;

[0010] Among them, the AXI_DMA IP core communicates with the GVCP processing module and the DDR controller I respectively;

[0011] The ARM processor in the PS terminal reads the camera configuration file and transmits it to the GVCP processing module. The GVCP processing module encapsulates the camera configuration instructions in the camera configuration file according to the GVCP protocol to form a GVCP configuration instruction package, and stores the GVCP configuration instruction package in the DDR chip I through the DDR controller I. After storage, the GVCP processing module sends a transmission instruction to the AXI_DMAIP core.

[0012] After receiving the transmission command, the AXI_DMA IP core retrieves the GVCP configuration command packet from the DDR chip I through the transmission interface and DDR controller I, and caches the GVCP configuration command packet in the FIFO buffer area I.

[0013] The network processing module reads the GVCP configuration command packet from the FIFO buffer area I and performs data format conversion according to the AXI-Stream protocol. The converted GVCP configuration command packet is then processed by the MAC layer and sent to the camera.

[0014] The camera responds to the GVCP configuration command packet, configures the camera and acquires images according to the configuration information in the GVCP configuration command packet, encapsulates the response information into a GVCP response data packet, encapsulates the image data into a GVSP data packet, and sends them back to the network processing module respectively.

[0015] The network processing module performs CRC check and identification on the GVCP response data packet and the GVSP data packet respectively:

[0016] The identified GVCP response data packets are converted according to the AXI protocol, and the converted data is cached in FIFO buffer area II. The data in FIFO buffer area II is read in batches through the AXI_DMA IP core and stored in DDR chip I through the transmission interface and DDR controller I. The GVCP processing module reads the GVCP response data packets from DDR chip I through DDR controller I, and determines the time difference between the reading time of the GVCP response data packets and the transmission time of the GVCP configuration command packets. If the time difference exceeds the threshold, the transmission command is resent to the AXI_DMA IP core.

[0017] The network processing module identifies GVSP data packets and sends them to the GVSP processing module. The GVSP processing module performs packet loss checks on the GVSP data packets. If there is no packet loss, the image data in the GVSP data packets is stored in the DDR chip II through the DDR controller II. If there is packet loss, a packet loss retransmission request is sent to the camera. After the camera retransmits the lost data packets, the image data of the lost data packets is stored in the DDR chip II through the DDR controller II.

[0018] Once all image data is stored in the DDR chip II, the GVSP processing module sends a notification signal to the data transmission module. After receiving the notification signal, the data transmission module uses the DDR controller II to read the image data from the DDR chip II and sends it to the external device, thus completing the image transmission.

[0019] Furthermore, the network processing module includes a MAC layer processing module I, a packet filtering module, and a UDP payload processing module connected in sequence; it also includes a protocol conversion module I, a protocol conversion module II, a UDP sending module I, and a packet forwarding module; the UDP payload processing module is connected to the GVSP processing module; the protocol conversion module I is connected between the FIFO buffer area I and the packet forwarding module, and the packet forwarding module is also connected to the MAC layer processing module I and the UDP sending module I respectively; the UDP sending module I is connected to the GVSP processing module; the MAC layer processing module I communicates with the camera; the protocol conversion module II is connected between the packet filtering module and the FIFO buffer area II;

[0020] The MAC layer processing module I is used to receive GVCP response data packets and GVSP data packets, and to perform CRC checks on the GVCP response data packets and GVSP data packets respectively, to remove data packets with incorrect checks, and to forward data packets with correct checks to the packet filtering module.

[0021] The packet filtering module is used to extract the five-tuple information from the data packets and identify the data packets as either GVCP response data packets or GVSP data packets based on the extracted information; the GVCP response data packets are sent to the protocol conversion module II and the GVSP data packets are sent to the UDP payload processing module.

[0022] The protocol conversion module II is used to convert GVCP response data packets according to the AXI protocol and cache the converted data in FIFO buffer area II;

[0023] The UDP payload processing module removes the network header from the GVSP data packets and sends the valid UDP payload data to the GVSP processing module.

[0024] The UDP sending module I is used to receive the packet loss retransmission request sent by the GVSP processing module. The packet loss retransmission request contains the ID information of the lost data packet. A network packet header is added to the packet loss retransmission request to form a GVSP request data packet, which is then forwarded to the data packet forwarding module.

[0025] The protocol conversion module I is used to read GVCP configuration instruction packets from FIFO buffer area I and convert the data format according to the AXI-Stream protocol, and send the format-converted GVCP configuration instruction packets to the data packet forwarding module;

[0026] The packet forwarding module sends the GVCP configuration instruction packet and the GVSP request packet to the MAC layer processing module in the order in which they are received.

[0027] The MAC layer processing module I adds a preamble and a frame delimiter to the received GVCP configuration instruction packet and GVSP request data packet, performs CRC verification, adds the verification result to the end of the packet, and then forwards it to the camera.

[0028] Furthermore, when the ZYNQ chip communicates with external devices via the PCIe interface, the data transmission module includes a connected DMA processing module and an XDMA IP core;

[0029] The DMA processing module is connected to the GVSP processing module and the DDR controller II respectively. It is used to receive the notification signal sent by the GVSP processing module, read the image data from the DDR chip II through the DDR controller II, and then encapsulate the image data according to the AXI4_Stream protocol.

[0030] The XDMA IP core reads image data from the DMA processing module and then forwards the image data to external devices in streaming mode to complete image transmission.

[0031] Furthermore, when the ZYNQ chip communicates with external devices via a network, the data transmission module includes a connected UDP sending module II and a MAC layer processing module II;

[0032] The UDP sending module II is connected to the GVSP processing module and the DDR controller II respectively. It is used to receive the notification signal sent by the GVSP processing module, read the image data from the DDR chip II through the DDR controller II, add a packet header to the image data to form an image data packet, and forward it to the MAC layer processing module II.

[0033] The MAC layer processing module II adds a preamble and frame delimiter to the received image data packet and performs CRC check. The check result is added to the end of the packet before being forwarded to the external device to complete the image transmission.

[0034] This solution has the following characteristics:

[0035] 1. Higher processing bandwidth: This system uses the PL terminal to implement GVSP, which can achieve gigabit full bandwidth data transmission.

[0036] 2. Lower latency: Compared to Solution 2 mentioned in the background technology, this solution shortens the data transmission path, reduces the VDMA transmission step, and improves the real-time performance of the transmission. For example, at a 200M transmission clock, VDMA buffering of one frame of 1080P image requires 10.3ms, which greatly increases the image transmission latency.

[0037] 3. Enhanced scalability: The abundant IO resources on the PL end enable real-time control and synchronous data reception and processing of multiple GigE Vision cameras. Attached Figure Description

[0038] Figure 1 This is a structural block diagram of the image transmission system (with the data transmission module being one form) in a specific implementation embodiment;

[0039] Figure 2 This is a structural block diagram of the image transmission system (the data transmission module is of another form) in a specific implementation. Detailed Implementation

[0040] The technical solution of the present invention will be described in detail below with reference to specific embodiments.

[0041] An image transmission system based on a ZYNQ chip, such as Figure 1 As shown, the ZYNQ chip includes a PS terminal and a PL terminal that communicate with each other. The PS terminal is equipped with a connected GVCP processing module and a DDR controller I. The DDR controller I is used to perform read and write operations on the DDR chip I.

[0042] The PL terminal is provided with an AXI_DMA IP core, a FIFO buffer area I, a network processing module, a GVSP processing module, a DDR controller II, and a data transmission module connected in sequence; the GVSP processing module also communicates with the data transmission module; the DDR controller II is used to perform read and write operations on the DDR chip II; a FIFO buffer area II is also provided between the network processing module and the AXI_DMA IP core;

[0043] Among them, the AXI_DMA IP core communicates with the GVCP processing module and the DDR controller I respectively;

[0044] In practice, the camera configuration file is transmitted in real time via a host computer or pre-stored in Flash or SSD.

[0045] The ARM processor in the PS terminal reads the camera configuration file and transmits it to the GVCP processing module. The GVCP processing module encapsulates the camera configuration instructions in the camera configuration file according to the GVCP protocol to form a GVCP configuration instruction package, and stores the GVCP configuration instruction package in the DDR chip I through the DDR controller I. After storage, the GVCP processing module sends a transmission instruction to the AXI_DMAIP core.

[0046] After receiving the transmission command, the AXI_DMA IP core retrieves the GVCP configuration command packet from the DDR chip I through the transmission interface (M_AXIS_MM2S interface) and the DDR controller I, and caches the GVCP configuration command packet in the FIFO buffer area I;

[0047] The network processing module reads the GVCP configuration command packet from the FIFO buffer area I and performs data format conversion according to the AXI-Stream protocol. The converted GVCP configuration command packet is then processed by the MAC layer and sent to the camera.

[0048] The camera responds to the GVCP configuration command packet, configures the camera and acquires images according to the configuration information in the GVCP configuration command packet, encapsulates the response information into a GVCP response data packet, encapsulates the image data into a GVSP data packet, and sends them back to the network processing module respectively.

[0049] Explanatoryly, the GVCP configuration command packet includes the Packet ID and Ack_ID, as well as configuration information (such as exposure time, gain, and resolution); the GVCP response packet includes the Packet ID and Ack_ID information corresponding to the GVCP configuration packet.

[0050] The network processing module performs CRC check and identification on the GVCP response data packet and the GVSP data packet respectively:

[0051] The identified GVCP response data packets are converted according to the AXI protocol, and the converted data is cached in FIFO buffer area II. The data in FIFO buffer area II is read in batches through the AXI_DMA IP core and stored in DDR chip I through the transmission interface (M_AXIS_MM2S interface) and DDR controller I. The GVCP processing module reads the GVCP response data packets from DDR chip I through DDR controller I, and determines the time difference between the reading time of the GVCP response data packets and the transmission time of the GVCP configuration command packets. If the time difference exceeds the threshold, the transmission command is resent to the AXI_DMA IP core (retransmission of GVCP configuration command packets).

[0052] The network processing module identifies GVSP data packets and sends them to the GVSP processing module. The GVSP processing module performs packet loss checks on the GVSP data packets. If no packet loss is found, the image data (payload data) in the GVSP data packets is stored in the DDR chip II via the DDR controller II. If packet loss is found, a packet loss retransmission request is sent to the camera. After the camera retransmits the lost data packets, the image data of the lost data packets is stored in the DDR chip II via the DDR controller II.

[0053] Once all image data is stored in the DDR chip II, the GVSP processing module sends a notification signal to the data transmission module. After receiving the notification signal, the data transmission module uses the DDR controller II to read the image data from the DDR chip II and sends it to the external device, thus completing the image transmission.

[0054] Explanatory: The GVSP processing module performs packet loss checks on GVSP packets by parsing the Block ID and Packet ID in the packet header. The GVSP processing module stores GVSP packets with different IDs in different DDR storage areas. In this embodiment, the external device is a CPU processor, GPU processor, etc.

[0055] More specifically, the network processing module includes a MAC layer processing module I, a packet filtering module, and a UDP payload processing module connected in sequence; it also includes a protocol conversion module I, a protocol conversion module II, a UDP sending module I, and a packet forwarding module; the UDP payload processing module is connected to the GVSP processing module; the protocol conversion module I is connected between the FIFO buffer area I and the packet forwarding module, and the packet forwarding module is also connected to the MAC layer processing module I and the UDP sending module I respectively; the UDP sending module I is connected to the GVSP processing module; the MAC layer processing module I communicates with the camera; the protocol conversion module II is connected between the packet filtering module and the FIFO buffer area II;

[0056] The MAC layer processing module I receives GVCP response data packets and GVSP data packets through the RGMII interface, performs CRC checks on the GVCP response data packets and GVSP data packets respectively, removes data packets with incorrect checks, and forwards data packets with correct checks to the packet filtering module.

[0057] The packet filtering module extracts five-tuple information from data packets and identifies them as either GVCP response packets or GVSP packets based on the extracted information. It then sends GVCP response packets to the protocol conversion module II and GVSP packets to the UDP payload processing module.

[0058] The 5-tuple information includes the protocol type, source IP address, destination IP address, source port number, and destination port number.

[0059] The protocol conversion module II is used to convert GVCP response data packets according to the AXI protocol and cache the converted data in FIFO buffer area II;

[0060] The UDP payload processing module removes the network header (UDP header, IP header, and MAC header) from the GVSP data packets and sends the valid UDP payload data to the GVSP processing module.

[0061] The UDP sending module I is used to receive the packet loss retransmission request sent by the GVSP processing module. The packet loss retransmission request contains the ID information of the lost data packet. A network packet header is added to the packet loss retransmission request to form a GVSP request data packet, which is then forwarded to the data packet forwarding module.

[0062] The network packet header includes the UDP header, IP header, and MAC header. The ID information for lost packets includes the Block ID (sequence number of the data block) and the Packet ID (indicating the sequence number of the packet within the current data block).

[0063] The protocol conversion module I is used to read GVCP configuration instruction packets from FIFO buffer area I and convert the data format according to the AXI-Stream protocol, and send the format-converted GVCP configuration instruction packets to the data packet forwarding module;

[0064] The packet forwarding module sends the GVCP configuration instruction packet and the GVSP request packet to the MAC layer processing module in the order in which they are received.

[0065] The MAC layer processing module I adds a preamble and a frame delimiter (SFD) to the received GVCP configuration instruction packet and GVSP request packet, respectively, performs CRC check, adds the check result to the end of the packet, and then forwards it to the camera through the RGMII interface.

[0066] In practical implementation, depending on the different communication methods between the ZYNQ chip and external devices, the data transmission module includes the following two forms:

[0067] Format 1:

[0068] When the ZYNQ chip communicates with external devices via the PCIe interface, such as Figure 1 The data transmission module includes a connected DMA processing module and an XDMA IP core;

[0069] The DMA processing module is connected to the GVSP processing module and the DDR controller II respectively. It is used to receive the notification signal sent by the GVSP processing module, read the image data from the DDR chip II through the DDR controller II, and then encapsulate the image data according to the AXI4_Stream protocol.

[0070] The XDMA IP core reads image data from the DMA processing module and then forwards the image data to external devices in streaming mode to complete image transmission.

[0071] Form Two:

[0072] When the ZYNQ chip communicates with external devices via a network, such as Figure 2 The data transmission module includes a connected UDP sending module II and a MAC layer processing module II;

[0073] The UDP sending module II is connected to the GVSP processing module and the DDR controller II respectively. It is used to receive the notification signal sent by the GVSP processing module, read the image data from the DDR chip II through the DDR controller II, add a packet header to the image data to form an image data packet, and forward it to the MAC layer processing module II.

[0074] The MAC layer processing module II adds a preamble and frame delimiter to the received image data packet and performs CRC check. The check result is added to the end of the packet, and then forwarded to the external device through the RGMII interface to complete the image transmission.

[0075] This system uses the PL terminal to implement GVSP, which can achieve gigabit full-bandwidth data transmission; it reduces the VDMA transmission step and improves the image transmission speed.

[0076] The abundant IO resources on the PL end enable real-time control and synchronous data reception and processing of multiple GigE Vision cameras.

[0077] The foregoing description of specific exemplary embodiments of the present invention is for illustrative and descriptive purposes. It is not intended to be exhaustive, nor to limit the invention to the precise forms disclosed; obviously, many changes and variations are possible in accordance with the foregoing teachings. The exemplary embodiments were chosen and described to explain the specific principles of the invention and its practical application, thereby enabling others skilled in the art to implement and utilize various exemplary embodiments of the invention, as well as their different alternatives and modifications. The scope of the invention is intended to be defined by the appended claims and their equivalents.

Claims

1. An image transmission system based on a ZYNQ chip, wherein the ZYNQ chip includes a PS terminal and a PL terminal that communicate with each other, characterized in that, The PS end is equipped with a connected GVCP processing module and DDR controller I. DDR controller I is used to read and write DDR chip I. The PL terminal is provided with an AXI_DMA IP core, a FIFO buffer area I, a network processing module, a GVSP processing module, a DDR controller II, and a data transmission module connected in sequence; the GVSP processing module also communicates with the data transmission module; the DDR controller II is used to perform read and write operations on the DDR chip II; a FIFO buffer area II is also provided between the network processing module and the AXI_DMA IP core; Among them, the AXI_DMA IP core communicates with the GVCP processing module and the DDR controller I respectively; The ARM processor in the PS terminal reads the camera configuration file and transmits it to the GVCP processing module. The GVCP processing module encapsulates the camera configuration instructions in the camera configuration file according to the GVCP protocol to form a GVCP configuration instruction package, and stores the GVCP configuration instruction package in the DDR chip I through the DDR controller I. After storage, the GVCP processing module sends a transmission instruction to the AXI_DMA IP core. After receiving the transmission command, the AXI_DMA IP core retrieves the GVCP configuration command packet from the DDR chip I through the transmission interface and DDR controller I, and caches the GVCP configuration command packet in the FIFO buffer area I. The network processing module reads the GVCP configuration command packet from the FIFO buffer area I and performs data format conversion according to the AXI-Stream protocol. The converted GVCP configuration command packet is then processed by the MAC layer and sent to the camera. The camera responds to the GVCP configuration command packet, configures the camera and acquires images according to the configuration information in the GVCP configuration command packet, encapsulates the response information into a GVCP response data packet, encapsulates the image data into a GVSP data packet, and sends them back to the network processing module respectively. The network processing module performs CRC check and identification on the GVCP response data packet and the GVSP data packet respectively: The identified GVCP response data packets are converted according to the AXI protocol, and the converted data is cached in FIFO buffer area II. The data in FIFO buffer area II is read in batches through the AXI_DMA IP core and stored in DDR chip I through the transmission interface and DDR controller I. The GVCP processing module reads the GVCP response data packets from DDR chip I through DDR controller I, and determines the time difference between the reading time of the GVCP response data packets and the transmission time of the GVCP configuration command packets. If the time difference exceeds the threshold, the transmission command is resent to the AXI_DMA IP core. The network processing module identifies GVSP data packets and sends them to the GVSP processing module. The GVSP processing module performs packet loss checks on the GVSP data packets. If there is no packet loss, the image data in the GVSP data packets is stored in the DDR chip II through the DDR controller II. If there is packet loss, a packet loss retransmission request is sent to the camera. After the camera retransmits the lost data packets, the image data of the lost data packets is stored in the DDR chip II through the DDR controller II. Once all image data is stored in the DDR chip II, the GVSP processing module sends a notification signal to the data transmission module. After receiving the notification signal, the data transmission module uses the DDR controller II to read the image data from the DDR chip II and sends it to the external device, thus completing the image transmission.

2. The image transmission system based on the ZYNQ chip as described in claim 1, characterized in that: The network processing module includes a MAC layer processing module I, a packet filtering module, and a UDP payload processing module connected in sequence; it also includes a protocol conversion module I, a protocol conversion module II, a UDP sending module I, and a data packet forwarding module; the UDP payload processing module is connected to the GVSP processing module; the protocol conversion module I is connected between the FIFO buffer area I and the data packet forwarding module, and the data packet forwarding module is also connected to the MAC layer processing module I and the UDP sending module I respectively; the UDP sending module I is connected to the GVSP processing module; the MAC layer processing module I communicates with the camera; The protocol conversion module II is connected between the packet filtering module and the FIFO buffer area II; The MAC layer processing module I is used to receive GVCP response data packets and GVSP data packets, and to perform CRC checks on the GVCP response data packets and GVSP data packets respectively, to remove data packets with incorrect checks, and to forward data packets with correct checks to the packet filtering module. The packet filtering module is used to extract the five-tuple information from the data packets and identify the data packets as either GVCP response data packets or GVSP data packets based on the extracted information; the GVCP response data packets are sent to the protocol conversion module II and the GVSP data packets are sent to the UDP payload processing module. The protocol conversion module II is used to convert GVCP response data packets according to the AXI protocol and cache the converted data in FIFO buffer area II; The UDP payload processing module removes the network header from the GVSP data packets and sends the valid UDP payload data to the GVSP processing module. The UDP sending module I is used to receive the packet loss retransmission request sent by the GVSP processing module. The packet loss retransmission request contains the ID information of the lost data packet. A network packet header is added to the packet loss retransmission request to form a GVSP request data packet, which is then forwarded to the data packet forwarding module. The protocol conversion module I is used to read GVCP configuration instruction packets from FIFO buffer area I and convert the data format according to the AXI-Stream protocol, and send the format-converted GVCP configuration instruction packets to the data packet forwarding module; The packet forwarding module sends the GVCP configuration instruction packet and the GVSP request packet to the MAC layer processing module in the order in which they are received. The MAC layer processing module I adds a preamble and a frame delimiter to the received GVCP configuration instruction packet and GVSP request data packet, performs CRC verification, adds the verification result to the end of the packet, and then forwards it to the camera.

3. The image transmission system based on the ZYNQ chip as described in claim 1, characterized in that: When the ZYNQ chip communicates with external devices via the PCIe interface, the data transmission module includes a connected DMA processing module and an XDMA IP core; The DMA processing module is connected to the GVSP processing module and the DDR controller II respectively. It is used to receive the notification signal sent by the GVSP processing module, read the image data from the DDR chip II through the DDR controller II, and then encapsulate the image data according to the AXI4_Stream protocol. The XDMA IP core reads image data from the DMA processing module and then forwards the image data to external devices in streaming mode to complete image transmission.

4. The image transmission system based on the ZYNQ chip as described in claim 1, characterized in that: When the ZYNQ chip communicates with external devices via a network, the data transmission module includes a connected UDP sending module II and a MAC layer processing module II; The UDP sending module II is connected to the GVSP processing module and the DDR controller II respectively. It is used to receive the notification signal sent by the GVSP processing module, read the image data from the DDR chip II through the DDR controller II, add a packet header to the image data to form an image data packet, and forward it to the MAC layer processing module II. The MAC layer processing module II adds a preamble and frame delimiter to the received image data packet and performs CRC check. The check result is added to the end of the packet before being forwarded to the external device to complete the image transmission.

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