A method for manufacturing a semiconductor structure and a semiconductor structure

Abstract

The present disclosure provides a semiconductor structure manufacturing method and a semiconductor structure. The semiconductor structure includes a substrate, and a connection region of the substrate includes vertically-alternating first insulating layers and semiconductor layers. Part of the semiconductor layers in the connection region is replaced by second insulating layers. A contact plug is formed through the first insulating layers, the second insulating layers, and the remaining semiconductor layers, and the contact plug extends to the corresponding second insulating layers with different extension depths. Part of the second insulating layers is removed by taking the remaining semiconductor layers as an etching stop layer, and a lateral space of the contact plug and an end of an array region exposed in the connection region is formed. A horizontal word line electrically coupled with the horizontal word line and the contact plug is formed in the lateral space, and the horizontal word line abuts against the remaining semiconductor layers. The semiconductor layers as the etching stop layer limit the size of the lateral space in the etching process, ensure the controllable size of the lateral space, and make the horizontal word line meet the expected shape, thereby reducing the parasitic capacitance and the additional power consumption.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor structure and the semiconductor structure itself. Background Technology

[0002] In a three-dimensional memory, storage cells are located in an array region, and word lines in the array region need to be connected to external circuits through a connection region.

[0003] In related technologies, the shape of the horizontal wires used for electrical coupling with word lines to external circuits in the connection area is difficult to control, and unwanted metal layers are easily generated during the manufacturing process. The parasitic capacitance generated between these metal layers affects the performance of the 3D memory. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] According to an embodiment of this disclosure, a method for fabricating a semiconductor structure is provided, comprising:

[0006] A substrate is provided, the substrate including horizontally adjacent array regions and connection regions, the connection regions including vertically alternating first insulating layers and semiconductor layers;

[0007] In the connection region, a portion of the semiconductor layer is replaced with a second insulating layer;

[0008] A contact plug is formed through the first insulating layer, the second insulating layer and the remaining semiconductor layer, the contact plug extending to the corresponding second insulating layer at different depths;

[0009] Using the remaining semiconductor layer as an etch stop layer, a portion of the second insulating layer is removed to form the ends of the horizontal word lines of the array region and the lateral space of the contact plug in the connection area;

[0010] Horizontal conductors are formed within the lateral space, electrically coupling the horizontal word lines and the contact plugs respectively, and the horizontal conductors also abut against the remaining semiconductor layer.

[0011] In some embodiments, the first insulating layer includes a silicon oxide layer and a silicon nitride layer surrounding the surface of the silicon oxide layer, with the bottom of the contact plug located on the silicon oxide layer.

[0012] In some embodiments, forming a contact plug through the first insulating layer, the second insulating layer, and the remaining semiconductor layer includes:

[0013] The first insulating layer, the second insulating layer, and the remaining semiconductor layer are etched downwards to form contact holes with different depths, the bottom of which is located on the surface of the silicon nitride layer in the first insulating layer;

[0014] Deposit insulating material within the contact hole;

[0015] Remove the insulating material at the bottom of the contact hole, as well as the material below the bottom of the contact hole, until the surface of the silicon oxide layer in the first insulating layer of the next layer is exposed, forming pad holes located in the corresponding second insulating layer. The remaining insulating material is located on the sidewall of the contact hole, forming a sidewall layer.

[0016] A pad is formed in the pad hole, the pad being located on the silicon oxide layer and surrounded by the second insulating layer;

[0017] The contact plug is formed within the contact hole, the bottom of the contact plug is located on the pad to extend through the pad to the corresponding second insulating layer, and the sidewall of the contact plug contacts the sidewall layer.

[0018] In some embodiments, the manufacturing method further includes:

[0019] A diffusion barrier layer is formed on the surface of the pad hole and the surface of the sidewall layer.

[0020] In some embodiments, the contact plug and the pad are an integral structure.

[0021] In some embodiments, the contact plugs are distributed on opposite sides of the horizontal conductor;

[0022] Among them, the bottom of the contact plug located on one of the opposite sides of the horizontal conductor is electrically coupled to the odd-numbered horizontal word lines;

[0023] The bottom of the contact plug located on the other side of the opposite sides of the horizontal conductor is electrically coupled to the even-numbered horizontal letter lines.

[0024] In some embodiments, the horizontal conductor is looped, and the contact plug is located on the outside of the loop of the horizontal conductor.

[0025] In some embodiments, providing the substrate includes:

[0026] Vertically alternating initial semiconductor layers and sacrificial semiconductor layers are formed on the array region and the connection region of the substrate;

[0027] The initial semiconductor layer and the sacrificial semiconductor layer of the array region are patterned, and vertically stacked memory cells are formed in the array region;

[0028] A first vertical opening is formed in the connection region, the first vertical opening penetrating the initial semiconductor layer and the sacrificial semiconductor layer;

[0029] The sacrificial semiconductor layer is etched laterally along the first vertical opening to form a lateral groove;

[0030] The initial semiconductor layer exposed by the lateral groove is thinned along the lateral groove, and the thinned initial semiconductor layer forms the semiconductor layer;

[0031] The first insulating layer is formed in the lateral groove, the first insulating layer covers the surface of the semiconductor layer, and the first insulating layer and the semiconductor layer alternate vertically.

[0032] In some embodiments, forming the first insulating layer in the lateral groove includes:

[0033] A silicon nitride layer is formed in the lateral groove, and the silicon nitride layer covers the surface of the semiconductor layer;

[0034] The remaining area of ​​the lateral groove is filled with a silicon oxide layer, which covers the surface of the silicon nitride layer.

[0035] A second aspect of this disclosure provides a semiconductor structure, comprising:

[0036] The substrate includes horizontally adjacent array regions and connection regions;

[0037] The connection area includes:

[0038] First insulating layer;

[0039] A composite layer comprising a connected second insulating layer and a semiconductor layer, wherein the first insulating layer and the composite layer alternate vertically.

[0040] The contact plug extends through the first insulating layer and the combined layer and into the corresponding second insulating layer in the combined layer;

[0041] A horizontal conductor electrically couples the horizontal word line of the array region to the contact plug, and the horizontal conductor also abuts against the semiconductor layer.

[0042] In some embodiments, the first insulating layer includes a silicon oxide layer and a silicon nitride layer surrounding the surface of the silicon oxide layer, with the bottom of the contact plug located on the silicon oxide layer.

[0043] In some embodiments, the semiconductor structure further includes a pad, one sidewall of which is connected to the horizontal conductor, and the remaining sidewalls of which are connected to a corresponding second insulating layer.

[0044] The pads are connected to the silicon oxide layer beneath the corresponding second insulating layer.

[0045] In some embodiments, the contact plug and the pad are integrally formed, and a sidewall layer is provided around the contact plug;

[0046] A diffusion barrier layer is provided on a portion of the outer surface of the integral structure formed by the contact plug and the solder pad.

[0047] In some embodiments, the contact plugs are distributed on opposite sides of the horizontal conductor, wherein,

[0048] The bottom of the contact plug located on one of the opposite sides of the horizontal conductor is electrically coupled to the odd-numbered horizontal letter lines.

[0049] The bottom of the contact plug located on the other side of the opposite sides of the horizontal conductor is electrically coupled to the even-numbered horizontal letter lines.

[0050] In some embodiments, the horizontal conductor is looped, and the contact plug is located on the outside of the loop of the horizontal conductor.

[0051] In the semiconductor structure fabrication method disclosed herein, the semiconductor layer is used as an etch stop layer. The lateral dimensions of the lateral space used to form the horizontal conductors are limited by the etch stop layer, ensuring the controllability of the shape and size of the lateral space and avoiding over-etching problems during the formation of the lateral space. Because the size of the lateral space is controllable, the formed horizontal conductors conform to the expected design shape, reducing parasitic capacitance and additional power consumption caused by excessively large horizontal conductor areas. This facilitates the establishment of efficient, low-parasitic, and low-power electrical coupling connections between the horizontal conductors and peripheral circuits via contact plugs.

[0052] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0053] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of these embodiments. In these drawings, similar reference numerals are used to denote similar elements. The drawings described below are some embodiments of the present disclosure, but not all embodiments. Other drawings will be readily available to those skilled in the art based on these drawings without inventive effort.

[0054] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment;

[0055] Figure 2 This is a schematic diagram of a substrate according to an exemplary embodiment;

[0056] Figure 3 This is a schematic diagram of a semiconductor structure after forming a first isolation structure and a second isolation structure in a substrate, according to an exemplary embodiment.

[0057] Figure 4 This is a schematic diagram of a semiconductor structure after forming a first vertical opening and removing the sacrificial semiconductor layer, according to an exemplary embodiment.

[0058] Figure 5 This is a schematic diagram of a semiconductor structure after thinning an initial semiconductor layer, according to an exemplary embodiment.

[0059] Figure 6 This is a schematic diagram of a semiconductor structure after forming a silicon nitride layer, according to an exemplary embodiment.

[0060] Figure 7 This is a schematic diagram illustrating a semiconductor structure after the formation of a silicon oxide layer, according to an exemplary embodiment.

[0061] Figure 8 yes Figure 7 A sectional view of section A-A';

[0062] Figure 9 This is a schematic diagram of the semiconductor structure after the removal of the first isolation structure in cross section A-A', according to an exemplary embodiment.

[0063] Figure 10 This is a schematic diagram of a semiconductor structure after the formation of a second insulating layer in cross section A-A', according to an exemplary embodiment.

[0064] Figure 11 This is a schematic diagram of a semiconductor structure after the shape of the second insulating layer has been adjusted, shown in section A-A' according to an exemplary embodiment;

[0065] Figure 12 This is a schematic diagram of the semiconductor structure after the formation of the third isolation structure in cross section A-A', according to an exemplary embodiment;

[0066] Figure 13 This is a schematic diagram of a semiconductor structure in section A-A' after the initial contact hole has been formed, according to an exemplary embodiment.

[0067] Figure 14This is a schematic diagram of a semiconductor structure after the formation of an isolation material layer in cross section A-A', according to an exemplary embodiment.

[0068] Figure 15 This is a schematic diagram of a semiconductor structure after the formation of a sidewall layer in section A-A', according to an exemplary embodiment.

[0069] Figure 16 This is a schematic diagram of a semiconductor structure in section A-A' after the formation of pad holes, according to an exemplary embodiment.

[0070] Figure 17 This is a schematic diagram of a semiconductor structure after the formation of contact plugs and pads in cross section A-A', according to an exemplary embodiment.

[0071] Figure 18 This is a schematic diagram of a semiconductor structure in section A-A' after the formation of a lateral space, according to an exemplary embodiment.

[0072] Figure 19 This is a schematic diagram of a semiconductor structure in section A-A' after the formation of horizontal wires, according to an exemplary embodiment.

[0073] Figure 20 This is a schematic diagram of the semiconductor structure after the formation of the fourth isolation structure in cross section A-A', according to an exemplary embodiment;

[0074] Figure 21 This is a three-dimensional schematic diagram of a semiconductor structure according to an exemplary embodiment;

[0075] Figure 22 This is a top view of a semiconductor structure according to an exemplary embodiment;

[0076] Figure 23 This is a schematic diagram of the semiconductor structure after the removal of the first isolation structure in cross section A-A', according to another exemplary embodiment;

[0077] Figure 24 This is a schematic diagram of the semiconductor structure after the removal of the first isolation structure in cross section A-A', according to yet another exemplary embodiment;

[0078] Figure 25 This is a schematic diagram of the semiconductor structure in section A-A' after the initial contact hole has been formed, according to another exemplary embodiment.

[0079] Figure label:

[0080] 100, Substrate; 100a, Connecting region; 100b, Array region;

[0081] 10. First insulating layer; 11. Silicon oxide layer; 12. Silicon nitride layer;

[0082] 20. Composite layer; 21. Semiconductor layer; 21'. Initial semiconductor layer; 22. Second insulating layer; 23. Lateral void;

[0083] 30. Sacrificial semiconductor layer;

[0084] 40. Contact plug;

[0085] 50', horizontal guide wire; 50', transverse space;

[0086] 60', Sidewall layer; 60', Isolation material layer;

[0087] 70, pad; 70', pad hole;

[0088] 80. Diffusion barrier layer;

[0089] 91. First vertical opening; 92. Lateral groove; 93. Contact hole; 93'. Initial contact hole; 94. Etched opening; 94a. First opening; 94b. Second opening; 94c. Third opening; 94d. Fourth opening; 94e. Fifth opening;

[0090] 101. First dielectric layer; 102. Second dielectric layer; 103. First isolation structure; 104. Second isolation structure; 105. Third isolation structure; 106. Fourth isolation structure;

[0091] 200, Horizontal word line; 201, End point; 300, Bit line; 400, Active region; 500, Memory cell. Detailed Implementation

[0092] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0093] To address the problems in related technologies, this disclosure provides a method for fabricating a semiconductor structure and a semiconductor structure, which will be described below in conjunction with... Figures 1 to 25 The technical solution disclosed herein will be explained and illustrated.

[0094] According to exemplary embodiments of this disclosure, such as Figure 1 As shown, this embodiment provides a method for fabricating a semiconductor structure, the method including the following steps:

[0095] Step S110: Provide a substrate, the substrate including horizontally adjacent array regions and connection regions, the connection regions including vertically alternating first insulating layer and semiconductor layer.

[0096] In this step, Figures 2 to 20 A substrate 100 for supporting a semiconductor structure is shown. The substrate 100 can be made of any of the following materials: monocrystalline silicon, polycrystalline silicon, amorphous silicon, germanium, silicon carbide, silicon germanide, germanium on insulator (GOI), or silicon on insulator (SOI).

[0097] See Figure 3 The substrate 100 includes an array region 100b and a connecting region 100a adjacent in the horizontal direction (i.e., the plane containing the x and y directions shown in the figure). In this embodiment, the horizontal direction is described using the x direction as an example. The array region 100b is used to form multiple horizontal word lines 200 extending in the horizontal direction (see [reference]). Figure 21 Connection area 100a is used to form an interconnection structure (including horizontal conductor 50 and contact plug 40, see [reference]). Figure 21 (This will be explained in detail later). The interconnect structure can be connected to multiple horizontal word lines 200 in the array region 100b. By controlling the interconnect structure in the connection region 100a, efficient and unified control of multiple horizontal word lines 200 in the array region 100b can be achieved.

[0098] It should be noted that only a partial area of ​​the substrate 100 is shown in this embodiment. For the entire substrate 100, the substrate 100 may include multiple array regions 100b and connection regions 100a alternately arranged along the x-direction. Simultaneously, multiple array regions 100b may be spaced apart along the y-direction, and multiple connection regions 100a may also be spaced apart along the y-direction. Each connection region 100a can be electrically coupled to at least one side of the array region 100b located in its x-direction, thereby achieving efficient and unified control of a large number of memory cells 500 in the array region 100b through the connection region 100a.

[0099] See Figure 2 , Figure 3 , Figure 7 and Figure 8 The connection region 100a of the substrate 100 includes vertical ( Figure 2The first insulating layer 10 and the semiconductor layer 21 are alternately arranged in the z-direction shown in the diagram. The first insulating layer 10 and the semiconductor layer 21 have different etching selectivity ratios for a specific etchant, thereby enabling selective removal of the semiconductor layer 21 and the first insulating layer 10 in subsequent steps. In one example, the material of the first insulating layer 10 includes silicon nitride, silicon oxynitride, or silicon carbide nitride, the material of the semiconductor layer 21 includes silicon, and the etchant can be any one of HF-based (such as HF and CH3OH gas), plasma (such as CHF3, CF4, O2, and He), or diluted hydrofluoric acid solution (DHF).

[0100] Step S120: Replace part of the semiconductor layer in the connection area with a second insulating layer.

[0101] In this step, such as Figures 8 to 12 As shown, a portion of the semiconductor layer 21 is replaced by a second insulating layer 22 to change the contour shape of the semiconductor layer 21, dividing the originally continuous semiconductor layer 21 into a composite layer 20 formed by connecting the remaining semiconductor layer 21 and the second insulating layer 22. The second insulating layer 22 can have a similar etching selectivity to a portion of the structure of the first insulating layer 10 (such as the silicon nitride layer 12 of the first insulating layer 10), facilitating the use of the same etchant for uniform removal in subsequent steps to form the lateral space 50'. This arrangement simplifies the process steps. The material of the second insulating layer 22 can be, for example, silicon nitride.

[0102] This step defines the shape and position of the remaining semiconductor layer 21 that will serve as the etch stop layer. Since the materials of the second insulating layer 22 and the semiconductor layer 21 have different etching selectivity, it is beneficial to form a lateral space 50' of a specific shape and size through selective etching, thus avoiding the problem of forming an additional metal layer due to excessive etching that causes the lateral space 50' to be too large.

[0103] In one example, see Figures 9 to 12 The semiconductor layer 21 can be partially replaced by the second insulating layer 22 in the following manner:

[0104] First, a portion of the semiconductor layer 21 is selectively removed along the horizontal direction using a lateral etching process to form lateral voids 23. The stopping position of the lateral etching can be controlled by adjusting parameters such as etching time, etchant flow rate, and flow volume, thereby forming the remaining semiconductor layer 21 with a specific shape and size.

[0105] Then, a second insulating layer 22 can be filled into the transverse gap 23 by deposition or other processes, thereby achieving the effect of replacing part of the semiconductor layer 21 with the second insulating layer 22 in the connection region 100a.

[0106] Among them, see Figure 8 and Figure 9 The first isolation structure 103 can be removed to form an etched opening 94 in the semiconductor structure. The etched opening 94 exposes the sidewalls of the semiconductor layer 21. By introducing an etchant into the etched opening 94, and utilizing the horizontal flow property of the etchant, a portion of the semiconductor layer 21 can be removed by lateral etching. Accordingly, see [reference needed]. Figure 11 and Figure 12 After the second insulating layer 22 is fabricated, the etched opening 94 needs to be filled with insulating material to form a third insulating structure 105. The material of the third insulating structure 105 can be the same as that of the first insulating structure 103 (see...). Figure 3 The materials are the same.

[0107] In some embodiments, see Figure 21 and Figure 22 This is a schematic diagram of the final structure of a semiconductor structure provided in an embodiment of this disclosure. As shown in the figure, the retained semiconductor layer 21 is close to and flush with one side of the contact plug 40 along the y-direction to form a ring-shaped horizontal conductor 50 with a flat outer side. To fabricate this final structure, this embodiment provides several methods, and the structure can be obtained through any of the following methods. Figure 21 and Figure 22 The structure shown is as follows:

[0108] In one possible implementation, see [reference] Figure 9 The diagram shows five etched openings 94. This is for the purpose of explaining the technical solution of this disclosure. Figure 9 Based on the indicated orientation, the five etched openings 94 are named, from left to right, as first opening 94a, second opening 94b, third opening 94c, fourth opening 94d, and fifth opening 94e. For example, when etchant is introduced into the first opening 94a and second opening 94b, a portion of the semiconductor layer 21 located between the first opening 94a and second opening 94b can be removed. By controlling parameters such as the proportion, flow rate, flow velocity, and time of the etchant, the position and shape of the retained semiconductor layer 21 can be adjusted, thereby controlling the shape and size of the subsequently formed horizontal conductive line 50. In one example, combined with... Figure 9 and Figure 23 By increasing the flow rate or volume of the etchant in the first opening 94a to be greater than that in the second opening 94b, a smaller lateral gap 23 can be formed on the right side of the retained semiconductor layer 21. This allows the retained semiconductor layer 21 to be closer to the second opening 94b in the y-direction, thus bringing the retained semiconductor layer 21 closer to the side of the subsequently formed contact plug 40 in the y-direction. This embodiment achieves this by introducing etchants with different flow rates or volumes into different etched openings 94, which is beneficial in subsequent processes (see...). Figure 13It can be manufactured without changing the initial position of the contact hole 93'. Figure 21 and Figure 22 The semiconductor structure shown has a ring-shaped horizontal conductor 50 with a flat outer side.

[0109] In another possible implementation, see Figure 24 The retained semiconductor layer 21 is located in the center between two adjacent etched openings 94. Figure 24 Compared to the retained semiconductor layer 21 shown Figure 9 The retained semiconductor layer 21 shown has a larger dimension in the y-direction. This arrangement ensures that when the dimension of the retained semiconductor layer 21 in the y-direction is equal to the dimension of the contact hole 93 in the y-direction, in subsequent processes (see...). Figure 13 Without changing the opening position of the initial contact hole 93', it is possible to prevent part of the structure of the horizontal wire 50 from extending between adjacent initial contact holes 93', so that the horizontal wire 50 is located on one side of the contact plug 40 in the y direction, thereby obtaining Figure 21 and Figure 22 The semiconductor structure shown has a ring-shaped horizontal conductor 50 with a flat outer side. In this embodiment, the amount of etching on the semiconductor layer 21 can be reduced by decreasing the flow rate or velocity of the etchant, or by reducing the etching time, thereby making the size of the retained semiconductor layer 21 larger. This will not be elaborated further here.

[0110] In yet another possible implementation, combined with Figure 9 and Figure 25 ,exist Figure 9 In the steps shown, an etchant with the same parameters can be introduced into each etched opening 94, so that the retained semiconductor layer 21 is located in a centered position between two adjacent etched openings 94. Subsequently, the position or shape of the initial contact hole 93' can be changed so that the left or right edge of the initial contact hole 93' is aligned with the edge of the retained semiconductor layer 21, thus fabricating the desired semiconductor layer 21. Figure 21 and Figure 22 The semiconductor structure shown has a ring-shaped horizontal conductor 50 with a flat outer side. Exemplarily, in conjunction with... Figure 9 and Figure 25 The initial contact hole 93' between the first opening 94a and the second opening 94b can be set to be close to the first opening 94a.

[0111] Step S130: Forming contact plugs that pass through the first insulating layer, the second insulating layer and the remaining semiconductor layer, with the contact plugs extending to the corresponding second insulating layer at different depths.

[0112] In this step, such as Figures 15 to 17As shown, a multi-step photolithography and etching process can be used to etch the first insulating layer 10 and the combined layer 20 (i.e., the second insulating layer 22 and the remaining semiconductor layer 21) downward along the z-direction, forming a plurality of contact holes 93 with different extension depths. The contact holes 93 of different depths are respectively aligned with different layers of the second insulating layer 22 and extend to the corresponding second insulating layer 22 (hereinafter referred to as the target insulating layer), thereby exposing part of the top surface of the silicon oxide layer 11 of the first insulating layer 10 below the target insulating layer (described in detail below).

[0113] By filling each contact hole 93 with a conductive material (such as copper or tungsten), a contact plug 40 can be formed.

[0114] Step S140: Using the remaining semiconductor layer as an etch stop layer, remove a portion of the second insulating layer to form the ends of the horizontal word lines of the exposed array region and the lateral space of the contact plug in the connection region.

[0115] In this step, such as Figure 17 and Figure 18 As shown, the remaining semiconductor layer 21 can be used as an etch stop layer to remove part of the structure of the second insulating layer 22, thereby forming the end 201 of the horizontal word line 200 exposing the array region 100b in the connection region 100a (see...). Figure 22 ) and the lateral space 50' of the contact plug 40.

[0116] An etchant with a high etch selectivity to the second insulating layer 22 but a very low etch selectivity to the semiconductor layer 21 can be used to selectively etch away the second insulating layer 22 between the semiconductor layer 21 and the etched opening 94 until the semiconductor layer 21 is exposed, so as to form a lateral space 50' in the connection region 100a.

[0117] Since the semiconductor layer 21 serves as an etch stop layer, the lateral dimension of the lateral space 50' used to form the horizontal conductor 50 is restricted, ensuring the controllability of the shape and size of the lateral space 50'. This avoids over-etching during the formation of the lateral space 50', thereby preventing excessive parasitic capacitance caused by an excessively large relative area of ​​the metal layer in the lateral space 50'. By setting an etch stop layer, parasitic capacitance can be effectively reduced, improving the performance of the semiconductor device.

[0118] Step S150: Form horizontal wires that electrically couple horizontal word lines and contact plugs in the lateral space, with the horizontal wires also abutting against the remaining semiconductor layer.

[0119] In this step, such as Figure 19 As shown, a deposition process can be used to fill the lateral space 50' with conductive material to form electrically coupled to the horizontal word lines 200 (see...). Figure 21) and the horizontal wire 50 of the contact plug 40.

[0120] In this embodiment, since the size of the lateral space 50' is controllable, the formed horizontal conductor 50 conforms to the expected design shape, reducing the parasitic capacitance and additional power consumption caused by the excessive area of ​​the horizontal conductor 50, which is conducive to establishing an efficient, low parasitic, and low power consumption electrical coupling connection between the horizontal conductor 50 and the other circuit structures through the contact plug 40.

[0121] In some embodiments, this embodiment is a further explanation of step S130 in the foregoing embodiments. Step S130, forming a contact plug 40 that passes through the first insulating layer 10, the second insulating layer 22, and the remaining semiconductor layer 21, includes the following steps:

[0122] Step S210: Etch the first insulating layer, the second insulating layer and the remaining semiconductor layer downward to form contact holes with different extension depths. The bottom of the contact holes is located on the surface of the silicon nitride layer in the first insulating layer.

[0123] In this step, such as Figure 13 As shown, semiconductor structures can be patterned using processes such as photolithography to form multiple contact holes within the semiconductor structure. It should be noted that, for ease of explanation of the technical solution of this disclosure, the contact hole formed in step S210 is named initial contact hole 93'. By further fabricating the initial contact hole 93', the final shape of the contact hole 93 can be obtained. The cross-sectional shape (i.e., the xy-plane) of the initial contact hole 93' can be, for example, rectangular, circular, etc. In this embodiment, a rectangle is used as an example for illustration.

[0124] By controlling parameters such as the composition, ratio, flow rate, flow velocity, and time of the etchant, selective etching of different structures (such as silicon oxide layer 11, silicon nitride layer 12, and semiconductor layer 21) can be achieved. The semiconductor layer 21 can be made of silicon, for example. Through repeated alternating etching steps, multiple initial contact holes 93' of different depths can be formed, with the bottom of each initial contact hole 93' stopping at the upper surface of the corresponding silicon nitride layer 12 of the first insulating layer 10. During the repeated alternating etching process, for example, plasma etching of the silicon oxide layer 11 and silicon nitride layer 12 can be used, primarily composed of fluorocarbon compounds (such as C4F8 / CHF3 / O2), while fluorine-based gas etching of the semiconductor layer 21 can be employed.

[0125] Step S220: Deposit insulating material inside the contact hole.

[0126] In this step, such as Figure 14As shown, after forming the initial contact hole 93', a layer of isolation material can be deposited on the surface of the semiconductor structure using a deposition process to form an isolation material layer 60'. The surface of the semiconductor structure includes the top surface of the semiconductor structure, as well as the bottom and sidewalls of the initial contact hole 93'. The isolation material layer 60' has a large difference in etching selectivity between the silicon nitride layer 12 of the first insulating layer 10 and the second insulating layer 22, thereby avoiding the accidental removal of the isolation material when the second insulating layer 22 and the first insulating layer 10 are removed to form the lateral space 50'. In one example, the isolation material can be, for example, silicon oxide.

[0127] The thickness of the isolation material layer 60' can be adaptively adjusted according to the structural requirements of the semiconductor structure; however, no further limitations are imposed in this embodiment.

[0128] Step S230: Remove the insulating material at the bottom of the contact hole and the material below the bottom of the contact hole until the surface of the silicon oxide layer in the next layer of the first insulating layer is exposed, forming pad holes located in the corresponding second insulating layer. The remaining insulating material is located on the sidewall of the contact hole, forming a sidewall layer.

[0129] In this step, such as Figure 15 and Figure 16 As shown, an etching process can be used, with the top surface of the silicon oxide layer 11 in the first insulating layer 10 exposed by the initial contact hole 93' in step S210 as the etching stop position, and the isolation material layer 60' located on the bottom wall of the initial contact hole 93' removed along the vertical direction (i.e., the z-direction shown). During the removal of the isolation material layer 60' in the initial contact hole 93', the isolation material layer 60' covering the top surface of the semiconductor structure will also be removed simultaneously, leaving the isolation material layer 60' covering the sidewall of the initial contact hole 93', and the retained isolation material layer 60' forms the sidewall layer 60.

[0130] The inner wall has an initial contact hole 93' forming a contact hole 93 in the sidewall layer 60.

[0131] Reference Figure 16 As shown, after forming the sidewall layer 60, an etchant with a high etch selectivity for silicon nitride can be used to remove material located below the bottom of the contact hole 93 (e.g., the silicon nitride layer 12 of the first insulating layer 10, the second insulating layer 22, and the semiconductor layer 21) through an etching process until the surface of the silicon oxide layer 11 in the first insulating layer 10 located below the target insulating layer is exposed. The etchant can flow and diffuse in the horizontal direction to remove portions of the first insulating layer 10, the second insulating layer 22, and the semiconductor layer 21 between two adjacent silicon oxide layers 11, thereby forming a pad hole 70' extending between the two adjacent silicon oxide layers 11 below the contact hole 93.

[0132] In some embodiments, based on different material properties, the first insulating layer 10 and the second insulating layer 22 can be etched away first to form the contact hole 93 and the pad hole 70', and then the semiconductor layer 21 in the contact hole 93 and the pad hole 70' can be removed to meet the etching morphology and avoid abnormal morphology of the contact hole 93 and the pad hole 70' due to different material etching selectivity.

[0133] See Figure 16 The pad hole 70' is located at the bottom of the contact hole 93 and the two are connected to each other. The dimension of the pad hole 70' in the y-direction is larger than the dimension of the contact hole 93 in the y-direction. The bottom of the pad hole 70' exposes part of the top surface of the silicon oxide layer 11 located below the target insulating layer.

[0134] Step S240: Form a pad in the pad hole. The pad is located on the silicon oxide layer and surrounded by the second insulating layer.

[0135] In this step, such as Figure 17 As shown, and in combination Figure 16 As shown, conductive material can be filled into the pad hole 70' to form the pad 70. The pad 70 is located on the silicon oxide layer 11 of the first insulating layer 10 and is surrounded by the second insulating layer 22. It should be noted that in subsequent fabrication processes, part of the structure of the second insulating layer 22 will be removed, so that one sidewall of the pad 70 is connected to the horizontal conductor 50, which will be described in detail later.

[0136] In some alternative implementations, see Figure 17 Before filling with conductive material, a thin diffusion barrier layer 80 can be deposited within the pad hole 70' to form the pad 70, and then the main conductive material can be filled in to form the pad 70. The material of the diffusion barrier layer 80 can be, for example, titanium nitride, which can effectively prevent the main conductive material (e.g., copper, tungsten) from diffusing into the surrounding insulating material (e.g., sidewall layer 60, silicon oxide layer 11) during high-temperature processes, thereby avoiding device leakage or failure caused by diffusion. At the same time, as an intermediate layer between the pad 70 and the insulating material, the diffusion barrier layer 80 can significantly enhance the adhesion between the pad 70 and the insulating material, improve the overall stability of the structure, and prevent the contact plug 40 and the pad 70 from delaminating or falling off.

[0137] Step S250: A contact plug is formed in the contact hole, the bottom of the contact plug is located on the pad so as to extend through the pad to the corresponding second insulating layer, and the sidewall of the contact plug contacts the sidewall layer.

[0138] In this step, such as Figure 17 As shown, the contact plug 40 can be fabricated in the same manner as the pad 70. The sidewall of the contact plug 40 contacts the sidewall layer 60, and the bottom of the contact plug 40 is located on the pad 70, thereby extending through the pad 70 to the corresponding second insulating layer 22.

[0139] In some alternative implementations, see Figure 16 and Figure 17 Steps S240 and S250 can be performed in the same deposition process step, thereby forming an integrated contact plug 40 and pad 70. This integrated structure simplifies the manufacturing process and reduces the contact resistance and capacitance between the contact plug 40 and pad 70, facilitating the formation of a reliable conductive path. Furthermore, by integrating the contact plug 40 and pad 70, the structural reliability and stability of both are ensured, which is beneficial for improving the stability of electrical signal transmission.

[0140] In some embodiments, see Figure 17 After the contact plug 40 is formed, a second dielectric layer 102 can be deposited on the top surface of the semiconductor structure. The material of the second dielectric layer 102 can be an oxide (e.g., silicon oxide). The second dielectric layer 102 can provide protection for the semiconductor structure (e.g., the contact plug 40) to prevent the contact plug 40 from being damaged in subsequent processes, which would lead to performance degradation.

[0141] See Figures 18 to 20 In subsequent processes (i.e., when fabricating the horizontal space 50' and the horizontal conductor 50), the second dielectric layer 102 at a specific location and the third isolation structure 105 located below it can be removed to expose the sidewalls of the retained semiconductor layer 21. After fabricating the horizontal conductor 50, the area where the third isolation structure 105 has been removed needs to be refilled with isolation material to form a fourth isolation structure 106. The fourth isolation structure 106 is used to protect the exposed sidewalls of the horizontal conductor 50.

[0142] In some embodiments, this embodiment is a further explanation of step S110 in the foregoing embodiments. Step S110, providing a substrate, includes the following steps:

[0143] Step S310: Form vertically alternating initial semiconductor layers and sacrificial semiconductor layers on the array region and connection region of the substrate.

[0144] In this step, such as Figure 2 and Figure 3 As shown, the substrate 100 includes an adjacent array region 100b and a connection region 100a.

[0145] like Figure 2As shown, multiple layers of initial semiconductor layers 21' and multiple layers of sacrificial semiconductor layers 30 can be vertically and alternately stacked on the top surface of the substrate 100 through processes such as epitaxial growth or deposition. The initial semiconductor layer 21' can be made of polycrystalline silicon or monocrystalline silicon, for example, and is used to subsequently form the active region of the array region 100b and the semiconductor layer 21 of the connection region 100a; the sacrificial semiconductor layer 30 can be made of silicon germanide (SiGe) or other materials that have etching selectivity with the initial semiconductor layer 21'.

[0146] In this embodiment, during the formation of the horizontal conductor 50 in the connection region 100a, the etching amount can be controlled by adjusting the etching parameters during the replacement of the stacked layer material. This retains a portion of the semiconductor layer 21 as an etching stop layer. The area of ​​the semiconductor layer 21 removed by lateral etching can be filled with insulating material to form a second insulating layer 22. By providing an etching stop layer in this embodiment, when etching the second insulating layer 22, the etchant used to etch the second insulating layer 22 has a poor etching effect on the etching stop layer. Therefore, after encountering the etching stop layer, etching of the second insulating layer 22 will not continue. This effectively limits the over-etching problem of the second insulating layer 22 during the fabrication of the horizontal conductor 50, thereby solving the problem of excessively large dimensions of the horizontal conductor 50 and the resulting parasitic capacitance between the horizontal conductors 50 caused by over-etching.

[0147] In one example, the initial semiconductor layer 21' is made of silicon, and the sacrificial semiconductor layer 30 is made of silicon germanide. Silicon germanide has a high lattice match with silicon but can be selectively etched, making it easy to be replaced by the first insulating layer 10 later.

[0148] In some embodiments, see Figure 2 and Figure 3 The semiconductor structure can be patterned to form multiple isolation structures within the semiconductor structure. These isolation structures include a first isolation structure 103 and a second isolation structure 104. The multiple first isolation structures 103 are arranged along... Figure 2 The y-direction spacing shown is arranged in the connection region 100a to divide the connection region 100a into multiple isolated regions, each of which can form stacked multi-layer horizontal conductors 50. Multiple second isolation structures 104 are spaced apart along the y-direction between the connection region 100a and the array region 100b to avoid interference between the manufacturing processes of the two regions. Gaps exist between adjacent second isolation structures 104 to allow horizontal word lines 200 (see reference) in the array region 100b to pass through. Figure 21 It passes through and is electrically coupled to the horizontal conductor 50.

[0149] Step S320: Pattern the initial semiconductor layer and the sacrificial semiconductor layer of the array region, and form vertically stacked memory cells in the array region.

[0150] In this step, such as Figures 2 to 7 As shown, and in combination Figure 21 and Figure 22 By patterning the initial semiconductor layer 21' and the sacrificial semiconductor layer 30 of the array region 100b, vertically stacked active regions 400 and memory cells 500, as well as bit lines 300 extending in the vertical direction (i.e., the z direction) and horizontal word lines 200 extending in the horizontal direction (i.e., the x direction) can be formed in the array region 100b. The manufacturing process of the array region 100b will not be described in detail in this embodiment.

[0151] It should be noted that this step can be performed simultaneously with steps S330 to S360 (that is, to create a storage cell 500 in array region 100b and to create a horizontal wire 50 in connection region 100a), or they can be performed sequentially, without any restrictions.

[0152] Step S330: A first vertical opening is formed in the connection region, the first vertical opening penetrating the initial semiconductor layer and the sacrificial semiconductor layer.

[0153] In this step, such as Figure 4 As shown, the connection region 100a can be patterned using photolithography and etching processes to form a first vertical opening 91 in the connection region 100a. The first vertical opening 91 extends through all the initial semiconductor layers 21' and sacrificial semiconductor layers 30 in the connection region 100a along the vertical direction (z direction) until it exposes the top surface of the substrate 100 or extends into the substrate 100.

[0154] The sidewall of the first vertical opening 91 shows a clear cross-section where the initial semiconductor layer 21' (silicon layer) and the sacrificial semiconductor layer 30 (silicon germanium layer) are alternately exposed. The first vertical opening 91 serves as a channel for subsequent lateral processes. Etching agent is introduced into the first vertical opening 91, thereby selectively removing the sacrificial semiconductor layer 30 in the first vertical opening 91. Then, the first insulating layer 10 is formed through a deposition process, achieving the effect of replacing the sacrificial semiconductor layer 30 with the first insulating layer 10.

[0155] Before forming the first vertical opening 91, a first dielectric layer 101 may be deposited on the top surface of the substrate 100. The material of the first dielectric layer 101 may be an oxide (e.g., silicon oxide).

[0156] Step S340: Laterally etch the sacrificial semiconductor layer along the first vertical opening to form a lateral groove.

[0157] In this step, such as Figure 4As shown, an etchant (such as a solution of hydrogen peroxide and hydrofluoric acid mixed in a specific ratio) with a high etch selectivity for the sacrificial semiconductor layer 30 can be introduced into the first vertical opening 91 to etch the sacrificial semiconductor layer 30 laterally along the sidewall of the first vertical opening 91, thereby forming a lateral groove 92 between two adjacent initial semiconductor layers 21' (see...). Figure 5 The lateral groove 92 communicates with the first vertical opening 91. In subsequent steps, for example, material can be deposited into the lateral groove 92 through the first vertical opening 91 to form the first insulating layer 10 (see...). Figure 7 ).

[0158] In an alternative implementation, the entire sacrificial semiconductor layer 30 located between adjacent initial semiconductor layers 21' can be completely removed.

[0159] Step S350: Thin the initial semiconductor layer exposed by the lateral groove along the lateral groove, and the thinned initial semiconductor layer forms a semiconductor layer.

[0160] In this step, such as Figure 5 As shown, the first vertical opening 91 can be used to access the lateral groove 92 (see reference). Figure 4 An etchant is introduced into the lateral groove 92, and the etchant reacts with the structure of the initial semiconductor layer 21' exposed in the lateral groove 92 to consume the initial semiconductor layer 21', thereby thinning the thickness of the initial semiconductor layer 21'. The thinned initial semiconductor layer 21' forms a semiconductor layer 21 of the target size.

[0161] In some alternative implementations, the initial thickness of the initial semiconductor layer 21' and the sacrificial semiconductor layer 30 can be controlled in step S310, for example, the thickness of the initial semiconductor layer 21' can be set to the target size, thereby skipping step S350, that is, directly jumping to step S360 after step S340.

[0162] Step S360: A first insulating layer is formed in the lateral groove. The first insulating layer covers the surface of the semiconductor layer, and the first insulating layer and the semiconductor layer alternate vertically.

[0163] In this step, such as Figure 6 and Figure 7 As shown, the first vertical opening 91 can be used to access the lateral groove 92 (see reference). Figure 8 Silicon nitride and silicon oxide are deposited sequentially in the process to form a silicon nitride layer 12 and a silicon oxide layer 11, which together constitute the first insulating layer 10.

[0164] In an alternative embodiment, the first insulating layer 10 may be formed by the following steps:

[0165] Step S361: A silicon nitride layer is formed in the lateral groove, and the silicon nitride layer covers the surface of the semiconductor layer.

[0166] In this step, such as Figures 6 to 8 As shown, a silicon nitride layer 12 can be deposited into the lateral groove 92 through the first vertical opening 91, and the silicon nitride layer 12 covers the surface of the semiconductor layer 21. Specifically, the silicon nitride layer 12 covers the bottom surface of the semiconductor layer 21 above the lateral groove 92, the top surface of the semiconductor layer 21 below the lateral groove 92, and also covers the sidewall surface of the lateral groove 92.

[0167] Step S362: Fill the remaining area of ​​the lateral groove with a silicon oxide layer, which covers the surface of the silicon nitride layer.

[0168] In this step, such as Figure 7 and Figure 8 As shown, a silicon oxide layer 11 can be deposited into the lateral groove 92 through the first vertical opening 91. The formed silicon oxide layer 11 is located between two adjacent silicon nitride layers 12. The two silicon nitride layers 12 and the silicon oxide layer 11 constitute the first insulating layer 10 of the sandwich structure. The multiple first insulating layers 10 and the multiple semiconductor layers 21 are stacked alternately in the vertical direction (i.e., the z-direction). In one example, the silicon oxide layer 11 and the silicon nitride layer 12 surrounding the surface of the silicon oxide layer 11 can be formed through steps S361 and S362.

[0169] This embodiment provides an efficient and reliable method for constructing a three-dimensional stacked semiconductor structure in the connection region 100a. The connection region 100a and the array region 100b share an initial stacked layer, and the devices in the connection region 100a can start the process synchronously with the core devices (such as memory cell 500) in the array region 100b, simplifying the overall process.

[0170] In some embodiments, such as Figures 20 to 22 As shown, contact hole 93 is adaptively configured (see reference). Figure 16 The placement of the contacts 40 allows multiple contacts 40 to be separated and formed on both sides of the width direction (i.e., the y-direction) of the horizontal conductor 50. This arrangement helps to shorten the space occupied by the horizontal conductor 50 in the width direction, thereby reducing the size of the semiconductor structure and improving the integration density.

[0171] Among them, such as Figure 21 and Figure 22 As shown, for ease of explanation of the technical solution of this disclosure, the multi-layer horizontal conductors 50 are numbered along the stacking direction. The topmost horizontal conductor 50 is numbered 1, and the horizontal conductors numbered 2, 3, 4, and 5 are numbered sequentially downwards. Horizontal conductors 50 numbered 1, 3, and 5 are odd-numbered conductors, while horizontal conductors 50 numbered 2 and 4 are even-numbered conductors. Figure 21 and Figure 22 Taking the indicated direction as an example, along Figure 21 In the y-direction shown, multiple contact plugs 40, separately positioned on one side of the horizontal conductor 50 in the y-direction, are electrically coupled to the odd-numbered conductors in the multi-layer horizontal conductor 50. Conversely, multiple contact plugs 40 on the other side of the horizontal conductor 50 in the y-direction are electrically coupled to the even-numbered conductors. This arrangement allows for the efficient and reliable routing of multiple horizontal conductors 50 through the contact plugs 40 on both sides within a limited horizontal space. Furthermore, the odd and even numbers directly correspond to their physical left and right positions, resulting in a more regular and symmetrical circuit layout and wiring, which simplifies the overall chip design.

[0172] In some embodiments, such as Figure 21 and Figure 22 As shown, at least a portion of the horizontal conductors 50 in the multi-layered horizontal conductors 50 are configured as loops, such as rectangular loops, elliptical loops, or track loops (see [reference]). Figure 21 and Figure 22 ). Combination Figures 20 to 22 It is understandable that by setting the horizontal conductor 50 into a ring shape and placing the contact plug 40 on the outer side of the ring shape of the horizontal conductor 50, multiple horizontal conductors 50 can be uniformly manufactured through the opening on the inner side of the ring during the process, which improves the consistency of the multiple horizontal conductors 50 and simplifies the process.

[0173] According to exemplary embodiments of this disclosure, such as Figures 20 to 22 As shown, this embodiment provides a semiconductor structure that can be formed using the semiconductor structure fabrication method provided in any of the foregoing embodiments of this disclosure.

[0174] like Figure 20 As shown, the semiconductor structure includes a substrate 100, which supports a structure disposed thereon. In this embodiment, the substrate 100 can be made of any one of the following materials: monocrystalline silicon, polycrystalline silicon, amorphous silicon, germanium, silicon carbide, silicon germanide, germanium-on-insulator, or silicon-on-insulator.

[0175] like Figure 20 and Figure 22 As shown, the substrate 100 includes an array region 100b and a connection region 100a that are adjacent in the horizontal direction. The horizontal direction can be either the x-direction or the y-direction shown in the figure; in this embodiment, the x-direction is used as an example for illustration.

[0176] Among them, reference Figure 21 , Figure 22 and Figure 20The array region 100b of the substrate 100 has a storage function (also known as a core region). The array region 100b contains a plurality of memory cells 500 that are three-dimensionally stacked and defined by the intersection of horizontal word lines 200 and vertical bit lines 300. The array region 100b also includes a plurality of active regions 400, which are arranged in an array along the horizontal and vertical directions (shown in the z direction). The plurality of active regions 400 are arranged in a one-to-one correspondence with the plurality of memory cells 500.

[0177] The connection region 100a of the substrate 100 is adjacent to the array region 100b. The connection region 100a includes multiple horizontal conductors 50 and multiple contact plugs 40 with different extension depths. The multiple horizontal conductors 50 are connected to the multiple contact plugs 40 in a one-to-one correspondence. The number of layers of the horizontal conductors 50 is the same as the number of layers of the multiple memory cells 500 in the array region 100b. The horizontal conductors 50 electrically couple the horizontal word lines 200 to the contact plugs 40, so that the contact plugs 40 establish electrical coupling with the horizontal word lines 200 through the horizontal conductors 50, thereby achieving efficient and unified control of a large number of memory cells 500 in the array region 100b through the connection region 100a.

[0178] refer to Figure 21 and Figure 22 For example, the horizontal conductor 50 of the connection area 100a connects four horizontal word lines 200 of the array area 100b adjacent to it on the left and right sides. However, this is not a limitation; more or fewer horizontal word lines 200 can also be connected. In this embodiment, the horizontal conductor 50 allows multiple memory cells 500 on the same layer to share the control signal of the same horizontal word line 200, thereby significantly reducing the number of interconnect plugs, saving physical space in the connection area 100a, avoiding wiring congestion, suppressing signal crosstalk and noise, and improving overall storage density and reliability. Furthermore, the horizontal conductor 50 allows for the sharing of peripheral circuitry, reducing the length and delay of signal transmission paths, making row selection operations faster, enabling rapid activation of specific memory cells (e.g., capacitors and transistors), and improving access speed and efficiency.

[0179] The connection region 100a of the substrate 100 further includes a plurality of first insulating layers 10 and a plurality of combined layers 20, which are alternately stacked along the thickness direction (z direction shown) of the substrate 100. The first insulating layer 10 is made of insulating material, and a first insulating layer 10 is disposed between any two adjacent horizontal conductors 50, so that the first insulating layer 10 can electrically isolate the two adjacent horizontal conductors 50.

[0180] The composite layer 20 is located between two adjacent first insulating layers 10, so that the number of layers in the composite layer 20 is the same as the number of layers in the horizontal conductor 50. The composite layer 20 is a composite structure, and each composite layer 20 includes a connected second insulating layer 22 and a semiconductor layer 21 (such as a silicon layer). The second insulating layer 22 and the semiconductor layer 21 are arranged and connected in the horizontal direction. The semiconductor layer 21 in the composite layer 20 is also in contact with the horizontal conductor 50. The second insulating layer 22 is located on the side of the retained semiconductor layer 21 away from the horizontal conductor 50.

[0181] The retained semiconductor layer 21 is formed before the horizontal wire 50 and serves as an etching stop layer in the fabrication step of the horizontal wire 50. The retained semiconductor layer 21 can limit the structural parameters (such as shape and size) of the horizontal wire 50 to form a horizontal wire 50 with the desired shape and size. This avoids the horizontal wire 50 from having an excessively large area due to over-etching during fabrication, which would result in a large parasitic capacitance. By setting an etching stop layer, the performance of the semiconductor structure can be improved.

[0182] In some embodiments, such as Figure 16 and Figure 20 As shown, the first insulating layer 10 includes a silicon oxide layer 11 and a silicon nitride layer 12 surrounding the surface of the silicon oxide layer 11. The silicon nitride layer 12 and the silicon oxide layer 11 exhibit a high difference in etch selectivity for a specific etchant. Based on this, by setting the first insulating layer 10 to be composed of a silicon oxide layer 11 and a silicon nitride layer 12, it is possible to ensure that the bottom of the initial contact hole 93' is precisely stopped on the surface of the silicon nitride layer 12 when forming the initial contact hole 93' during the semiconductor structure fabrication process (as described above), and it is also possible to ensure that after forming the sidewall layer 60 (made of the same material as the silicon oxide layer 11), a portion of the silicon nitride layer 12 is removed laterally to create a pad 70 between two adjacent silicon oxide layers 11.

[0183] It should be noted that, in Figures 8 to 20 In the z-direction, the thickness of each semiconductor layer 21 is much greater than the thickness of the two adjacent silicon nitride layers 12. Based on this, even if the silicon nitride layer 12 and the second insulating layer 22 are made of the same material, the semiconductor layer 21 has a larger thickness and the silicon nitride layer 12 has a smaller thickness. The blocking effect of the semiconductor layer 21 is obvious, which can still ensure that when the second insulating layer 22 is removed to form the lateral space 50', the semiconductor layer 21 can act as an etching stop layer to limit the size of the lateral space 50'.

[0184] In some embodiments, such as Figure 20 and Figure 21As shown, the semiconductor structure also includes multiple pads 70, which are connected one-to-one with multiple contact plugs 40 and are located at the bottom of the corresponding contact plugs 40. Taking a pad 70 with a rectangular cross-section as an example, one of the four sides of the pad 70 is used for electrical coupling with the horizontal conductor 50, and the other three sides are surrounded by a second insulating layer 22. The bottom surface of the pad 70 is connected to the silicon oxide layer 11 below the corresponding second insulating layer 22 of the contact plug 40.

[0185] The pad 70 serves as an intermediate structure for interconnecting the contact plug 40 and the horizontal conductor 50. The pad 70 is larger in the horizontal direction than the contact plug 40. By setting the pad 70, it is beneficial to form a stable contact interface and improve the reliability of the electrical coupling between the contact plug 40 and the horizontal conductor 50.

[0186] In some embodiments, such as Figure 16 and Figure 17 As shown, the pad 70 and the contact plug 40 can be formed simultaneously in one step, thus forming an integral structure. This integral structure simplifies the manufacturing process and reduces the contact resistance and parasitic capacitance between the contact plug 40 and the pad 70, facilitating the formation of a reliable conductive path. By integrating the pad 70 and the contact plug 40 into a single structure, the overall structural reliability is increased, ensuring a reliable conductive path and guaranteeing the structural reliability and stability of both, which is beneficial for improving the stability of electrical signal transmission.

[0187] Among them, such as Figure 20 and Figure 21 As shown, a sidewall layer 60 is also provided on the side wall of the contact plug 40, and the sidewall layer 60 surrounds the contact plug 40 in the circumferential direction. By providing the sidewall layer 60, an insulating connection can be formed between the contact plug 40 and the non-target structure it passes through (such as the horizontal wire 50 located above the second insulating layer 22 corresponding to the contact plug 40), thereby achieving an electrical isolation effect.

[0188] Among them, such as Figure 20As shown, a diffusion barrier layer 80 is also provided in the semiconductor structure. Specifically, the diffusion barrier layer 80 can be formed between the sidewall of the contact plug 40 and the sidewall of the sidewall layer 60, between the top surface of the pad 70 and the bottom surface of the sidewall layer 60, between the sidewall of the pad 70 and the corresponding second insulating layer 22, and between the bottom surface of the pad 70 and the top surface of the silicon oxide layer 11. The material of the diffusion barrier layer 80 can be, for example, titanium nitride, which can effectively block the diffusion of the main conductive material (e.g., copper, tungsten) into the surrounding insulating material (e.g., sidewall layer 60, silicon oxide layer 11) during high-temperature processes, thereby preventing diffusion from causing device leakage or failure. Furthermore, as an intermediate layer between the contact plug 40 and the pad 70 and the insulating material, the diffusion barrier layer 80 can significantly enhance the adhesion between the contact plug 40 and the pad 70 and the insulating material, improve the overall stability of the structure, and prevent the contact plug 40 and the pad 70 from delaminating or detaching.

[0189] In some embodiments, such as Figures 20 to 22 As shown, multiple contact plugs 40, which are connected one-to-one with the multilayer horizontal conductors 50 stacked in a stacked manner, are located on both sides of the width direction (i.e., the y-direction) of the horizontal conductors 50. This arrangement helps to shorten the space occupied by the horizontal conductors 50 in the width direction, thereby reducing the size of the semiconductor structure and improving the integration density.

[0190] Among them, such as Figures 20 to 22 As shown, for ease of explanation of the technical solution of this disclosure, the multi-layer horizontal conductors 50 are numbered along the stacking direction. The topmost horizontal conductor 50 is numbered 1, and the horizontal conductors numbered 2, 3, 4 and 5 are numbered downwards. The horizontal conductors 50 numbered 1, 3 and 5 are odd-numbered conductors, and the horizontal conductors 50 numbered 2 and 4 are even-numbered conductors.

[0191] by Figure 21 and Figure 22 Taking the indicated direction as an example, along Figure 21 In the y-direction shown, multiple contact plugs 40, separately positioned on one side of the horizontal conductor 50 in the y-direction, are electrically coupled to the odd-numbered conductors in the multi-layer horizontal conductor 50. Conversely, multiple contact plugs 40 on the other side of the horizontal conductor 50 in the y-direction are electrically coupled to the even-numbered conductors. This arrangement allows for the efficient and reliable routing of multiple horizontal conductors 50 through the contact plugs 40 on both sides within a limited horizontal space. Furthermore, the odd and even numbers directly correspond to their physical left and right positions, resulting in a more regular and symmetrical circuit layout and wiring, which simplifies the overall chip design.

[0192] In some embodiments, such as Figure 21 As shown, at least a portion of the horizontal conductors 50 in the multi-layered horizontal conductors 50 are configured as loops, such as rectangular loops, elliptical loops, or track loops (see [reference]). Figure 21 and Figure 22 ).

[0193] Combination Figures 20 to 22 The horizontal conductor 50 is set into a ring shape, and the contact plug 40 is set on the outer side of the ring shape of the horizontal conductor 50. During the process, multiple horizontal conductors 50 can be uniformly manufactured through the opening on the inner side of the ring, which improves the consistency of the multiple horizontal conductors 50 and simplifies the process.

[0194] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0195] In the description of this specification, references to the terms "embodiment," "exemplary embodiment," "some implementation," "illustrated implementation," "example," etc., refer to specific features, structures, materials, or characteristics described in connection with an implementation or example that are included in at least one implementation or example of this disclosure.

[0196] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.

[0197] In the description of this disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0198] It is understood that the terms "first," "second," etc., as used in this disclosure may be used to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.

[0199] In one or more accompanying drawings, the same elements are represented by similar reference numerals. For clarity, many parts in the drawings are not drawn to scale. Furthermore, certain well-known parts may not be shown. For simplicity, a structure obtained after several steps may be depicted in a single drawing. Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without adhering to these specific details.

[0200] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including horizontally adjacent array regions and connection regions, the connection regions including vertically alternating first insulating layers and semiconductor layers; In the connection region, a portion of the semiconductor layer is replaced with a second insulating layer; A contact plug is formed through the first insulating layer, the second insulating layer and the remaining semiconductor layer, the contact plug extending to the corresponding second insulating layer at different depths; Using the remaining semiconductor layer as an etch stop layer, a portion of the second insulating layer is removed to form the ends of the horizontal word lines of the array region and the lateral space of the contact plug in the connection area; Horizontal conductors are formed within the lateral space, electrically coupling the horizontal word lines and the contact plugs respectively, and the horizontal conductors also abut against the remaining semiconductor layer.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The first insulating layer includes a silicon oxide layer and a silicon nitride layer surrounding the surface of the silicon oxide layer, with the bottom of the contact plug located on the silicon oxide layer.

3. The method for fabricating a semiconductor structure according to claim 2, characterized in that, The formation of the contact plug through the first insulating layer, the second insulating layer, and the remaining semiconductor layer includes: The first insulating layer, the second insulating layer, and the remaining semiconductor layer are etched downwards to form contact holes with different depths, the bottom of which is located on the surface of the silicon nitride layer in the first insulating layer; Deposit insulating material within the contact hole; Remove the insulating material at the bottom of the contact hole, as well as the material below the bottom of the contact hole, until the surface of the silicon oxide layer in the first insulating layer of the next layer is exposed, forming pad holes located in the corresponding second insulating layer. The remaining insulating material is located on the sidewall of the contact hole, forming a sidewall layer. A pad is formed in the pad hole, the pad being located on the silicon oxide layer and surrounded by the second insulating layer; The contact plug is formed within the contact hole, the bottom of the contact plug is located on the pad to extend through the pad to the corresponding second insulating layer, and the sidewall of the contact plug contacts the sidewall layer.

4. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The contact plugs are distributed on opposite sides of the horizontal conductor; Among them, the bottom of the contact plug located on one of the opposite sides of the horizontal conductor is electrically coupled to the odd-numbered horizontal word lines; The bottom of the contact plug located on the other side of the opposite sides of the horizontal conductor is electrically coupled to the even-numbered horizontal letter lines.

5. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The horizontal conductor is looped, and the contact plug is located on the outside of the loop of the horizontal conductor.

6. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The provision of the substrate includes: Vertically alternating initial semiconductor layers and sacrificial semiconductor layers are formed on the array region and the connection region of the substrate; The initial semiconductor layer and the sacrificial semiconductor layer of the array region are patterned, and vertically stacked memory cells are formed in the array region; A first vertical opening is formed in the connection region, the first vertical opening penetrating the initial semiconductor layer and the sacrificial semiconductor layer; The sacrificial semiconductor layer is etched laterally along the first vertical opening to form a lateral groove; The initial semiconductor layer exposed by the lateral groove is thinned along the lateral groove, and the thinned initial semiconductor layer forms the semiconductor layer; The first insulating layer is formed in the lateral groove, the first insulating layer covers the surface of the semiconductor layer, and the first insulating layer and the semiconductor layer alternate vertically.

7. The method for fabricating a semiconductor structure according to claim 6, characterized in that, The formation of the first insulating layer in the lateral groove includes: A silicon nitride layer is formed in the lateral groove, and the silicon nitride layer covers the surface of the semiconductor layer; The remaining area of ​​the lateral groove is filled with a silicon oxide layer, which covers the surface of the silicon nitride layer.

8. A semiconductor structure, characterized in that, include: The substrate includes horizontally adjacent array regions and connection regions; The connection area includes: First insulating layer; A composite layer comprising a connected second insulating layer and a semiconductor layer, wherein the first insulating layer and the composite layer alternate vertically. The contact plug extends through the first insulating layer and the combined layer and into the corresponding second insulating layer in the combined layer; A horizontal conductor electrically couples the horizontal word line of the array region to the contact plug, and the horizontal conductor also abuts against the semiconductor layer.

9. The semiconductor structure according to claim 8, characterized in that, The first insulating layer includes a silicon oxide layer and a silicon nitride layer surrounding the surface of the silicon oxide layer, with the bottom of the contact plug located on the silicon oxide layer.

10. The semiconductor structure according to claim 9, characterized in that, The semiconductor structure also includes a pad, one sidewall of which is connected to the horizontal conductor, and the remaining sidewalls of which are connected to the corresponding second insulating layer. The pads are connected to the silicon oxide layer below the corresponding second insulating layer.

11. The semiconductor structure according to claim 10, characterized in that, The contact plug and the solder pad are integrally formed, and a sidewall layer is provided around the contact plug; A diffusion barrier layer is provided on a portion of the outer surface of the integral structure formed by the contact plug and the pad.

12. The semiconductor structure according to claim 8, characterized in that, The contact plugs are distributed on opposite sides of the horizontal conductor, wherein, The bottom of the contact plug located on one of the opposite sides of the horizontal conductor is electrically coupled to the odd-numbered horizontal word lines. The bottom of the contact plug located on the other side of the opposite sides of the horizontal conductor is electrically coupled to the even-numbered horizontal letter lines.

13. The semiconductor structure according to claim 8, characterized in that, The horizontal conductor is looped, and the contact plug is located on the outside of the loop of the horizontal conductor.

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