Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof. The manufacturing method comprises the following steps: providing a substrate; forming a liner layer on the substrate; a first shallow trench isolation structure with the bottom extending into the logic unit area is formed in the part, corresponding to the logic unit area, of the liner layer, and a second shallow trench isolation structure with the bottom extending into the flash memory unit area is formed in the part, corresponding to the flash memory unit area, of the liner layer; thinning the second shallow trench isolation structure to enable the top surface of the second shallow trench isolation structure to be lower than the top surface of the first shallow trench isolation structure; removing the liner layer; and forming a flash memory unit comprising a gate oxide layer, a floating gate layer, an isolation layer and a control gate layer on the flash memory region. The defect that the step height of the first shallow trench isolation structure of the logic unit region is low due to the fact that the flash memory unit region requirement is preferentially adapted in the prior art is overcome, the subsequent process integration effect and the device performance of the logic unit region can be guaranteed, and the electric leakage risk of the whole integrated circuit of the device can be remarkably reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] In related technologies, during the manufacturing process of flash memory devices, there is a problem that it is impossible to simultaneously achieve the STI step height for both the logic cell region (LG region) and the flash memory cell region (EF3 region). Related process solutions typically prioritize ensuring the step height of the STI corresponding to the flash memory cell region, but this results in a lower step height for the STI corresponding to the logic cell region. This not only affects the process integration effect and device performance of the logic cell region but also exacerbates leakage current issues in the overall integrated circuit (IP) of the device. Summary of the Invention

[0003] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This summary section is not intended to limit the key and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0004] To address the existing problems, this application provides a method for manufacturing a semiconductor device, the method comprising: A substrate is provided, the substrate including a logic cell region and a flash memory cell region; A pad layer is formed on the substrate; A first shallow trench isolation structure extending to the logic cell region is formed in the portion of the pad layer corresponding to the logic cell region, and a second shallow trench isolation structure extending to the flash memory cell region is formed in the portion of the pad layer corresponding to the flash memory cell region. The second shallow trench isolation structure is thinned so that the top surface of the second shallow trench isolation structure is lower than the top surface of the first shallow trench isolation structure; Remove the liner layer; A flash memory cell comprising a gate oxide layer, a floating gate layer, an isolation layer, and a control gate layer is formed on the flash memory cell region.

[0005] In some embodiments of this application, the second shallow trench isolation structure is thinned so that the top surface of the second shallow trench isolation structure is lower than the top surface of the first shallow trench isolation structure, including: A first mask layer is formed, which covers the first shallow trench isolation structure and the portion of the pad layer corresponding to the logic cell region; Based on the first mask layer, a portion of the thickness of the second shallow trench isolation structure is etched away so that the top surface of the second shallow trench isolation structure is lower than the top surface of the first shallow trench isolation structure.

[0006] In some embodiments of this application, the manufacturing method further includes the step of forming a well region in the flash memory cell region, and the same photomask is used to form the first mask layer and to form the well region in the flash memory cell region.

[0007] In some embodiments of this application, a portion of the thickness of the second shallow trench isolation structure is removed by a dry etching process using fluorine-containing gas, or a portion of the thickness of the second shallow trench isolation structure is removed by a wet etching process.

[0008] In some embodiments of this application, the pad layer includes a pad oxide layer on the substrate and a pad nitride layer on the side of the pad oxide layer away from the substrate.

[0009] In some embodiments of this application, forming a first shallow trench isolation structure extending to the logic cell region in the portion of the pad layer corresponding to the logic cell region, and forming a second shallow trench isolation structure extending to the flash memory cell region in the portion of the pad layer corresponding to the flash memory cell region, includes: A first shallow trench extending into the logic cell region is formed in the portion of the padding layer corresponding to the logic cell region, and a second shallow trench extending into the flash memory cell region is formed in the portion of the padding layer corresponding to the flash memory cell region. Deposit insulating material to fill the first shallow trench and the second shallow trench; Remove excess insulating material so that the surface of the insulating material is flush with the surface of the liner layer, thereby forming a first shallow trench insulating structure in the first shallow trench and a second shallow trench insulating structure in the second shallow trench.

[0010] In some embodiments of this application, forming a flash memory cell comprising a gate oxide layer, a floating gate layer, an isolation layer, and a control gate layer on the flash memory cell region includes: After the padding layer is removed, a gate oxide layer and a floating gate layer are sequentially formed on the exposed surface of the flash memory cell region, and an isolation layer covering the second shallow trench isolation structure and the floating gate layer, as well as a control gate layer located on the isolation layer, are formed.

[0011] In some embodiments of this application, after removing the pad layer, the exposed surface of the flash memory cell region is sequentially formed with a gate oxide layer and a floating gate layer, and an isolation layer covering the second shallow trench isolation structure and the floating gate layer, as well as a control gate layer located on the isolation layer, comprising: A gate oxide layer and a floating gate layer are sequentially formed on the exposed substrate surface after the pad layer is removed. The top surface of the floating gate layer in the logic cell region is higher than the top surface of the first shallow trench isolation structure, and the top surface of the floating gate layer in the flash memory cell region is higher than the top surface of the second shallow trench isolation structure. An isolation layer is formed covering the floating grid layer, the first shallow trench isolation structure, and the second shallow trench isolation structure; A control gate layer is formed on the isolation layer; A second mask layer is formed, which covers the portion of the control gate layer corresponding to the flash memory cell region; Based on the second mask layer, the portion of the control gate layer corresponding to the logic cell region, the portion of the isolation layer corresponding to the logic cell region, and the portion of the floating gate layer corresponding to the logic cell region are sequentially etched away.

[0012] In some embodiments of this application, a gate oxide layer and a floating gate layer are sequentially formed on the substrate surface exposed after the pad layer is removed, and the top surface of the floating gate layer in the logic cell region is higher than the top surface of the first shallow trench isolation structure, and the top surface of the flash memory cell region is higher than the top surface of the second shallow trench isolation structure, including: A gate oxide layer and a floating gate layer are sequentially formed on the exposed substrate surface, and the top surface of the floating gate layer is flush with the top surface of the first shallow trench isolation structure in the logic cell region, and the top surface of the floating gate layer is flush with the top surface of the second shallow trench isolation structure in the flash memory cell region. The first shallow trench isolation structure and the second shallow trench isolation structure are etched back so that the top surface of the first shallow trench isolation structure is lower than the top surface of the floating gate layer in the logic cell region, and the top surface of the second shallow trench isolation structure is lower than the top surface of the floating gate layer in the flash memory cell region.

[0013] In another aspect, this application provides a semiconductor device manufactured by the manufacturing method of any one of the semiconductor devices described above.

[0014] The semiconductor device and its manufacturing method of this application first perform a thinning process on the second shallow trench isolation structure in the flash memory cell region before the flash memory cell is fabricated, so that the top surface of the second shallow trench isolation structure is lower than the top surface of the first shallow trench isolation structure in the logic cell region. This avoids the drawback of the first shallow trench isolation structure in the logic cell region being too low due to prioritizing the needs of the flash memory cell region in related technologies. This can not only ensure the integration effect and device performance of subsequent processes in the logic cell region, but also significantly reduce the leakage risk of the overall integrated circuit of the device. Attached Figure Description

[0015] The following drawings, which are incorporated herein by reference and are used to understand this application, illustrate embodiments of the invention and their descriptions to explain the principles of the invention.

[0016] In the attached image: Figure 1A-1F A cross-sectional schematic diagram of a flash memory device obtained by sequentially implementing a manufacturing method for a flash memory device in the related art is shown.

[0017] Figure 2 A schematic diagram illustrating the decrease in coupling rate between multilayer films and floating gate layers in related technologies is shown.

[0018] Figure 3 A flowchart illustrating a method for manufacturing a semiconductor device according to one specific embodiment of this application is shown.

[0019] Figure 4A-4N This illustration shows a cross-sectional schematic diagram of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of this application. Detailed Implementation

[0020] The following description provides numerous specific details to offer a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described to avoid confusion with this application.

[0021] It should be understood that this application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of this application to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0022] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0023] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0024] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0025] In related technologies, such as Figures 1A-1F As shown, the method for manufacturing a flash memory device includes the following steps: First, such as Figure 1AAs shown, a substrate 110 is provided, which includes a logic cell region and a flash memory cell region. A pad oxide layer 121 and a pad nitride layer 122 are sequentially formed on the substrate 110. The pad oxide layer 121 and the pad nitride layer 122 together constitute a pad layer. Next, as Figure 1B As shown, in the portion of the pad layer (i.e., pad oxide layer 121 and pad nitride layer 122) corresponding to the logic cell region, a first shallow trench 131 extending to the logic cell region is etched; at the same time, in the portion of the pad layer corresponding to the flash memory cell region, a second shallow trench 132 extending to the flash memory cell region is etched. Subsequently, as Figure 1C As shown, the isolation material 140 is deposited and used to fill the first shallow trench 131 and the second shallow trench 132. After that, as Figure 1D As shown, the filled isolation material is planarized, with the nitrided layer 122 as the stop layer of the planarization process, and the excess isolation material 140 on the surface of the liner is removed. Finally, a first shallow trench isolation structure 141 is formed in the first shallow trench 131, and a second shallow trench isolation structure 142 is formed in the second shallow trench 132. Then, as Figure 1E As shown, the pad oxide layer 121 and the pad nitride layer 122 are removed sequentially by an etching process; Finally, as Figure 1F As shown, the subsequent flash memory cell fabrication process includes: depositing a gate oxide layer 151, depositing a floating gate layer 152, depositing a silicon oxide-silicon nitride-silicon oxide (ONO) multilayer film 153 (as an isolation layer between the floating gate and the control gate), depositing a control gate layer 154, and removing the gate oxide layer 151 material, the floating gate layer 152 material, the ONO multilayer film 153 material, and the control gate layer 154 material from the logic cell region.

[0026] The aforementioned flash memory cell fabrication process needs to be completed before the well region fabrication of the logic cell region. This process will affect the step height of the first shallow trench isolation structure 141 in the logic cell region.

[0027] In related technologies, the step height requirement of the second shallow trench isolation structure 142 corresponding to the flash memory cell region is usually prioritized. This results in a lower step height of the first shallow trench isolation structure 141 corresponding to the logic cell region, which in turn affects the process integration effect and device performance of the logic cell region, exacerbating the leakage current problem of the overall integrated circuit. Conversely, if the process is adjusted to retain the step height of the first shallow trench isolation structure 141 corresponding to the logic cell region, the step height of the second shallow trench isolation structure 142 corresponding to the flash memory cell region will be too high, causing a decrease in the coupling rate between the ONO multilayer film 153 and the floating gate layer 152 (e.g., ...). Figure 2 As shown, this weakens the charge control capability of the control gate layer 154 over the floating gate layer 152, ultimately leading to a degradation in the storage performance of the flash memory cell.

[0028] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0029] Example 1 Below, for reference Figure 3 A method for manufacturing a semiconductor device according to an embodiment of this application is described. For example... Figure 3 As shown, the manufacturing method includes the following steps: Step S11: Provide a substrate, the substrate including a logic cell region and a flash memory cell region; Step S12: Form a pad layer on the substrate; Step S13: A first shallow trench isolation structure extending to the logic cell region is formed in the portion of the pad layer corresponding to the logic cell region, and a second shallow trench isolation structure extending to the flash cell region is formed in the portion of the pad layer corresponding to the flash cell region. Step S14: Thin the second isolation structure so that the top surface of the second isolation structure is lower than the top surface of the first isolation structure; Step S15: Remove the padding layer; Step S16: A flash memory cell comprising a gate oxide layer, a floating gate layer 262, an isolation layer, and a control gate layer is formed on the flash memory cell region.

[0030] In this embodiment, before the flash memory cell is fabricated, the second shallow trench isolation structure in the flash memory cell region is thinned so that the top surface of the second shallow trench isolation structure is lower than the top surface of the first shallow trench isolation structure in the logic cell region. This avoids the drawback of the first shallow trench isolation structure in the logic cell region being too low due to prioritizing the needs of the flash memory cell region in related technologies. This not only ensures the subsequent process integration effect and device performance of the logic cell region, but also significantly reduces the leakage risk of the overall integrated circuit.

[0031] Furthermore, by controlling the thinning rate of the second shallow trench isolation structure to make it highly compatible with the fabrication requirements of the subsequent gate oxide layer, floating gate layer, isolation layer, and control gate layer in the flash memory cell region, the problem of reduced coupling rate between the isolation layer (such as ONO multilayer film) and the floating gate caused by excessively high steps in the second shallow trench isolation structure can be effectively avoided. This ensures the charge control capability of the control gate over the floating gate, thereby simultaneously guaranteeing the process and device performance of the logic cell region and the storage performance of the flash memory cell region, and improving the overall reliability and comprehensive performance of the semiconductor device.

[0032] The manufacturing method described above will be explained in more detail below.

[0033] First, execute step S11, as follows: Figure 4A As shown, a substrate 210 is provided, which includes a logic cell region and a flash memory cell region.

[0034] For example, the substrate 210 can be any suitable semiconductor substrate, such as a silicon substrate, or at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, including multilayer structures composed of these semiconductor materials, or silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), or it can be a double-side polished wafer (DSP), or a ceramic substrate such as alumina, a quartz or glass substrate, etc.

[0035] The logic cell area mainly forms logic cells such as NAND gates, NOR gates, and flip-flops, which are used to carry out logic operations, signal processing, and control functions of semiconductor devices. The flash memory cell area mainly forms flash memory cells including a gate oxide layer 261, a floating gate layer 262, an isolation layer 263, and a control gate layer 264, which are used to realize data storage.

[0036] Next, proceed to step S12, as follows: Figure 4B As shown, a pad layer is formed on the substrate 210.

[0037] In some embodiments, such as Figure 4B As shown, the pad layer includes a pad oxide layer 221 located on the substrate 210 and a pad nitride layer 222 located on the side of the pad oxide layer 221 away from the substrate 210.

[0038] The function of the pad oxide layer 221 is to provide stress buffer for the subsequently prepared pad nitride layer 222. If the pad nitride layer 222 is directly deposited on the surface of the substrate 210, the stress difference between the two is large, which can easily lead to dislocation defects on the surface of the substrate 210. However, the pad oxide layer 221 is located between the substrate 210 and the pad nitride layer 222, which can effectively alleviate the stress concentration at the interface, thereby avoiding the generation of dislocation defects on the surface of the substrate 210 and ensuring the structural integrity of the substrate 210.

[0039] The pad oxide layer 221 can be prepared using a furnace tube process. In terms of material, the pad oxide layer 221 is preferably silicon dioxide (SiO2), but other oxide materials that meet the requirements for insulation performance and stress buffering can also be used; this application does not limit the specific material. In terms of thickness, the thickness of the pad oxide layer 221 can be set to 110 angstroms, or it can be adjusted to other suitable thicknesses according to actual process adaptation requirements; this application does not limit the specific thickness.

[0040] Similarly, the pad nitride layer 222 can also be prepared using a furnace tube process. In terms of material, the pad nitride layer 222 is preferably silicon nitride (SiN), but other nitride materials with hard mask functionality and process compatibility can also be used; this application does not limit the specific material. In terms of thickness, the thickness of the pad nitride layer 222 can be set to 1500 angstroms, or it can be adjusted to other suitable thicknesses according to subsequent process objectives; this application does not limit the specific thickness.

[0041] It should be noted that the thickness of the nitriding layer 222 directly affects the step height of the shallow trench isolation structure subsequently prepared. Therefore, the step height of the shallow trench isolation structure can be increased by increasing the thickness of the nitriding layer 222. However, the process capability of filling the shallow trench with the isolation material 240 should also be taken into account to avoid insufficient filling of the isolation material 240 or voids in the trench due to the excessive thickness of the nitriding layer 222, which would affect the isolation performance of the shallow trench isolation structure.

[0042] Next, proceed to step S13, as follows: Figures 4C-4E As shown, a first shallow trench isolation structure 241 extending to the logic cell region is formed in the portion of the pad layer corresponding to the logic cell region, and a second shallow trench isolation structure 242 extending to the flash cell region is formed in the portion of the pad layer corresponding to the flash cell region.

[0043] In some embodiments, the first shallow trench isolation structure 241 and the second shallow trench isolation structure 242 can be prepared by the following steps S131~S133.

[0044] Step S131, as follows Figure 4C As shown, a first shallow trench 231 extending into the logic cell region is formed in the portion of the pad layer corresponding to the logic cell region, and a second shallow trench 232 extending into the flash cell region is formed in the portion of the pad layer corresponding to the flash cell region.

[0045] Specifically, the first shallow trench 231 and the second shallow trench 232 can be fabricated using photolithography. First, a photoresist mask layer is formed on the pad layer. Through exposure, development, and other processes, the photoresist mask layer is patterned to form a patterned mask layer that defines the first shallow trench 231 and the second shallow trench 232 to be formed. Then, the patterned mask layer is etched to form the first shallow trench 231 extending into the logic cell region in the portion of the pad layer corresponding to the logic cell region, and the second shallow trench 232 extending into the flash memory cell region in the portion of the pad layer corresponding to the flash memory cell region.

[0046] It should be noted that the above description is of a scheme in which the first shallow trench 231 and the second shallow trench 232 are prepared simultaneously by photolithography. However, they can also be prepared stepwise by photolithography. This application does not limit this.

[0047] For example, the first shallow trench 231 has a depth of approximately 4200 angstroms, and its inner sidewall forms an 85° slope angle with the bottom surface of the substrate 210. Of course, the depth and the inclination angle of the inner sidewall of the first shallow trench 231 can also be adjusted to other values ​​according to process requirements, and this application does not limit them. Similarly, the second shallow trench 232 has a depth of approximately 4200 angstroms, and its inner sidewall forms an 85° slope angle with the bottom surface of the substrate 210. Its depth and inclination angle can also be flexibly adjusted, and this application does not limit them.

[0048] It is worth noting that after the first shallow trench 231 and the second shallow trench 232 are formed, the remaining thickness of the pad nitride layer 222 can be maintained at a certain thickness, for example, about 1100 angstroms, so as to reserve sufficient process margin for the subsequent etch-back process of the pad nitride layer 222 and the height control of the shallow trench isolation structure.

[0049] Step S132, as follows Figure 4D As shown, the deposited isolation material 240 is used to fill the first shallow trench 231 and the second shallow trench 232.

[0050] Specifically, the isolation material 240 can be deposited using methods commonly used in the art, such as physical vapor deposition, chemical vapor deposition, or atomic layer deposition. During the deposition process, the isolation material 240 must completely fill the first shallow trench 231 and the second shallow trench 232.

[0051] In one specific embodiment, the insulating material 240 can be deposited using a high-density plasma (HDP) process.

[0052] In one specific embodiment, the deposited isolation material 240 may be an oxide, such as silicon oxide, etc. This application does not limit the specific type of isolation material 240.

[0053] Step S133, as follows Figure 4E As shown, excess insulating material 240 is removed so that the surface of the insulating material 240 is flush with the surface of the padding layer, so as to form a first shallow trench insulating structure 241 in the first shallow trench 231 and a second shallow trench insulating structure 242 in the second shallow trench 232.

[0054] Specifically, planarization can be performed using a chemical mechanical polishing (CMP) process to remove excess insulating material 240 deposited on the surface of the pad nitride layer 222.

[0055] It should be noted that, in order to avoid the problem of blocking wet etching during the subsequent removal of the pad nitride layer 222, the pad nitride layer 222 needs to be simultaneously subjected to chemical mechanical polishing to produce a certain thickness loss. For example, after chemical mechanical polishing, the thickness of the pad nitride layer 222 can be maintained at about 1000 angstroms; of course, it can also be adjusted to other thicknesses according to actual process requirements, and this application does not limit it.

[0056] Next, proceed to step S14, as follows: Figures 4F to 4G As shown, the second shallow trench isolation structure 242 is thinned so that the top surface of the second shallow trench isolation structure 242 is lower than the top surface of the first shallow trench isolation structure 241.

[0057] In some embodiments, the thinning of the second shallow trench isolation structure 242 so that its top surface is lower than the top surface of the first shallow trench isolation structure 241 can be achieved through the following steps S141~S142: Step S141, as follows Figure 4F As shown, a first mask layer 250 is formed, which covers the first shallow trench isolation structure 241 and a portion of the logic cell region corresponding to the pad layer.

[0058] Specifically, the process of forming the first mask layer 250 may include: coating a photoresist material onto the portion of the first shallow trench isolation structure 241 and the corresponding logic cell region of the pad layer; exposing the coated photoresist material; and forming the first mask layer 250 after development. This first mask layer 250 completely covers the first shallow trench isolation structure 241 and also covers the entire area of ​​the corresponding logic cell region in the pad layer, ensuring that the portion of the first shallow trench isolation structure 241 and the corresponding logic cell region of the pad layer is not etched in subsequent etching processes; while the portion of the second shallow trench isolation structure 242 and the portion of the pad layer corresponding to the flash memory cell region is completely exposed, providing a process window for subsequent thinning etching of the second shallow trench isolation structure 242.

[0059] It should be noted that before forming the pad layer on the substrate 210, a well region can also be formed in the flash memory cell region of the substrate 210. The same photomask (i.e., the same mask plate) can be used to form the first mask layer 250 and the well region of the flash memory cell region.

[0060] Step S142, as follows Figure 4G As shown, based on the first mask layer 250, a portion of the thickness of the second shallow trench isolation structure 242 is etched away so that the top surface of the second shallow trench isolation structure 242 is lower than the top surface of the first shallow trench isolation structure 241.

[0061] Specifically, with the protection of the first mask layer 250, the second shallow trench isolation structure 242 is thinned using a dry etching process or a wet etching process.

[0062] Taking the thinning of the second shallow trench isolation structure 242 using a dry etching process as an example, a fluorine-containing gas can be used as the etching source. Under preset RF power and chamber pressure conditions, active fluorine ions generated by plasma are used to etch the exposed second shallow trench isolation structure 242. During the etching process, the first mask layer 250 completely blocks the erosion of the logic cell region by the etching ions, ensuring that the first shallow trench isolation structure 241 and the corresponding logic cell region of the pad layer are not damaged. In addition, the etching depth can be monitored in real time by optical endpoint detection, and the thickness of the removed second shallow trench isolation structure 242 can be precisely controlled until its top surface is lower than the top surface of the first shallow trench isolation structure 241, ultimately forming a height difference between the two isolation structures, laying the foundation for the height matching of the subsequent floating gate material layer 2621 and the shallow trench isolation structure.

[0063] Taking the thinning of the second shallow trench isolation structure 242 using a wet etching process as an example, an etching solution with a high selectivity for the material of the second shallow trench isolation structure 242, such as hydrofluoric acid etching solution, can be selected. During etching, the device is immersed in the etching solution. The etching solution only reacts chemically with the exposed second shallow trench isolation structure 242 and gradually dissolves the structure to achieve thinning. The first mask layer 250 isolates the etching solution from contact with the logic cell area, thereby protecting the first shallow trench isolation structure 241 and the corresponding pad layer from corrosion. To control the etching amount, the top surface of the second shallow trench isolation structure 242 is lower than that of the first shallow trench isolation structure 241 by real-time monitoring of the etching solution concentration, setting a fixed etching time, or monitoring the structure height with an optical thickness detection device. This ensures that the target height difference between the two isolation structures is formed, laying the foundation for the height matching of the subsequent floating gate material layer 2621 and the shallow trench isolation structure.

[0064] For example, the thickness of the second shallow trench isolation structure 242 etched away is about 150 angstroms, but it can be adjusted to other suitable values ​​according to actual process requirements. This application does not limit this.

[0065] After etching, the first mask layer 250 can be removed by processes such as stripping or ashing to completely remove the photoresist covering the first shallow trench isolation structure 241 and the corresponding logic unit area of ​​the pad layer.

[0066] This embodiment forms a first mask layer 250 covering the first shallow trench isolation structure 241 and the corresponding logic cell region of the pad layer, and then etches a second shallow trench isolation structure 242 based on the first mask layer 250 to remove part of its thickness to form a height difference. Compared with related technologies, this embodiment effectively balances the step height difference of the shallow trench isolation structure between the logic cell region and the flash memory cell region by introducing only one photolithography and etching process. This allows the first shallow trench isolation structure 241 in the logic cell region to meet its own process integration and device electrical requirements, and the second shallow trench isolation structure 242 in the flash memory cell region to adapt to the electrical requirements of its flash memory cell fabrication, thereby significantly reducing the leakage risk of the overall integrated circuit.

[0067] Moreover, although this embodiment requires an additional layer of photoresist, it does not require an additional photomask. The photomask used can be the same as the photomask used to fabricate the trap region in the flash memory cell area. This avoids the cost increase caused by adding a photomask and does not increase the complexity of the process. It balances process economy and feasibility while ensuring the overall performance of the device.

[0068] Next, proceed to step S15, as follows: Figure 4H As shown, the padding layer is removed.

[0069] In some embodiments, the pad layer includes a pad nitride layer 222 and a pad oxide layer 221, and the step of removing the pad layer includes: sequentially removing the pad nitride layer 222 and the pad oxide layer 221 to expose the surface of the substrate 210.

[0070] For example, the pad nitride layer 222 is first removed using a wet etching process. Specifically, a wet etching solution with a high selectivity for the pad nitride layer 222, such as hot phosphoric acid, can be used to remove the pad nitride layer 222 located above the pad oxide layer 221, thereby exposing the surface of the pad oxide layer 221.

[0071] At this point, the first shallow trench isolation structure 241 and the second shallow trench isolation structure 242 become prominent. For example, the height of the first shallow trench isolation structure 241 relative to the surface of the pad oxide layer 221 is approximately 950 angstroms, and the height of the second shallow trench isolation structure 242 relative to the surface of the pad oxide layer 221 is approximately 800 angstroms; of course, the heights of both can be adjusted to other suitable values ​​according to actual process requirements, and this application does not limit this.

[0072] Subsequently, a wet etching process is used to remove the pad oxide layer 221. Specifically, a suitable wet etching solution such as hydrofluoric acid can be used to remove the pad oxide layer 221 located on the surface of the substrate 210, ultimately exposing the surface of the substrate 210.

[0073] Next, proceed to step S16, as follows: Figures 4I to 4N As shown, a flash memory cell comprising a gate oxide layer 261, a floating gate layer 262, an isolation layer 263, and a control gate layer 264 is formed on the flash memory cell region.

[0074] Specifically, a gate oxide layer 261 and a floating gate layer 262 may be sequentially formed on the exposed surface of the flash memory cell region after the pad layer is removed, and an isolation layer 263 covering the second shallow trench isolation structure 242 and the floating gate layer 262 and a control gate layer 264 located on the isolation layer 263 may be formed to form a flash memory cell including the gate oxide layer 261, the floating gate layer 262, the isolation layer 263 and the control gate layer 264.

[0075] It is worth noting that during the fabrication of flash memory cells, the height of the first shallow trench isolation structure 241 in the logic cell region will be appropriately reduced due to the associated effects of subsequent common process steps such as photolithography, etching, or planarization. However, even with this process-related loss, after all fabrication steps are completed, the final height of the first shallow trench isolation structure 241 in the logic cell region is still significantly improved compared to the lower height in related technologies caused by prioritizing the needs of the flash memory cell region. This ensures the integration effect and device performance of subsequent processes in the logic cell region, and also significantly reduces the leakage risk of the overall integrated circuit.

[0076] In some embodiments, a gate oxide layer 261 and a floating gate layer 262 are sequentially formed on the exposed surface of the flash memory cell region after the pad layer is removed, and an isolation layer 263 covering the second shallow trench isolation structure 242 and the floating gate layer 262 and a control gate layer 264 located on the isolation layer 263 are formed, including the following steps S161 to S165: Step S161, as follows Figures 4I to 4K As shown, a gate oxide layer 261 and a floating gate layer 262 are sequentially formed on the surface of the substrate 210 exposed after the pad layer is removed. The top surface of the floating gate layer 262 in the logic cell region is higher than the top surface of the first shallow trench isolation structure 241, and the top surface of the floating gate layer 262 in the flash memory cell region is higher than the top surface of the second shallow trench isolation structure 242.

[0077] For example, such as Figure 4IAs shown, after the pad layer is removed and the surface of the substrate 210 is exposed, a gate oxide layer 261 is first grown on the surface of the substrate 210. The gate oxide layer 261 uniformly covers the exposed surface of the substrate 210 in the logic cell region and the flash memory cell region, forming an insulating interface between the subsequently formed floating gate and the substrate 210.

[0078] In one specific embodiment, the gate oxide layer 261 can be grown on the surface of the substrate 210 using an in-situ vapor generation (ISSG) process, or other suitable processes that meet the process requirements. This application does not limit this. The thickness of the grown gate oxide layer 261 can be set to 80 angstroms, or other suitable thicknesses that meet the insulation performance requirements. This application does not limit this.

[0079] For example, such as Figure 4I As shown, a floating gate material layer 2621 is then deposited on the gate oxide layer 261. The floating gate material layer 2621 is undoped polysilicon or any other suitable material, and its deposition thickness covers the top surface of the first shallow trench isolation structure 241 and the second shallow trench isolation structure 242.

[0080] In one specific embodiment, a furnace tube deposition process can be used to deposit a floating gate material layer 2621 on the gate oxide layer 261. Other suitable processes with thin film uniformity can also be used, and this application does not limit the specific process. The thickness of the deposited floating gate material layer 2621 can be set to 1750 angstroms, or it can be set to other suitable thicknesses to meet subsequent planarization requirements, and this application does not limit the specific process.

[0081] For example, such as Figure 4J As shown, the floating gate material layer 2621 is then planarized using a chemical mechanical polishing process. The top surfaces of the first shallow trench isolation structure 241 and the second shallow trench isolation structure 242 are used as polishing stop layers for the logic cell region and the flash memory cell region, respectively. Finally, the top surface of the floating gate material layer 2621 in the logic cell region is flush with the top surface of the first shallow trench isolation structure 241, and the top surface of the floating gate material layer 2621 in the flash memory cell region is flush with the top surface of the second shallow trench isolation structure 242, so as to form a floating gate layer 262 on the gate oxide layer 261, providing a flat and highly matched substrate for the subsequent fabrication of the gate structure.

[0082] Among them, after the floating gate material layer 2621 is chemically mechanically polished, the thickness of the remaining floating gate layer 262 corresponding to the logic cell region can be set to 750 angstroms, and the thickness of the remaining floating gate layer 262 corresponding to the flash memory cell region can be set to 600 angstroms, or it can be set to a suitable thickness to match the functional requirements of other regions. This application does not limit this.

[0083] For example, such as Figure 4KAs shown, after the floating gate layer 262 is fabricated, the first shallow trench isolation structure 241 and the second shallow trench isolation structure 242 are etched back so that the top surface of the first shallow trench isolation structure 241 is lower than the top surface of the floating gate layer 262 in the logic cell region, and the top surface of the second shallow trench isolation structure 242 is lower than the top surface of the floating gate layer 262 in the flash memory cell region.

[0084] Specifically, the back etching can employ a wet etching process, using an etching solution to reduce the height of the first shallow trench isolation structure 241 and the second shallow trench isolation structure 242. After wet etching, the top surface of the first shallow trench isolation structure 241 can be 150 angstroms lower than the surface of the floating gate layer 262 corresponding to the logic cell region, and the top surface of the second shallow trench isolation structure 242 can be 150 angstroms lower than the surface of the floating gate layer 262 corresponding to the flash memory cell region. Alternatively, other suitable height differences can be adjusted according to subsequent device integration requirements; this application does not limit this adjustment.

[0085] It should be noted that before performing back etching on the shallow trench isolation structure using wet etching, an optional dry etching step can be performed first to remove a portion of the thickness of the floating gate layer 262 to adjust its final thickness. For example, the thickness of the portion of the floating gate layer 262 corresponding to the logic cell region can be reduced from 750 angstroms to 550 angstroms after dry etching; the thickness of the portion of the floating gate layer 262 corresponding to the flash memory cell region can be reduced from 600 angstroms to 400 angstroms after dry etching. It can also be adjusted to other suitable thicknesses according to actual process objectives, and this application does not limit this.

[0086] Step S162, as follows Figure 4L As shown, an isolation layer 263 is formed covering the floating grid layer 262, the first shallow trench isolation structure 241, and the second shallow trench isolation structure 242.

[0087] The isolation layer 263 serves as the electrical isolation medium between the floating gate layer 262 and the subsequent control gate layer 264. It must completely cover all exposed surfaces of the floating gate layer 262, the first shallow trench isolation structure 241, and the second shallow trench isolation structure 242 to achieve insulation isolation between the floating gate layer 262 and the control gate layer 264, while ensuring the charge coupling efficiency between them.

[0088] In specific preparation, commonly used methods in the field (such as physical vapor deposition, chemical vapor deposition or atomic layer deposition) can be used to deposit the isolation layer 263 material, thereby forming the isolation layer 263; the selected process must take into account the film uniformity and step coverage of the isolation layer 263 to ensure that it can form a continuous and dense film on different structural surfaces.

[0089] In one specific embodiment, the isolation layer 263 is preferably a silicon oxide-silicon nitride-silicon oxide (ONO) multilayer film structure: the bottom silicon oxide film directly contacts the floating gate layer 262, which can reduce surface damage to the floating gate layer 262 and improve interfacial adhesion; the middle silicon nitride film serves as charge storage and isolation layer 263, effectively blocking charge migration and preventing leakage; the top silicon oxide film provides a flat and insulating substrate for the subsequent deposition of the control gate layer 264. Of course, the isolation layer 263 can also be made of other suitable materials that meet the requirements of insulation performance and charge coupling, and this application does not limit this.

[0090] Step S163, as follows Figure 4L As shown, a control gate layer 264 is formed on the isolation layer 263; Exemplarily, the control gate layer 264 can be formed using methods commonly used in the art, such as physical vapor deposition, chemical vapor deposition, or atomic layer deposition, to deposit the control gate layer 264 material on the isolation layer 263. The control gate layer 264 material is preferably undoped polysilicon, but other suitable materials that meet conductivity and process compatibility requirements may also be selected; this application does not limit the choice of material.

[0091] The thickness of the control gate layer 264 can be controlled to be approximately 730 angstroms, or it can be adjusted to other suitable values ​​according to the requirements of subsequent etching processes and device performance targets (such as the charge control capability of the control gate layer 264 over the floating gate layer 262). This application does not limit this value.

[0092] Step S164, as follows Figure 4L As shown, a second mask layer 272 is formed, which covers a portion of the control gate layer 264 corresponding to the flash memory cell region; Specifically, the process of forming the second mask layer 272 may include: coating a portion of the control gate layer 264 corresponding to the flash memory cell region with photoresist material, exposing the coated photoresist material, and forming the second mask layer 272 after development. This second mask layer 272 completely covers the portion of the control gate layer 264 corresponding to the flash memory cell region, ensuring that this portion is not etched during subsequent etching processes; while the portion of the control gate layer 264 corresponding to the logic cell region is fully exposed, providing a process window for subsequent etching.

[0093] Step S165, as follows Figures 4M~4N As shown, based on the second mask layer 272, the portion of the control gate layer 264 corresponding to the logic cell region, the portion of the isolation layer 263 corresponding to the logic cell region, and the portion of the floating gate layer 262 corresponding to the logic cell region are sequentially etched away.

[0094] Specifically, with the protection of the second mask layer 272, dry or wet etching processes are used to sequentially etch away the portions of the control gate layer 264 corresponding to the logic cell region, the isolation layer 263 corresponding to the logic cell region, and the floating gate layer 262 corresponding to the logic cell region. During the etching process, the second mask layer 272 completely blocks the erosion of the flash memory cell region by etching ions or wet etching solution.

[0095] After etching, the second mask layer 272 can be removed by processes such as stripping or ashing to completely remove the photoresist covering the portion of the flash memory cell area corresponding to the control gate layer 264.

[0096] It is worth noting that, in order to avoid damage to the control gate layer 264 of the flash memory cell region in subsequent processes, such as Figure 4L As shown, a hard mask layer 271 can be prepared on the surface of the control gate layer 264 before forming the second mask layer 272. In step S165, as... Figure 4M and Figure 4N As shown, only the portion of the hard mask layer 271 corresponding to the logic cell region is removed, while the portion corresponding to the flash memory cell region is retained. This retained portion of the hard mask layer 271 can reliably protect the control gate layer 264 of the flash memory cell region, thereby effectively avoiding subsequent processes from eroding or damaging the control gate layer 264 in this region and ensuring the performance stability of the control gate layer 264.

[0097] For example, the thickness of the hard mask layer 271 formed on the surface of the control gate layer 264 can be 1250 angstroms, or it can be adjusted to other suitable thicknesses according to actual process objectives. This application does not limit this.

[0098] For example, after completing the above steps to form a flash cell on the flash cell region, the step height of the first shallow trench isolation structure 241 in the logic cell region is adjusted to 900-1000 angstroms, and the step height of the second shallow trench isolation structure 242 in the flash cell region is adjusted to 700-900 angstroms. It can also be adjusted to other suitable thicknesses according to the actual process target, and this application does not limit it.

[0099] In addition, subsequent steps may include forming logic units such as NAND gates, NOR gates, and flip-flops on the logic unit area, which will not be elaborated here.

[0100] This concludes the description of the key steps in the semiconductor device manufacturing method of this application. The complete semiconductor device manufacturing method may also include other steps, which will not be elaborated here. It is worth mentioning that the order of the above steps can be adjusted without conflict.

[0101] In summary, the semiconductor device manufacturing method of this application embodiment first performs a thinning process on the second shallow trench isolation structure 242 in the flash memory cell region before the flash memory cell is prepared, so that the top surface of the second shallow trench isolation structure 242 is lower than the top surface of the first shallow trench isolation structure 241 in the logic cell region. This avoids the disadvantage in related technologies where the step height of the first shallow trench isolation structure 241 in the logic cell region is too low due to prioritizing the adaptation to the needs of the flash memory cell region. This can not only ensure the subsequent process integration effect and device performance of the logic cell region, but also significantly reduce the leakage risk of the overall integrated circuit of the device.

[0102] Example 2 This application also provides a semiconductor device. It is understood that the semiconductor device in this embodiment can be manufactured by the method in the aforementioned embodiment one. In order to avoid repetition, only a brief description is given for the same components and structures as in the aforementioned embodiment one. For specific explanations and descriptions, please refer to the description in embodiment one.

[0103] In some embodiments, the semiconductor device in this embodiment is a flash memory device.

[0104] Based on the above description, according to the semiconductor device and manufacturing method of the present application embodiment, before the flash memory cell is prepared, the second shallow trench isolation structure of the flash memory cell region is thinned so that the top surface of the second shallow trench isolation structure is lower than the top surface of the first shallow trench isolation structure of the logic cell region. This avoids the disadvantage of the first shallow trench isolation structure of the logic cell region being too low due to prioritizing the needs of the flash memory cell region in the related technology. This can not only ensure the subsequent process integration effect and device performance of the logic cell region, but also significantly reduce the leakage risk of the overall integrated circuit of the device.

[0105] Although exemplary embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above exemplary embodiments are merely illustrative and are not intended to limit the scope of this application. Various changes and modifications can be made therein by those skilled in the art without departing from the scope and spirit of this application. All such changes and modifications are intended to be included within the scope of this application as claimed in the appended claims.

[0106] Similarly, it should be understood that, in order to simplify this application and aid in understanding one or more aspects of the application, various features of this application may sometimes be grouped together in a single embodiment, figure, or description thereof in the description of exemplary embodiments of this application. However, this approach should not be construed as reflecting an intention that the claimed application requires more features than are expressly recited in each claim. Rather, as reflected in the corresponding claims, the point of application is that the corresponding technical problem can be solved with fewer features than all of a single disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of this application.

[0107] Furthermore, those skilled in the art will understand that although some embodiments described herein include certain features but not others included in other embodiments, combinations of features from different embodiments are intended to be within the scope of this application and form different embodiments. For example, in the claims, any one of the claimed embodiments can be used in any combination.

[0108] It should be noted that the above embodiments are illustrative of this application and not limiting of it, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, The manufacturing method includes: A substrate is provided, the substrate including a logic cell region and a flash memory cell region; A pad layer is formed on the substrate; A first shallow trench isolation structure extending to the logic cell region is formed in the portion of the pad layer corresponding to the logic cell region, and a second shallow trench isolation structure extending to the flash memory cell region is formed in the portion of the pad layer corresponding to the flash memory cell region. The second shallow trench isolation structure is thinned so that the top surface of the second shallow trench isolation structure is lower than the top surface of the first shallow trench isolation structure; Remove the liner layer; A flash memory cell comprising a gate oxide layer, a floating gate layer, an isolation layer, and a control gate layer is formed on the flash memory cell region.

2. The manufacturing method as described in claim 1, characterized in that, The second shallow trench isolation structure is thinned so that the top surface of the second shallow trench isolation structure is lower than the top surface of the first shallow trench isolation structure, including: A first mask layer is formed, which covers the first shallow trench isolation structure and the portion of the pad layer corresponding to the logic cell region; Based on the first mask layer, a portion of the thickness of the second shallow trench isolation structure is etched away so that the top surface of the second shallow trench isolation structure is lower than the top surface of the first shallow trench isolation structure.

3. The manufacturing method as described in claim 2, characterized in that, The manufacturing method further includes the step of forming a trap region in the flash memory cell region, and the same photomask is used to form the first mask layer and to form the trap region in the flash memory cell region.

4. The manufacturing method as described in claim 2 or 3, characterized in that, The second shallow trench isolation structure with a portion of its thickness is removed by a dry etching process using fluorine-containing gas, or by a wet etching process.

5. The manufacturing method as described in claim 1, characterized in that, The pad layer includes a pad oxide layer on the substrate and a pad nitride layer on the side of the pad oxide layer away from the substrate.

6. The manufacturing method as described in claim 1, characterized in that, The method of forming a first shallow trench isolation structure extending to the logic cell region in the portion of the pad layer corresponding to the logic cell region, and forming a second shallow trench isolation structure extending to the flash memory cell region in the portion of the pad layer corresponding to the flash memory cell region, includes: A first shallow trench extending into the logic cell region is formed in the portion of the padding layer corresponding to the logic cell region, and a second shallow trench extending into the flash memory cell region is formed in the portion of the padding layer corresponding to the flash memory cell region. Deposit insulating material to fill the first shallow trench and the second shallow trench; Remove excess insulating material so that the surface of the insulating material is flush with the surface of the liner layer, thereby forming a first shallow trench insulating structure in the first shallow trench and a second shallow trench insulating structure in the second shallow trench.

7. The manufacturing method as described in claim 1, characterized in that, The formation of a flash memory cell comprising a gate oxide layer, a floating gate layer, an isolation layer, and a control gate layer on the flash memory cell region includes: After the padding layer is removed, a gate oxide layer and a floating gate layer are sequentially formed on the exposed surface of the flash memory cell region, and an isolation layer covering the second shallow trench isolation structure and the floating gate layer, as well as a control gate layer located on the isolation layer, are formed.

8. The manufacturing method as described in claim 7, characterized in that, The exposed surface of the flash memory cell region after removing the pad layer is sequentially formed with a gate oxide layer and a floating gate layer, and an isolation layer covering the second shallow trench isolation structure and the floating gate layer, and a control gate layer located on the isolation layer, including: A gate oxide layer and a floating gate layer are sequentially formed on the exposed substrate surface after the pad layer is removed. The top surface of the floating gate layer in the logic cell region is higher than the top surface of the first shallow trench isolation structure, and the top surface of the floating gate layer in the flash memory cell region is higher than the top surface of the second shallow trench isolation structure. An isolation layer is formed covering the floating grid layer, the first shallow trench isolation structure, and the second shallow trench isolation structure; A control gate layer is formed on the isolation layer; A second mask layer is formed, which covers the portion of the control gate layer corresponding to the flash memory cell region; Based on the second mask layer, the portion of the control gate layer corresponding to the logic cell region, the portion of the isolation layer corresponding to the logic cell region, and the portion of the floating gate layer corresponding to the logic cell region are sequentially etched away.

9. The manufacturing method as described in claim 8, characterized in that, The process involves sequentially forming a gate oxide layer and a floating gate layer on the substrate surface exposed after removing the pad layer, wherein the top surface of the floating gate layer in the logic cell region is higher than the top surface of the first shallow trench isolation structure, and the top surface of the floating gate layer in the flash memory cell region is higher than the top surface of the second shallow trench isolation structure, including: A gate oxide layer and a floating gate layer are sequentially formed on the exposed substrate surface, and the top surface of the floating gate layer is flush with the top surface of the first shallow trench isolation structure in the logic cell region, and the top surface of the floating gate layer is flush with the top surface of the second shallow trench isolation structure in the flash memory cell region. The first shallow trench isolation structure and the second shallow trench isolation structure are etched back so that the top surface of the first shallow trench isolation structure is lower than the top surface of the floating gate layer in the logic cell region, and the top surface of the second shallow trench isolation structure is lower than the top surface of the floating gate layer in the flash memory cell region.

10. A semiconductor device, characterized in that, Manufactured by the method of manufacturing a semiconductor device according to any one of claims 1 to 9.

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