DRAM (Dynamic Random Access Memory) double-particle stacked packaging structure and packaging process
By using a dual-chip stacked DRAM packaging structure and packaging process, the problems of secondary capacity expansion of old DRAM chips and collaborative operation of heterogeneous capacity chips are solved, realizing resource reuse and performance stability, and meeting the diversified needs of the market.
Patent Information
- Application Number
- CN202511707345.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-20
- Publication Date
- 2026-02-17
AI Technical Summary
Existing technologies make it difficult to achieve secondary capacity expansion of pre-packaged low-capacity, outdated DRAM chips and collaborative operation of heterogeneous capacity chips, resulting in resource waste and unmet market demands.
The DRAM dual-chip stacked packaging structure is adopted, in which thinned DRAM chips are bonded back to back with thermally and electrically conductive adhesive, circuit interconnection is achieved by bonding wires, and external circuits are connected through the molding area and solder balls. The complete package is formed by combining SMT soldering and reflow soldering processes.
It enables the reuse of old chips, supports mixed capacity combinations, meets diverse market demands, has a simple and reliable process, avoids resource waste, and ensures stable chip performance.
Smart Images
Figure CN121548049A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor storage technology, specifically to a DRAM dual-chip stacked packaging structure and packaging process. Background Technology
[0002] As DRAM chip technology continues to advance, on the one hand, 16Gb and 24Gb capacities for single DRAM chips have become mainstream, with 32Gb already entering the market, and 64Gb and 128Gb to be launched in the near future. On the other hand, flagship consumer devices (mobile phones / PCs) are increasingly adopting 24GB to 32GB of storage, with 8GB to 16GB becoming the "bottom line" for ensuring smooth multitasking and intelligent applications in the next generation of devices. This rapid technological iteration is leading to the obsolescence of older DRAM chips such as 4Gb / 8Gb, while the actual lifespan of these chips can reach 10 years; direct disposal would result in a serious waste of resources.
[0003] Currently, existing technologies for DRAM chip packaging capacity expansion typically operate at the bare chip level, expanding capacity by packaging multiple bare chips of the same capacity into a single chip. This approach cannot perform secondary capacity expansion on already packaged, low-capacity, older chip chips. Furthermore, traditional packaging technologies suffer from compatibility issues, making it difficult to achieve collaborative operation of heterogeneous capacity chips and failing to meet market demands for mixed-capacity combinations.
[0004] Therefore, we propose a DRAM dual-chip stacked packaging structure and packaging process. Summary of the Invention
[0005] The purpose of this invention is to provide a DRAM dual-chip stacked packaging structure and packaging process, which solves the problems mentioned in the background art.
[0006] To achieve the above objectives, the present invention provides the following technical solution: a DRAM dual-chip stacked packaging structure, comprising a first DRAM chip, a second DRAM chip, adhesive, a first substrate, a second substrate, bonding wires, a molding compound area, and solder balls; both the first DRAM chip and the second DRAM chip are chips that have undergone thinning treatment by polishing the molding compound surface, and the polished surfaces of the two chips are fixed back-to-back by the adhesive; the side of the first DRAM chip away from the bonding surface is soldered to the first substrate, and the side of the second DRAM chip away from the bonding surface is soldered to the second substrate; the bonding wires respectively connect the first substrate and the second substrate, the first DRAM chip and the first substrate, and the second DRAM chip and the second substrate to realize the circuit interconnection between the first DRAM chip and the second DRAM chip; the molding compound area wraps the first DRAM chip, the second DRAM chip, the connection part of the adhesive, the bonding wires, and part of the first substrate and the second substrate, for physical protection of the internal structure; the solder balls are disposed on the surface of the first substrate and the second substrate away from the chip, for realizing the electrical connection between the packaging structure and the external circuit.
[0007] In a preferred embodiment of the present invention, the first DRAM chip and the second DRAM chip are DRAM chips with different capacities, including a combination of 4Gb and 8Gb.
[0008] In a preferred embodiment of the present invention, after the first DRAM chip and the second DRAM chip are polished, their surfaces still retain a plastic encapsulation layer with a thickness of 0.1 to 0.3 mm to avoid damaging the effective circuit area inside the chip.
[0009] In a preferred embodiment of the present invention, the adhesive is a thermally and electrically conductive adhesive, and is cured by baking at 120-150°C for 60-90 minutes to ensure that the first DRAM chip and the second DRAM chip are firmly bonded and achieve heat conduction.
[0010] In a preferred embodiment of the present invention, the bonding wire is made of any one of gold wire, silver wire or copper wire.
[0011] In a preferred embodiment of the present invention, the material of the encapsulation area is epoxy resin encapsulating material, and it is cured and molded at high temperature.
[0012] In a preferred embodiment of the present invention, the solder ball has a diameter of 0.3 to 0.5 mm and is fixed to the surface of the first substrate and the second substrate by a reflow soldering process.
[0013] This invention also relates to a DRAM dual-chip stacked packaging process, comprising the following method steps:
[0014] Step 1: Select the first and second DRAM chips to be recycled, and perform performance testing on both chips to ensure that there is no physical damage or performance failure.
[0015] Step 2: Use a polishing device to polish and thin the plastic seal of the first DRAM chip and the second DRAM chip, and control the particle surface to retain a plastic seal layer of 0.1 to 0.3 mm thickness after polishing;
[0016] Step 3: Apply thermally and electrically conductive adhesive evenly to the polished surface of the first DRAM chip or the polished surface of the second DRAM chip, align the polished surfaces of the two chips back to back and bond them together, ensuring that there are no air bubbles on the bonding surface.
[0017] Step 4: Place the bonded particle components into a baking device and bake at 120-150℃ for 60-90 minutes to allow the adhesive to fully cure.
[0018] Step 5: Using SMT soldering process, solder the side of the cured first DRAM chip away from the bonding surface to the first substrate, and solder the side of the second DRAM chip away from the bonding surface to the second substrate, ensuring that there are no cold solder joints or false solder joints.
[0019] Step 6: Using wirebonding technology, gold, silver or copper wires are used as bonding wires to connect the first substrate and the second substrate, the first DRAM chip and the first substrate, and the second DRAM chip and the second substrate, respectively, to realize the circuit interconnection between the two chips.
[0020] Step 7: Place the components with completed circuit interconnection into a molding die, inject epoxy resin molding compound, and cure at high temperature to form a molding area that encapsulates the internal structure;
[0021] Step 8: Perform ball placement on the surface of the first and second substrates away from the particles, using solder balls with a diameter of 0.3 to 0.5 mm. Fix the solder balls through a reflow soldering process to obtain a complete DRAM dual-particle stacked package structure.
[0022] Compared with the prior art, the beneficial effects of the present invention are as follows:
[0023] This invention enables the reuse of old DRAM chips. For old, low-capacity DRAM chips that have already been packaged, the chip-level capacity can be expanded through stacking packaging, thus avoiding resource waste.
[0024] Supports mixed capacity combinations: Breaking through the compatibility limitations of traditional packaging technologies, it enables DRAM chips of different capacities to work together, meeting diverse market demands;
[0025] The process is simple and reliable, and the packaging process does not require complex equipment. Steps such as polishing, bonding, and bonding are easy to operate, and the original effective area of the particle is preserved to ensure stable chip performance. Attached Figure Description
[0026] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:
[0027] Figure 1 This is a schematic diagram of the adhesive coating of the present invention;
[0028] Figure 2 This is a schematic diagram of the bonding process of the present invention;
[0029] Figure 3 This is a schematic diagram of the SMT soldering process of this invention;
[0030] Figure 4 This is a schematic diagram of the bonding process of the present invention;
[0031] Figure 5 This is a schematic diagram of the plastic encapsulation process of the present invention;
[0032] Figure 6 This is a schematic diagram of the ball-planting process of the present invention. Detailed Implementation
[0033] To make the technical means, creative features, objectives and effects of this invention easier to understand, the invention will be further described below in conjunction with specific embodiments.
[0034] like Figure 1-6 As shown, a dual-chip stacked DRAM package structure includes a first DRAM chip 1, a second DRAM chip 2, adhesive 3, a first substrate 4, a second substrate 5, bonding wires 6, a molding compound area 7, and solder balls 8. Both the first DRAM chip 1 and the second DRAM chip 2 are chips whose molding surfaces have been thinned by polishing, and the polished surfaces of the two chips are bonded back-to-back by the adhesive 3. The side of the first DRAM chip 1 away from the bonding surface is soldered to the first substrate 4, and the side of the second DRAM chip 2 away from the bonding surface is soldered to the second substrate 5. The bonding wires 6 connect the first substrate 4 and the second substrate 5, the first DRAM chip 1 and the first substrate 4, and the second DRAM chip 2 and the second substrate 6, respectively, to achieve circuit interconnection between the first DRAM chip 1 and the second DRAM chip 2. The molding compound area 7 encapsulates the connection points of the first DRAM chip 1, the second DRAM chip 2, the adhesive 3, the bonding wires 6, and part of the first substrate 4 and the second substrate 5, providing physical protection for the internal structure. The solder balls 8 are disposed on the surface of the first substrate 4 and the second substrate 5 away from the chips, enabling electrical connection between the package structure and external circuitry.
[0035] The specific packaging process steps are as follows:
[0036] Particle pretreatment
[0037] The selected first DRAM chip 1 and second DRAM chip 1 are subjected to secondary performance testing. The read and write speed, storage stability and pin conductivity of the chips are verified by professional testing equipment, and unqualified chips are eliminated.
[0038] The plastic sealant on both particles was thinned using a grinding machine. The thickness of the sealant was monitored in real time during the grinding process to ensure that a 0.2mm thick sealant layer remained on the particle surface after grinding, thus avoiding damage to the internal circuitry. After grinding, a high-pressure air gun was used to remove dust from the particle surface, ensuring a clean and impurity-free surface.
[0039] Particle bonding and curing
[0040] Thermally and electrically conductive adhesive 3 is uniformly coated on the polished surface of the first DRAM chip 1, with the coating thickness controlled at 0.05mm to ensure that the adhesive covers the entire polished surface without accumulation.
[0041] The polished surface of the second DRAM chip 2 is precisely aligned with the adhesive-coated surface of the first DRAM chip 1. A vacuum bonding device is used to bond them back to back, applying a pressure of 0.3 MPa to ensure that the two chips are tightly bonded. At the same time, air bubbles on the bonding surface are expelled to ensure that there are no gaps on the bonding surface.
[0042] The bonded granular components are placed in a constant temperature baking device, and the baking temperature is set to 135℃ for 75 minutes to allow adhesive 3 to fully cure and form a strong bonded structure. After curing, the bonding strength is tested to ensure there is no peeling or loosening.
[0043] Substrate soldering and circuit interconnection
[0044] Using SMT soldering technology, the pins of the first DRAM chip 1 away from the bonding surface are aligned with the pads of the first substrate 4 after curing. The soldering is fixed by reflow soldering equipment, with the soldering temperature controlled at 220℃ and the holding time at 10 seconds. Similarly, the second DRAM chip 2 is soldered to the second substrate 5. After soldering, X-ray inspection equipment is used to check for cold solder joints and false solder joints to ensure that the solder joints have good conductivity.
[0045] Using a wirebonding bonding process, one end of a gold wire is soldered to the pin pad of the first DRAM chip 1, and the other end is soldered to the corresponding pad of the first substrate 4. Subsequently, the bonding of the second DRAM chip 2 to the second substrate 5 and the cross-substrate bonding between the first substrate 4 and the second substrate 5 are completed to realize the circuit interconnection of the two chips. The bonding pressure is controlled at 0.1MPa to ensure reliable contact at the bonding point.
[0046] Plastic sealing and ball planting
[0047] The interconnected components are placed into a custom molding die, the die cavity size of which is adapted to the overall structure of the components. Epoxy resin molding compound is injected, and the die is cured at 175°C for 90 minutes to form the molding area. The molding area must completely cover the first DRAM chip 1, the second DRAM chip 2, the adhesive 3, the bonding wire 6 connection area, and the edge areas of the two substrates to ensure that the internal structure is fully physically protected.
[0048] After molding, the surface of the substrate away from the particles is cleaned to remove any residual molding compound. Using a ball-mounting device, 0.4mm diameter solder balls (8) are precisely placed onto the substrate pads. The substrate is then placed in a reflow oven at 230℃ to ensure a firm bond between the solder balls (8) and the substrate pads. After ball mounting, visual inspection and continuity testing are performed to ensure the solder balls (8) are neatly arranged, without misalignment or cold solder joints.
[0049] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or basic characteristics. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within the present invention.
[0050] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.
Claims
1. A DRAM dual-pile-up package structure, characterized by: The application relates to a DRAM (Dynamic Random Access Memory) packaging structure and a packaging method thereof.
2. The DRAM dual-pellet stack package structure of claim 1, wherein: The first DRAM particle (1) and the second DRAM particle (2) are DRAM particles with different capacities, and the different capacities include the combination of 4Gb and 8Gb.
3. The DRAM dual-pellet stack package structure of claim 1, wherein: The first DRAM particle (1) and the second DRAM particle (2) are still provided with a plastic sealing layer with a thickness of 0.1-0.3 mm after polishing, so as to avoid damaging the effective circuit area in the particles.
4. The DRAM dual-pellet stack package structure of claim 1, wherein: The glue (3) is heat-conducting and electrically-conducting glue, and is baked at 120-150 DEG C for 60-90 minutes to be solidified, so as to ensure that the first DRAM particle (1) and the second DRAM particle (2) are firmly combined and heat conduction is realized.
5. The DRAM dual-pellet stack package structure of claim 1, wherein: The material of the bonding wire (6) is any one of gold wire, silver wire or copper wire.
6. The DRAM dual-pellet stack package structure of claim 1, wherein: The material of the plastic sealing area (7) is epoxy resin plastic sealing material, and the plastic sealing area (7) is formed through high-temperature solidification.
7. The DRAM dual-pellet stack package structure of claim 1, wherein: The diameter of the tin ball (8) is 0.3-0.5 mm, and the tin ball (8) is fixed on the surfaces of the first substrate and the second substrate through a reflow soldering process.
8. A DRAM dual-pile-up package process, suitable for the DRAM dual-pile-up package structure of any one of claims 1-7, characterized in that: The application further discloses a packaging method of the DRAM packaging structure. Step 1: selecting first DRAM particles (1) and second DRAM particles (2) to be recycled, and performing performance detection on the two particles to ensure that the particles are free of physical damage and performance failure; Step 2: polishing and thinning the plastic sealing surfaces of the first DRAM particles (1) and the second DRAM particles (2) by using a polishing device, and controlling the thickness of the plastic sealing layer reserved on the particle surfaces after polishing to be 0.1-0.3 mm; Step 3: uniformly coating heat-conducting and electrically-conducting glue (3) on the polishing surfaces of the first DRAM particles (1) and the second DRAM particles (2), aligning and combining the polishing surfaces of the two particles back to back, and ensuring that the combined surfaces are free of bubbles; Step 4: Put the bonded particle assembly into a baking device, bake at 120-150℃ for 60-90 minutes to make the glue (3) completely solidify; Step 5: Through SMT welding process, weld the solidified first DRAM particle (1) away from the bonding surface to the first substrate (4), and weld the second DRAM particle (2) away from the bonding surface to the second substrate (5), to ensure that the welding points are not false or fake; Step 6: Using wirebonding process, use gold wire, silver wire or copper wire as bonding wire (6) to connect the first substrate (4) and the second substrate (5), the first DRAM particle (1) and the first substrate (4), and the second DRAM particle (2) and the second substrate (5) respectively, to realize the circuit interconnection of the two particles; Step 7: Put the assembly with completed circuit interconnection into a plastic sealing mold, inject epoxy resin plastic sealing material, and form a plastic sealing area wrapping the internal structure through high-temperature solidification; Step 8: Perform ball planting operation on the surface of the first substrate (4) and the second substrate (5) away from the particles, use tin balls (8) with a diameter of 0.3-0.5mm, and fix the tin balls (8) through reflow soldering process to obtain a complete DRAM double-particle stacked packaging structure.