Semiconductor devices

Abstract

This disclosure relates to the field of semiconductor technology, providing a semiconductor device to address the technical problem that high-bandwidth memory technology still has significant room for improvement. The semiconductor device includes a chip stack structure, comprising: a first semiconductor chip and a second semiconductor chip stack structure stacked along a first direction; the first semiconductor chip includes a controller, a computing module, and an interface module; the controller is configured to: perform a first access operation on stored data in the second semiconductor chip stack structure and send the stored data to the interface module to allow external devices to access the stored data in the second semiconductor chip stack structure through the interface module; and perform a second access operation on the stored data in the second semiconductor chip stack structure and send the stored data to the computing module to allow the computing module to perform computational operations on the stored data. This improves integration and shortens data transmission paths, reducing bandwidth consumption and energy loss.

Description

Technical Field

[0001] This disclosure relates to semiconductor technology, and more particularly to a semiconductor device. Background Technology

[0002] With the rapid development of High Performance Computing (HPC) and Artificial Intelligence (AI) technologies, higher demands are being placed on the storage bandwidth and data processing capabilities of semiconductor devices. To meet the needs of high-frequency, high-capacity data processing, High Bandwidth Memory (HBM) has emerged. HBM, with its stacked architecture and high-speed interconnect characteristics, can efficiently match the high-frequency data access requirements of different application scenarios. However, with the explosive development of artificial intelligence and big data technologies, people's requirements for storage performance, cost, and adaptability continue to upgrade. Existing HBM technology, limited by factors such as complex packaging processes and high production costs, still has significant room for optimization and improvement. Summary of the Invention

[0003] In view of the above, this disclosure provides a semiconductor device comprising: a chip stack structure including: a first semiconductor chip and a second semiconductor chip stack structure stacked along a first direction; the first semiconductor chip being connected to the second semiconductor chip stack structure via a through-silicon via (TSV); the first semiconductor chip including a controller, a computing module, and an interface module, the controller being coupled to the computing module and the interface module respectively, and the controller also being coupled to the second semiconductor chip via a TSV; the controller being configured to: perform a first access operation on stored data in the second semiconductor chip stack structure and send the stored data to the interface module to allow an external device to access the stored data in the second semiconductor chip stack structure through the interface module; and perform a second access operation on the stored data in the second semiconductor chip stack structure and send the stored data to the computing module to allow the computing module to perform a computing operation on the stored data in the second semiconductor chip stack structure.

[0004] In some embodiments, the controller is further configured to perform a refresh operation on at least the second semiconductor chip stack structure.

[0005] In some embodiments, the first semiconductor chip further includes a test module connected to the through-silicon via; the controller is specifically configured to perform test operations on the second semiconductor chip in the second semiconductor chip stack structure through the through-silicon via.

[0006] In some embodiments, the interface module includes a first interconnect interface; wherein the controller is specifically configured to implement a first type of package of the chip stack structure using the first interconnect interface.

[0007] In some embodiments, the first interconnect interface is a die-to-die D2D interconnect interface or a chip-to-chip C2C interconnect interface.

[0008] In some embodiments, the semiconductor device includes a plurality of chip stack structures arranged in an array along a second direction and a third direction; adjacent chip stack structures are coupled through the first interconnect interface; wherein the second direction and the third direction intersect and are both perpendicular to the first direction.

[0009] In some embodiments, the semiconductor device further includes a third semiconductor chip, the third semiconductor chip including the first interconnect interface and coupled to the chip stack structure through the first interconnect interface; wherein the third semiconductor chip includes a main processor, the main processor including at least one of: a graphics processing unit, a central processing unit, or a tensor processor.

[0010] In some embodiments, the chip stack structure located on both sides of the third semiconductor chip along the second direction is axially symmetrical with respect to the third semiconductor chip.

[0011] In some embodiments, the semiconductor device further includes a packaging substrate and a packaging layer; wherein a plurality of the chip stack structures are located on the packaging substrate, and the packaging layer encapsulates the plurality of the chip stack structures.

[0012] In some embodiments, the first semiconductor chip includes a logic chip, and the second semiconductor chip includes a dynamic random access memory (DRAM) chip.

[0013] This disclosure provides a semiconductor device, including: a chip stacking structure, comprising: a first semiconductor chip and a second semiconductor chip stacking structure stacked along a first direction; the second semiconductor chip stacking structure includes a plurality of second semiconductor chips stacked sequentially along the first direction; the first semiconductor chip is connected to the second semiconductor chip stacking structure through a through-silicon via (TSV); the first semiconductor chip includes a controller, a computing module, and an interface module, the controller being coupled to the computing module and the interface module respectively, and the controller is also coupled to the second semiconductor chip through a TSV; the controller is configured to: perform a first access operation on stored data in the second semiconductor chip stacking structure and send the stored data to the interface module to allow an external device to access the stored data in the second semiconductor chip stacking structure through the interface module; and perform a second access operation on the stored data in the second semiconductor chip stacking structure and send the stored data to the computing module to allow the computing module to perform a computing operation on the stored data in the second semiconductor chip stacking structure. Thus, on the one hand, by adopting a chip stacking architecture, the first semiconductor chip integrating the controller and computing module is vertically integrated with multiple stacked second semiconductor chips along the same direction, reducing the planar area occupied, improving integration density, and shortening the data transmission path. The controller within the first semiconductor chip can directly access the stacked structure of the second semiconductor chip via through-silicon vias (TSVs), enabling access to the stored data within the stacked structure without the need for additional relay links. This significantly reduces access latency and improves instruction response speed. Furthermore, the controller of the first semiconductor chip, in conjunction with the computing module, calls upon the stored data in the second semiconductor chip to perform computational operations, constructing an integrated "storage-computing" architecture. This avoids frequent data transfer between the storage units within the chip stack and the computing modules outside the chip stack, reducing bandwidth consumption and energy loss. Moreover, by adding a controller with both storage management and computation scheduling functions to the first semiconductor chip, the hardware architecture is simplified, reducing overall cost and wiring complexity. Attached Figure Description

[0014] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0015] Figure 1 This is one of the schematic diagrams of a semiconductor device provided in an embodiment of the present disclosure;

[0016] Figure 2This is a schematic diagram of the structure of a first semiconductor chip provided in an embodiment of the present disclosure;

[0017] Figure 3 This is a second schematic diagram of the structure of a semiconductor device provided in an embodiment of the present disclosure;

[0018] Figure 4 This is the third schematic diagram of the structure of a semiconductor device provided in an embodiment of the present disclosure;

[0019] Figure 5 Fourth schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure;

[0020] Figure 6 Fifth schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure;

[0021] Figure 7 This is the sixth schematic diagram of the structure of a semiconductor device provided in an embodiment of the present disclosure. Detailed Implementation

[0022] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0023] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0024] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0025] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0026] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0027] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of features, integers, steps, operations, elements, and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0028] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0029] Chip-on-Wafer-on-Substrate (CoWoS) technology typically places multiple high-bandwidth memories and processors side-by-side on an interposer. This packaging method requires a large-area interposer, which not only accounts for a significant portion of the bill of materials (BOM) but also faces bottlenecks such as complex manufacturing processes and low yields. This, coupled with the premium effect caused by highly concentrated production capacity, leads to increased packaging costs. Meanwhile, current HBM technology is limited by the high complexity and rising manufacturing costs of CoWoS packaging processes, and still relies on external scheduling mechanisms when performing computational tasks, resulting in high data transmission and instruction response latency, significantly restricting its application efficiency in high-performance computing scenarios.

[0030] This disclosure provides a semiconductor device, such as... Figure 1 and Figure 2 As shown, the semiconductor device includes a chip stacking structure 122, comprising a first semiconductor chip 104 stacked along a first direction and a second semiconductor chip stacking structure 116; the second semiconductor chip stacking structure 116 includes a plurality of second semiconductor chips 114 stacked sequentially along the first direction; the first semiconductor chip is connected to the second semiconductor chip stacking structure through a through-silicon via 118. The first semiconductor chip 104 includes a controller 110, a computing module 108, and an interface module 106, the controller 110 being coupled to the computing module 108 and the interface module 106 respectively; the controller 110 is configured to: perform a first access operation on stored data in the second semiconductor chip stacking structure 116 and send the stored data to the interface module 106 to allow external devices to access the stored data in the second semiconductor chip stacking structure 116 through the interface module 106; and perform a second access operation on the stored data in the second semiconductor chip stacking structure 116 and send the stored data to the computing module 108 to allow the computing module 108 to perform computation operations on the stored data in the second semiconductor chip stacking structure 116.

[0031] In some embodiments, the first semiconductor chip includes a logic chip (also referred to herein as a base die) and the second semiconductor chip includes a dynamic random access memory (DRAM) chip (also referred to herein as a core die).

[0032] In some embodiments, the second semiconductor chip 114 in the second semiconductor chip stack structure 116 includes an independent memory array responsible for actual data storage. The second semiconductor chip 114 can achieve high-density stacking, for example, stacking 4 to 12 layers, with the total capacity increasing linearly with the number of stacked layers.

[0033] In this embodiment of the disclosure, the second semiconductor chip 114 may include a memory cell array and peripheral circuitry.

[0034] In this embodiment of the disclosure, the peripheral circuitry in the second semiconductor chip 114 may include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of the memory cell array. For example, the peripheral circuitry may include one or more of the following: decoders (e.g., row decoders and column decoders), input / output (I / O) circuitry, voltage sources or generators, any portion of the functional circuitry mentioned above (e.g., sub-circuits), or any active or passive component of the circuitry (e.g., transistors, diodes, resistors, or capacitors). According to some implementations, the peripheral circuitry may be implemented using complementary metal-oxide-semiconductor (CMOS) technology.

[0035] In this embodiment of the disclosure, the memory cell array in the second semiconductor chip 114 may include a DRAM memory cell array using transistors as switching and selection devices. Each memory cell includes a capacitor for storing data bits as positive or negative charges and one or more transistors (also referred to as transfer transistors) for controlling (e.g., switching and selection) access to it. In some embodiments, each DRAM cell may be a single transistor-single capacitor (1T1C) cell.

[0036] In some embodiments, the first access operation includes read and write operations of stored data in the second semiconductor chip stack structure 116 by an external device via controller 110, wherein controller 110 can be connected to an interface module via system bus 120 to implement the first access operation. The second access operation includes read and write operations of stored data in the second semiconductor chip stack structure 116 by computing module 108 via controller 110, wherein controller 110 can be connected to computing module 108 via system bus 120 to implement the second access operation.

[0037] In some implementations, the controller 110 is configured to perform a refresh operation on at least the second semiconductor chip stack structure 116. Specifically, the controller 110 may periodically perform a refresh operation on the second semiconductor chip 114 in the second semiconductor chip stack structure 116 to retain the charge stored in the memory cells and prevent data loss. Since DRAM uses capacitors to store charge to represent data, and capacitors have inherent leakage characteristics, if the charge is not replenished in time, the stored data will be lost within milliseconds. Therefore, a refresh operation is needed to periodically recharge the capacitors of the memory cells to maintain charge stability, avoid data loss, and ensure the reliable operation of the DRAM.

[0038] This embodiment of the disclosure places the controller inside the first semiconductor chip. On the one hand, the controller in the first semiconductor chip enables local management of the second semiconductor chip stack structure. Data transmission can be completed directly within the chip stack structure, significantly shortening the data transmission path, effectively reducing signal delay and loss, and significantly improving the response speed and overall efficiency of operations such as the first access operation and the second access operation. On the other hand, this layout design optimizes space utilization, efficiently integrating the controller with the chip stack structure, significantly reducing the overall footprint of the semiconductor device, eliminating the need for additional space reserved for the controller, and adapting to the miniaturization and high-density integration requirements of various electronic devices.

[0039] In some implementations, the computing module 108 includes, but is not limited to, a neural processing unit (NPU), and may also integrate a digital signal processor (DSP), a tensor processing unit (TPU), an arithmetic and logic unit (ALU), etc., according to application requirements. When an NPU is used as the core computing unit, the NPU has built-in convolution operation submodules, general matrix multiply (GEMM) submodules, and data format conversion submodules, which can directly perform neural network core operations on the stored data in the second semiconductor chip stack structure 116 without having to move the data to a computing module outside the chip stack structure.

[0040] The Von Neumann architecture, typically used in computers, consists of separate memory and processor. When instructions are executed, data is written to memory, and the processor sequentially reads instructions and data from memory, finally writing the execution results back to memory. Consequently, data is frequently transferred between the processor and memory. If the memory transfer speed cannot keep up with the processor's operating speed, the processor's computing power will be limited, thus reducing the performance of the entire computing system.

[0041] This embodiment integrates a computing module with computing capabilities within a first semiconductor chip in a chip stack structure, enabling "local computing" of data. This allows for both data computation and data storage within the chip stack structure. Since frequent data transfer between a processor outside the chip stack structure and a second semiconductor chip in the chip stack structure is eliminated, data transmission latency and power consumption are reduced, thus improving the overall performance of the computing system.

[0042] In other embodiments, the first and second access operations, along with computational operations (such as matrix multiplication and addition, convolution operations), essentially share the hardware resources of the second semiconductor chip, including its storage array, bus channels, and control logic. To avoid resource contention (such as address bus contention and memory cell read / write conflicts) caused by the parallel execution of these two types of operations, which leads to increased operation latency and data error rate, an alternating execution strategy can be adopted. This achieves temporal decoupling and resource reuse between the two types of operations: during computational operations, preparation for accessing the next batch of data is completed in advance; during access operations, the caching and verification of computation results are completed synchronously. Through precise timing scheduling, storage and computational resources are always operating at high efficiency, ultimately improving the overall system throughput and energy efficiency ratio.

[0043] In some embodiments, such as Figure 1 As shown, the multiple second semiconductor chips 114 in the second semiconductor chip stack structure 116 are connected through silicon vias 118.

[0044] In other embodiments, the plurality of second semiconductor chips 114 of the second semiconductor chip stack structure 116 are connected by hybrid bonding (HB) and through-silicon vias 118.

[0045] In some embodiments, such as Figure 1 As shown, the semiconductor device also includes a packaging substrate 100 and a packaging layer (not shown); wherein, a chip stack structure 122 is located on the packaging substrate 100, and the packaging layer encapsulates multiple chip stack structures 122.

[0046] In some implementations, such as Figure 1 As shown, the semiconductor device also includes a substrate connection bump 102, and the chip stack structure 122 achieves signal connection with the packaging substrate 100 through the substrate connection bump 102.

[0047] In some embodiments, the packaging substrate 100 may be a flexible printed circuit board (FPC) or a rigid printed circuit board (PCB), etc.

[0048] In some embodiments, the encapsulation layer includes a molding compound, and, exemplary, the material of the encapsulation layer may be made of a molding compound, a molding underfill, an epoxy molding compound, a resin, the like, or a combination thereof.

[0049] In some embodiments, the first semiconductor chip 104 further includes a test module 112 connected to a through-silicon via 118; the controller 110 is specifically configured to perform test operations on the second semiconductor chip 114 in the second semiconductor chip stack structure 116 through the through-silicon via 118.

[0050] In some implementations, the test module 112 includes, but is not limited to, self-test logic, which can independently perform Known Good Stacked Die (KGSD) testing and wafer screening operations on the target chip via a through-silicon via (TSV) interface. Thus, by integrating the self-test logic into the first semiconductor chip within the chip stack structure, accurate testing of multiple second semiconductor chips can be achieved locally, without relying on external large-scale testing equipment, shortening the testing path and reducing testing latency. It can quickly identify faulty chips during the chip stacking stage, promptly remove defective components, avoid the cost waste caused by overall scrapping after subsequent packaging, and significantly improve product yield. Simultaneously, it optimizes the spatial layout, eliminates the need for additional external testing space in the chip stack structure, simplifies the testing process, effectively reduces testing costs, and improves testing efficiency.

[0051] In some implementations, testing operations include, but are not limited to, low-speed direct current (DC) testing, high-speed alternating current (AC) testing, and functional testing. Low-speed DC testing verifies the static electrical parameters of the DRAM chip by applying a constant DC voltage / current and detecting parameters such as leakage current, withstand voltage, pin drive capability, short-circuit / open-circuit faults, and threshold voltage. High-speed AC testing verifies the dynamic performance and timing consistency of the DRAM chip at its actual operating frequency by applying a high-frequency AC signal to simulate real-world operating scenarios and detecting indicators such as signal transmission delay, setup / hold time, frequency response, read / write timing margin, and signal crosstalk. Functional testing verifies the normal operation of the core logic functions of the DRAM memory array, such as data read / write and hold. A preset test pattern (checkerboard, all 0s / all 1s, etc.) is written to a specified memory cell, and the data is read and compared with the original pattern to determine whether the memory cell has fixed faults, coupled faults, address decoding faults, or other logical failures.

[0052] In this way, the test module 112 is compatible with test operations of different test modes, realizing comprehensive test coverage of various typical failure modes of DRAM chips, and ensuring the functional reliability and yield screening accuracy of the chips.

[0053] In some embodiments, such as Figure 1 and Figure 2 As shown, the interface module 106 includes a first interconnect interface; wherein, the controller 110 is specifically configured to: implement a first type of package of the chip stack structure 122 using the first interconnect interface.

[0054] Here, the interface module 106 enables the external device 121 to access local data (e.g., stored data of the second semiconductor chip).

[0055] In some embodiments, the first interconnect interface is a die-to-die (D2D) interconnect interface or a chip-to-chip (C2C) interconnect interface.

[0056] In some implementations, when the first interconnect interface is a die-to-die (D2D) interconnect interface, the connection object of the first interconnect interface is an unpackaged die. It can be precisely docked with the redistribution layer (RDL) on the surface of the silicon interposer through technologies such as microbumps and hybrid bonding, so as to meet the high bandwidth and low latency communication requirements between dies in 2.5D packaging.

[0057] In some implementations, when the first interconnect interface is a chip-to-chip (C2C) interconnect interface, the connection object of the first interconnect interface is a chip that has been fully packaged. It does not need to rely on a silicon interposer and can directly realize data interaction between chips through the I / O pins of the packaging substrate, on-board wiring, etc., which fits the application scenarios of traditional packaging.

[0058] The two interface types of the first interconnect interface can be flexibly selected according to the technical specifications of the package type (such as interconnect density, transmission bandwidth, and power consumption budget). Through flexible package support, different application scenarios can be adapted, thereby achieving a balance between performance and cost of different package solutions.

[0059] In some embodiments, such as Figure 6 and Figure 7 As shown, the semiconductor device includes multiple chip stack structures 122 arranged in an array along a second direction and a third direction; adjacent chip stack structures 122 are coupled through a first interconnect interface to form a computing chip mesh network; wherein the second direction and the third direction intersect and are both perpendicular to the first direction.

[0060] In some implementations... Figure 6 and Figure 7As shown, each chip stack structure 122 integrates a computing module within its first semiconductor chip. This computing module can establish high-speed data interaction links with computing modules in other chip stack structures within the array via a mesh network of computing chips, supporting task scheduling and data sharing among multiple nodes, thereby achieving large-scale distributed collaborative computing. This architecture breaks down the boundaries of single-chip computing power, integrating dispersed computing resources into a unified computing power cluster through die-level mesh interconnection. It can efficiently adapt to application scenarios with stringent requirements for computing power and bandwidth, such as AI large-scale model training and high-performance numerical simulation, while possessing the technical advantages of elastic computing power expansion and low data transmission latency.

[0061] In some embodiments, such as Figure 3 As shown, the semiconductor device also includes a third semiconductor chip 124, which includes an interface module 106. The interface module 106 includes a first interconnect interface. The third semiconductor chip 124 connects to the chip stack structure 122 (see reference 124) via the first interconnect interface. Figure 2 The third semiconductor chip 124 is coupled to a main processor, which includes at least one of the following: a graphics processing unit (GPU), a central processing unit (CPU), or a tensor processor.

[0062] Here, the first interconnect interface is either a die-to-die (D2D) interconnect interface or a chip-to-chip (C2C) interconnect interface. It should be noted that the first interconnect interface in the third semiconductor chip is of the same type as the first interconnect structure in the chip stack structure.

[0063] In this embodiment, the first semiconductor chip not only achieves high-speed interconnection between the second semiconductor chip and the third semiconductor chip in the second chip stack structure, but also links the computing module through the system bus to directly call the stored data in the second semiconductor chip to perform computing operations, thus constructing an integrated "storage-computing" architecture to realize Computation Near Memory (CNM). This avoids frequent data transfer between the storage units of the chip stack structure and the computing modules outside the chip stack structure, reducing bandwidth consumption and energy loss.

[0064] In some embodiments, such as Figure 4 and Figure 5 As shown, the chip stack structure 122 located on both sides of the third semiconductor chip 124 along the second direction is axially symmetrically distributed with respect to the third semiconductor chip. Thus, the axially symmetrical distribution design balances the signal transmission path, optimizes heat dissipation efficiency, improves structural stability, simplifies wiring layout, and ensures the performance consistency of the chip stack structure.

[0065] Figure 4 and Figure 5 The chip stack structure 122 shown is a high-bandwidth memory.

[0066] here, Figure 4 and Figure 5 The multiple HBMs shown adopt a standard package design with unified size specifications, pin layout, interface protocol, and package form. Firstly, HBMs are mass-produced based on a unified standard, and their homogeneity significantly reduces R&D investment, further reducing production costs through economies of scale. Secondly, standardized interfaces and sizes eliminate the need for additional customized adaptation development, reducing compatibility debugging costs between third-party semiconductor chips and HBMs and improving integration efficiency. Thirdly, general-purpose production and testing equipment can be directly reused, avoiding the equipment purchase and debugging expenses required for customized processes and lowering the production threshold. Fourthly, defective HBMs can be disassembled and replaced individually, avoiding resource waste caused by scrapping the entire package. Fifthly, standardized design optimizes the package space layout, making each component more adaptable and enabling high-density integration within a limited space.

[0067] The technical solution provided in this disclosure, on the one hand, adopts a chip stacking architecture, vertically integrating a first semiconductor chip with an integrated controller and computing module, and multiple stacked second semiconductor chips in the same direction, reducing the planar area occupied, improving integration, and shortening the data transmission path. The controller of the first semiconductor chip can directly perform access operations on the stacked structure of the second semiconductor chip, realizing access to the stored data within the stacked structure of the second semiconductor chip without the need for additional relay links, significantly reducing access latency and improving instruction response speed. On the other hand, the controller of the first semiconductor chip, through linkage with the computing module, calls the stored data in the second semiconductor chip to perform computing operations, constructing an integrated "storage-computing" architecture, avoiding frequent data transfer between the storage units of the chip stacked structure and the computing modules outside the chip stacked structure, reducing bandwidth consumption and energy loss. In addition, by adding a controller with both storage management and computing scheduling functions to the first semiconductor chip, the hardware architecture is simplified, reducing overall cost and wiring complexity.

[0068] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0069] The above are merely preferred embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure. Any equivalent structural transformations made based on the inventive concept of this disclosure and the contents of the specification and drawings of this disclosure, or direct / simple applications in other related technical fields, are included within the scope of protection of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: A chip stacking structure includes: a first semiconductor chip and a second semiconductor chip stacking structure stacked along a first direction; the second semiconductor chip stacking structure includes a plurality of second semiconductor chips stacked sequentially along the first direction; the first semiconductor chip is connected to the second semiconductor chip stacking structure through a through-silicon via (TSV). The first semiconductor chip includes a controller, a computing module, and an interface module. The controller is coupled to the computing module and the interface module respectively. The controller is also coupled to the second semiconductor chip through a through-silicon via. The controller is configured to: perform a first access operation on the stored data in the second semiconductor chip stack structure and send the stored data to the interface module to allow an external device to access the stored data in the second semiconductor chip stack structure through the interface module; and perform a second access operation on the stored data in the second semiconductor chip stack structure and send the stored data to the computing module to allow the computing module to perform a computing operation on the stored data in the second semiconductor chip stack structure.

2. The semiconductor device according to claim 1, characterized in that, The controller is also configured to perform a refresh operation on at least the second semiconductor chip stack structure.

3. The semiconductor device according to claim 1, characterized in that, The first semiconductor chip further includes a test module connected to the through-silicon via; the controller is specifically configured to: Test operations are performed on the second semiconductor chip in the second semiconductor chip stack structure through the through-silicon via.

4. The semiconductor device according to claim 1, characterized in that, The interface module includes a first interconnect interface; wherein, the controller is specifically configured to: implement a first type of package of the chip stack structure using the first interconnect interface.

5. The semiconductor device according to claim 4, characterized in that, The first interconnection interface is a die-to-die D2D interconnection interface or a chip-to-chip C2C interconnection interface.

6. The semiconductor device according to claim 4, characterized in that, The semiconductor device includes a plurality of chip stack structures arranged in an array along a second direction and a third direction; adjacent chip stack structures are coupled through the first interconnect interface; Wherein, the second direction and the third direction intersect and are both perpendicular to the first direction.

7. The semiconductor device according to claim 6, characterized in that, The semiconductor device further includes a third semiconductor chip, the third semiconductor chip including the first interconnect interface and coupled to the chip stack structure through the first interconnect interface; The third semiconductor chip includes a main processor, which includes at least one of the following: a graphics processing unit, a central processing unit, or a tensor processor.

8. The semiconductor device according to claim 7, characterized in that, The chip stack structure located on both sides of the third semiconductor chip along the second direction is axially symmetrical with respect to the third semiconductor chip.

9. The semiconductor device according to claim 6, characterized in that, The semiconductor device further includes a packaging substrate and a packaging layer; The plurality of chip stack structures are located on the packaging substrate, and the packaging layer encapsulates the plurality of chip stack structures.

10. The semiconductor device according to claim 1, characterized in that, The first semiconductor chip includes a logic chip, and the second semiconductor chip includes a dynamic random access memory (DRAM) chip.

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