Silicon capacitor structure with low equivalent series resistance, preparation method thereof and electronic equipment

Abstract

The invention provides a silicon capacitor structure with low equivalent series resistance, a preparation method of the silicon capacitor structure and electronic equipment, and belongs to the technical field of semiconductors, the silicon capacitor structure comprises a silicon substrate, and a trench network is formed on the front surface of the silicon substrate; the laminated capacitor structure is arranged in the groove network and on the front surface of the silicon substrate, and the laminated capacitor structure comprises at least one layer of laminated structure composed of a bottom electrode, a dielectric layer and a top electrode; the bottom electrode covers the bottom surface and the side surface of the groove network and the front surface of the silicon substrate, the dielectric layer covers the bottom electrode, and the top electrode fills the groove network and covers the dielectric layer; the top electrode is electrically connected with the first electrode through the electrode interconnection hole, and the bottom electrode is electrically connected with the second electrode through the electrode interconnection hole; and at least one of the top electrode and the bottom electrode is correspondingly provided with a plurality of electrode interconnection holes. According to the invention, the equivalent series resistance of the silicon capacitor structure is reduced while the capacitance density is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a silicon capacitor structure with low equivalent series resistance, a preparation method thereof and an electronic device. BACKGROUND

[0002] In modern integrated circuits, capacitors are key components for realizing energy storage, decoupling, filtering and other functions, and their performance directly affects the power consumption, speed and stability of the entire system. With the continuous development of electronic devices towards miniaturization and high frequency, high requirements are put forward for the integration, capacitance density and frequency characteristics of capacitors. Traditional chip multilayer ceramic capacitors are difficult to meet the high performance requirements in advanced packaging due to packaging size and parasitic inductance. Under this background, silicon capacitors emerged as the times require. It is made on a silicon wafer using standard semiconductor processes, has high capacitance density, low equivalent series inductance, excellent high-frequency characteristics and is easy to be integrated with other chips in three dimensions, etc. It is an ideal choice for realizing the next generation of high-density and high-performance electronic systems.

[0003] At present, in order to improve the capacitance density, the number of layers of the capacitor structure in the silicon capacitor can be increased, but as the number of layers of the capacitor structure increases, the thickness of the single electrode layer will be thinned accordingly, resulting in an increase in the resistance of the electrode itself. At the same time, the interconnection structure introduced by the parallel connection of multiple layers of electrodes will also increase the additional parasitic resistance. These factors together cause the equivalent series resistance of the capacitor to increase. Therefore, while pursuing high capacitance density, how to effectively reduce the equivalent series resistance of the silicon capacitor has become a technical problem to be solved in the field. SUMMARY

[0004] The present application provides a silicon capacitor structure with low equivalent series resistance and a preparation method thereof and an electronic device, which reduces the equivalent series resistance of the silicon capacitor structure while improving the capacitance density.

[0005] In a first aspect, the present application provides a silicon capacitor structure with low equivalent series resistance, comprising: a silicon substrate, a front surface of the silicon substrate being formed with a trench network; a laminated capacitor structure arranged in the trench network and on the front surface of the silicon substrate, the laminated capacitor structure comprising at least one layer of laminated structure composed of a bottom electrode, a dielectric layer and a top electrode; wherein the bottom electrode covers the bottom surface and side surface of the trench network and the front surface of the silicon substrate, the dielectric layer covers the bottom electrode, and the top electrode fills the trench network and covers the dielectric layer; a first electrode and a second electrode arranged on the front surface of the laminated capacitor structure, the top electrode being electrically connected to the first electrode through an electrode interconnection hole, and the bottom electrode being electrically connected to the second electrode through an electrode interconnection hole; At least one of the top electrode and the bottom electrode is provided with a plurality of electrode interconnecting holes.

[0006] According to the present invention, a silicon capacitor structure with low equivalent series resistance is provided, wherein the vertical projection of the electrode interconnect hole is offset from the vertical projection of the trench network.

[0007] According to the present invention, a silicon capacitor structure with low equivalent series resistance is provided, wherein the stacked capacitor structure comprises multiple vertically stacked layers, and the top electrode of the stacked structure is reused as the bottom electrode of the next layer of the stacked structure; The even-numbered layer electrodes are electrically connected to the first electrode through the electrode interconnection holes, and the odd-numbered layer electrodes are electrically connected to the second electrode through the electrode interconnection holes.

[0008] According to the present invention, a silicon capacitor structure with low equivalent series resistance is provided, wherein at least two of the dielectric layers have different dielectric constants.

[0009] According to the present invention, a silicon capacitor structure with low equivalent series resistance is provided, wherein the material constituting the bottom electrode includes at least one conductive material selected from electro-polycrystalline silicon, titanium, titanium nitride, tantalum, tantalum nitride, gold, silver, platinum, copper or tungsten, and the material constituting the top electrode includes at least one material selected from titanium, titanium nitride, tantalum, tantalum nitride, copper or tungsten.

[0010] In a second aspect, the present invention also provides a method for fabricating a silicon capacitor structure with low equivalent series resistance, used to fabricate the silicon capacitor structure with low equivalent series resistance as described in the first aspect, the fabrication method comprising: A silicon substrate is provided, and a trench network is formed on the front side of the silicon substrate by an etching process; A multilayer capacitor structure is deposited within the trench network and on the front side of the silicon substrate; wherein the multilayer capacitor structure includes at least one multilayer structure consisting of a bottom electrode, a dielectric layer and a top electrode; Multiple electrode interconnect holes are formed by etching process, and a first electrode and a second electrode are formed in the electrode interconnect holes and on the front side of the stacked capacitor structure; wherein, the top electrode is electrically connected to the first electrode through the electrode interconnect holes, and the bottom electrode is electrically connected to the second electrode through the electrode interconnect holes, and at least one of the top electrode and the bottom electrode is provided with multiple electrode interconnect holes.

[0011] According to the present invention, a method for fabricating a silicon capacitor structure with low equivalent series resistance is provided. The stacked capacitor structure includes a double-layer stacked structure, wherein the double-layer stacked structure includes a first bottom electrode, a first dielectric layer, a first top electrode, a second dielectric layer, and a second top electrode, wherein the first top electrode is reused as the second bottom electrode. The deposition of a multilayer capacitor structure within the trench network and on the front side of the silicon substrate includes: The first bottom electrode is formed on the front side of the silicon substrate, such that the first bottom electrode covers the bottom and side surfaces of the trench network and the front side of the silicon substrate; Deposit the first dielectric layer on the first bottom electrode; The first top electrode is formed on the first dielectric layer; Deposit the second dielectric layer on the first top electrode; A second top electrode is formed on the second dielectric layer, such that the second top electrode fills the trench network; The process of forming multiple electrode interconnect holes through an etching process, and forming a first electrode and a second electrode within the electrode interconnect holes and on the front side of the stacked capacitor structure, includes: Etch the second top electrode and the second dielectric layer to form a first via exposing the first top electrode; Etch the second top electrode, the second dielectric layer, the first top electrode, and the first dielectric layer to form a second via exposing the first bottom electrode; An insulating layer is formed on the second top electrode, and the insulating layer is etched to form a first electrode interconnect hole exposing the first top electrode, a second electrode interconnect hole exposing the first bottom electrode, and a third electrode interconnect hole exposing the second top electrode; wherein the insulating layer covers the sidewalls of the first electrode interconnect hole and the second electrode interconnect hole. An electrode layer is formed on the insulating layer, and the electrode layer is etched to form a first electrode that fills the first electrode interconnect hole, and a second electrode that fills the second electrode interconnect hole and the third electrode interconnect hole.

[0012] According to a method for fabricating a silicon capacitor structure with low equivalent series resistance provided by the present invention, the process for fabricating the top electrode includes an annealing process to reduce the sheet resistance of the top electrode; and / or the process for fabricating the bottom electrode includes an annealing process to reduce the sheet resistance of the bottom electrode.

[0013] According to a method for fabricating a silicon capacitor structure with low equivalent series resistance provided by the present invention, the bottom electrode and the top electrode are fabricated by atomic layer deposition process.

[0014] Thirdly, the present invention also provides an electronic device comprising a silicon capacitor structure with low equivalent series resistance as described in the first aspect.

[0015] This invention, through an embodiment of the invention, forms a trench network by etching on the front side of a silicon substrate. With consistent dielectric materials and their withstand voltage, it transforms the originally flat two-dimensional surface into a three-dimensional structure. This means the effective area for forming the capacitor is no longer the planar projected area of ​​the silicon substrate, but rather the sum of the surface areas of the bottom and side surfaces of all the trenches. This achieves a larger effective surface area per unit area, significantly increasing capacitance density. Simultaneously, by providing multiple interconnecting vias for at least one of the top and bottom electrodes, the current flow path within the top and bottom electrodes is effectively shortened. This directly reduces the equivalent series resistance caused by the resistance of the top and bottom electrodes themselves, thereby lowering the overall equivalent series resistance of the silicon capacitor structure. Furthermore, the low equivalent series resistance silicon capacitor structure provided by this invention is compatible with existing semiconductor planar processes and is easy to integrate and manufacture. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 This is a three-dimensional structural diagram of a silicon capacitor structure with low equivalent series resistance provided by the present invention.

[0018] Figure 2 This is a cross-sectional schematic diagram of a silicon capacitor structure with low equivalent series resistance provided by the present invention.

[0019] Figure 3 This is a cross-sectional schematic diagram of another silicon capacitor structure with low equivalent series resistance provided by the present invention.

[0020] Figure 4 This is a schematic flowchart of a method for fabricating a silicon capacitor structure with low equivalent series resistance provided by the present invention.

[0021] Figures 5 to 12 This is a cross-sectional structural diagram of each step in the fabrication method of a silicon capacitor structure with low equivalent series resistance. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0023] Figure 1 This is a three-dimensional structural diagram of a silicon capacitor structure with low equivalent series resistance provided by the present invention. Figure 2 This is a cross-sectional schematic diagram of a silicon capacitor structure with low equivalent series resistance provided by the present invention. Combined with... Figure 1 and Figure 2 The low equivalent series resistance silicon capacitor structure includes a silicon substrate 1, a multilayer capacitor structure, a first electrode 6, and a second electrode 7. A trench network 2 is formed on the front side of the silicon substrate 1. The multilayer capacitor structure is disposed within the trench network 2 and on the front side of the silicon substrate 1. The multilayer capacitor structure includes at least one layer consisting of a bottom electrode 3, a dielectric layer 4, and a top electrode 5. The bottom electrode 3 covers the bottom and side surfaces of the trench network 2 and the front side of the silicon substrate 1. The dielectric layer 4 covers the bottom electrode 3. The top electrode 5 fills the trench network 2 and covers the dielectric layer 4. The first electrode 6 and the second electrode 7 are disposed on the front side of the multilayer capacitor structure. The top electrode 5 is electrically connected to the first electrode 6 through electrode interconnect holes 8, and the bottom electrode 3 is electrically connected to the second electrode 7 through electrode interconnect holes 8. At least one of the top electrode 5 and the bottom electrode 3 has a plurality of electrode interconnect holes 8 corresponding to it.

[0024] Specifically, silicon substrate 1 refers to a substrate made of single-crystal silicon material. In this embodiment of the invention, silicon substrate 1 can be, for example, but not limited to, a heavily doped silicon substrate. Trench network 2 refers to multiple groove structures formed on the front side of silicon substrate 1 by an etching process. Stacked capacitor structure refers to MIM (Metal-Insulator-Metal) capacitor structure. In this embodiment of the invention, it refers to a capacitor unit composed of bottom electrode 3, dielectric layer 4, and top electrode 5. Electrical connection refers to the ability of two components to conduct current. Electrode interconnection via 8 refers to a conductive via penetrating the intermediate layer to electrically lead the bottom electrode 3 or top electrode 5 to an external electrode. First electrode 6 and second electrode 7 refer to the two electrodes finally formed on the outermost side of the silicon capacitor, respectively connected to the two plates of the capacitor structure, namely the top electrode 5 and the bottom electrode 3.

[0025] With a fixed opening size in the trench network 2, the number of layers in the stacked capacitor structure can be increased to improve capacitance density. However, as the number of layers increases, the thickness of a single electrode layer in the stacked capacitor structure decreases accordingly, leading to an increase in the resistance of the electrode itself. Simultaneously, the interconnect structure introduced by the parallel connection of multiple electrodes also increases additional parasitic resistance. These factors collectively lead to an increase in the equivalent series resistance (ESR) of the capacitor. Therefore, while pursuing high capacitance density, effectively reducing the ESR of silicon capacitors has become a pressing technical challenge in this field. To address the aforementioned technical problems, this invention provides a silicon capacitor structure with low equivalent series resistance, achieving low ESR while improving the capacitance density of the silicon capacitor structure.

[0026] The core working principle of this invention lies in the fact that by providing multiple electrode interconnecting holes 8 for at least one of the top electrode 5 and the bottom electrode 3, the path length of current flowing from the inside of the electrode to the external connection point is significantly shortened, thereby reducing the equivalent series resistance of the capacitor. The provision of multiple electrode interconnecting holes 8 for at least one of the top electrode 5 and the bottom electrode 3 can be as follows: only the top electrode 5 may have multiple electrode interconnecting holes 8, only the bottom electrode 3 may have multiple electrode interconnecting holes 8, or both the top electrode 5 and the bottom electrode 3 may have multiple electrode interconnecting holes 8. For example... Figure 2 As shown in the figure, the top electrode 5 is provided with two electrode interconnecting holes 8, thereby realizing electrical connection with the first electrode 6, and the bottom electrode 3 is provided with two electrode interconnecting holes 8, thereby realizing electrical connection with the second electrode 7.

[0027] Specifically, when the capacitor is working, current needs to flow from the electrodes, including the top electrode 5 and the bottom electrode 3, to a fixed external connection point, including the first electrode 6 and the second electrode 7. Taking the bottom electrode 3 as an example, if the bottom electrode 3 only has one corresponding electrode interconnection hole 8, the current has to travel a long distance from the edge or far end of the bottom electrode 3 to the corresponding electrode interconnection hole 8, resulting in a large path resistance. This embodiment of the invention provides multiple distributed electrode interconnection holes 8 on the top electrode 5 and / or the bottom electrode 3, allowing the current to flow out from the electrode interconnection hole 8 closest to its origin. That is, the current can choose to be transmitted through the electrode interconnection hole 8 with the shortest transmission path, thereby greatly shortening the average length of each current path. According to the law of resistance, with the resistivity and cross-sectional area of ​​the material remaining constant, shortening the path length directly reduces the resistance. Therefore, at least one of the top electrode 5 and the bottom electrode 3 has multiple electrode interconnection holes 8, forming multiple parallel, shorter current paths. These current paths work together to reduce the overall equivalent series resistance of the silicon capacitor structure.

[0028] Therefore, in this embodiment of the invention, a trench network 2 is formed by etching on the front side of the silicon substrate 1. With consistent dielectric material and dielectric withstand voltage, the originally flat two-dimensional surface is transformed into a three-dimensional structure. This means the effective area for forming the capacitor is no longer the planar projected area of ​​the silicon substrate 1, but rather the sum of the surface areas of the bottom and side surfaces of all the trenches. This achieves a larger effective surface area per unit area, significantly improving capacitance density. Simultaneously, by providing multiple electrode interconnecting holes 8 corresponding to at least one of the top electrode 5 and bottom electrode 3, the current flow path within the top electrode 5 and bottom electrode 3 is effectively shortened. This directly reduces the equivalent series resistance caused by the resistance of the top electrode 5 and bottom electrode 3 themselves, thereby lowering the overall equivalent series resistance of the silicon capacitor structure. Furthermore, the low equivalent series resistance silicon capacitor structure provided by this embodiment of the invention is compatible with existing semiconductor planar processes and is easy to integrate and manufacture.

[0029] In some embodiments, the vertical projection of the electrode interconnect hole 8 is offset from the vertical projection of the trench network 2.

[0030] Specifically, vertical projection refers to the shape of the electrode interconnect hole 8 or trench network 2 projected onto the plane of the silicon substrate 1 in a direction perpendicular to the front side of the silicon substrate 1. Offset placement means that the vertical projection area of ​​the electrode interconnect hole 8 does not overlap with the vertical projection area of ​​the trench network 2. The etching process of the electrode interconnect hole 8 needs to stop precisely on the target electrode layer. If the electrode interconnect hole 8 is directly above the trench network 2, the etching process is difficult to control due to the complex topology of the trench, such as, but not limited to, steep steps and different material interfaces, easily leading to over-etching or under-etching. Over-etching of the electrode interconnect hole 8 may break through the underlying dielectric layer, causing a short circuit between the upper and lower electrodes; under-etching may lead to poor contact with the target electrode. By offsetting the placement of the electrode interconnect hole 8 from the trench network 2, that is, selecting a flat area on the front side of the silicon substrate 1, i.e., a non-trench area, to form the electrode interconnect hole 8, the complex structure of the trench can be avoided, greatly improving the reliability of the etching process and ensuring that the electrode interconnect hole 8 can accurately form an electrical connection with the target electrode.

[0031] Therefore, by setting the vertical projection of the electrode interconnect hole 8 to be staggered with the vertical projection of the trench network 2, this embodiment of the invention avoids the process difficulties caused by drilling holes in complex trench structures, reduces the risk of short circuits and poor contact, and improves process reliability and yield. Etching on flat areas is easier to control, resulting in lower and more stable contact resistance between the formed electrode interconnect hole 8 and the electrode, ensuring electrical connection quality and fundamentally avoiding dielectric layer breakdown and potential failure caused by over-etching, thus improving the long-term reliability of the capacitor.

[0032] Figure 3This is a cross-sectional schematic diagram of another silicon capacitor structure with low equivalent series resistance provided by the present invention. Figure 3 As shown, the multilayer capacitor structure includes a vertically stacked multilayer structure, and the top electrode of the multilayer structure is reused as the bottom electrode of the next multilayer structure; wherein, the even-numbered layer electrodes are electrically connected to the first electrode 6 through the electrode interconnection hole 8, and the odd-numbered layer electrodes are electrically connected to the second electrode 7 through the electrode interconnection hole 8.

[0033] Figure 3 An exemplary configuration of the stacked capacitor structure includes a vertically stacked double-layer structure. Vertical stacking refers to multiple stacked layers being sequentially stacked in a direction perpendicular to the silicon substrate 1. Multiplexing refers to the first top electrode 12 simultaneously serving as part of two different stacked structures; the first top electrode 12 is both the bottom electrode of the next stacked structure and the top electrode of the previous stacked structure. Even-numbered layer electrodes and odd-numbered layer electrodes refer to electrodes in stacked structures with an even number of layers (counting from the bottommost layer) and electrodes in stacked structures with an odd number of layers. After completing the stacked structure of the first bottom electrode 10-first dielectric layer 11-first top electrode 12 of the first layer, the first top electrode 12 is multiplexed as the second bottom electrode of the second stacked structure, and the second dielectric layer 13 and second top electrode 14 of the second stacked structure are deposited. The first stacked structure includes the first bottom electrode 10, the first dielectric layer 11, and the first top electrode 12; the second stacked structure includes the first top electrode 12, the second dielectric layer 13, and the second top electrode 14.

[0034] By setting the top and bottom electrodes of adjacent stacked structures to share the same conductive layer, and alternately connecting odd-numbered and even-numbered layer electrodes to the first electrode 6 and the second electrode 7 respectively, parallel connection of multilayer capacitor structures is achieved. Figure 3 Taking the double-layer structure shown as an example, the first bottom electrode 10 of the odd-numbered layers is connected to the second electrode 7, the first top electrode 12 of the even-numbered layers, which is multiplexed as the second bottom electrode, is connected to the first electrode 6, and the second top electrode 14 of the odd-numbered layers is connected to the second electrode 7. Figure 3 The electrode interconnect 8 for connecting the second top electrode 14 and the second electrode 7 is not shown. Thus, the two capacitor units—one consisting of the first bottom electrode 10, the first dielectric layer 11, and the first top electrode 12, and the other consisting of the first top electrode 12, the second dielectric layer 13, and the second top electrode 14—are connected in parallel. The total capacitance after parallel connection is the sum of the capacitances of each layer, thereby significantly increasing the total capacitance value without increasing the chip area.

[0035] Therefore, this embodiment of the invention utilizes a multi-layer stacked structure, overcoming the limitations of a two-dimensional plane. Without increasing the capacitor's footprint, it multiplies the total capacitance by increasing the number of layers in the vertical direction, further improving the capacitance density of the silicon capacitor. Electrode reuse reduces the required number of independent layers, simplifies the stacked structure, and makes the silicon capacitor structure compact. Through alternating odd and even connections, parallel connection of all capacitor units is efficiently achieved. It should be noted that the stacked capacitor structure can include three or more layers, with the electrical connection relationships satisfying that odd-numbered layer electrodes are short-circuited, even-numbered layer electrodes are short-circuited, odd-numbered layer electrodes are electrically connected to the second electrode 7, and even-numbered layer electrodes are electrically connected to the first electrode 6.

[0036] In some embodiments, at least two dielectric layers have different dielectric constants, for example, by setting... Figure 3 The dielectric constants of the first dielectric layer 11 and the second dielectric layer 13 are different.

[0037] Specifically, dielectric constant is a physical quantity that measures the polarization capability of a dielectric layer. The higher the dielectric constant of a dielectric layer, the larger the capacitance value that can be formed at the same thickness. In this embodiment of the invention, dielectric layers with different dielectric constants are used in the stacked structure of different layers, allowing for differentiated design of the performance of each capacitor unit. For example, but not limited to, the first dielectric layer 11 closest to the silicon substrate 1 can be made of a high dielectric constant dielectric material to provide a large capacitance value. The second dielectric layer 13 can be made of a dielectric material with a slightly lower dielectric constant but higher reliability and lower leakage current to improve the overall withstand voltage and reliability of the silicon capacitor.

[0038] Therefore, by setting at least two dielectric layers with different dielectric constants, this invention utilizes a hybrid dielectric design to allow for the synergistic optimization of multiple performance parameters such as capacitance, breakdown voltage, and leakage current within the same capacitor, overcoming the performance limitations of a single dielectric material. The most suitable material can be flexibly selected for different dielectric layers according to specific application requirements, achieving superior overall performance with limited cost increase.

[0039] In some embodiments, the material constituting the bottom electrode 3 includes at least one conductive material selected from electro-polycrystalline silicon, titanium, titanium nitride, tantalum, tantalum nitride, gold, silver, platinum, copper, or tungsten, and the material constituting the top electrode 5 includes at least one material selected from titanium, titanium nitride, tantalum, tantalum nitride, copper, or tungsten.

[0040] Specifically, conductive polycrystalline silicon refers to polycrystalline silicon material with good conductivity after doping. Since the bottom electrode 3 is in contact with the silicon substrate 1, the silicon substrate 1 can be directly doped to form heavily doped conductive regions on the surface of the trench network 2 and the front side of the silicon substrate 1, thus constituting the bottom electrode 3. Titanium, titanium nitride, tantalum, tantalum nitride, gold, silver, platinum, copper, or tungsten materials all have low resistivity. Selecting these low-resistivity materials as the bottom electrode 3 or top electrode 5 can reduce the sheet resistance of the bottom electrode 3 or top electrode 5 from the material itself, thereby directly contributing to reducing the equivalent series resistance of the capacitor. In addition, the listed materials are all conductive materials widely used in standard semiconductor processes, easy to integrate, and with mature processes.

[0041] In some embodiments, the aspect ratio of a single trench in the trench network 2 may be set to be greater than or equal to 10:1.

[0042] Specifically, taking a cylindrical trench as an example, the depth-to-width ratio is the ratio of the depth of a single trench to the diameter of the circular cross-section. Setting the depth-to-width ratio of a single trench in the trench network 2 to be greater than or equal to 10:1, preferably 50:1 or 60:1, can further increase the sidewall area of ​​the trench network 2 within a limited planar projected area, thereby achieving a larger effective surface area per unit area, maximizing the effective area of ​​the capacitor, and further improving the capacitance density of the capacitor.

[0043] In some embodiments, the vertical cross-sectional shape of a single trench in the trench network 2 is rectangular or spiral.

[0044] Specifically, the vertical cross-sectional shape refers to the cross-sectional profile shape obtained by cutting a single trench with a plane perpendicular to the surface of the silicon substrate 1, corresponding to the geometric characteristics of the single trench in the depth direction. When the single trench is a columnar trench, such as... Figure 2 and 3 As shown, the vertical cross-sectional shape of a single trench is rectangular. For example, but not limited to, anisotropic etching processes, such as deep reactive ion etching, can be used to fabricate columnar trenches. The increase in surface area depends on the depth and perimeter of the single trench. By increasing the aspect ratio, the surface area can be linearly increased. A spiral trench corresponds to a continuous, smooth helical curve in its vertical cross-section. The single trench extends along a meandering path within the silicon substrate 1, rather than sinking in a straight line. This can be achieved by optimizing the etching process, such as modulating etching parameters. The meandering path of the spiral trench results in a trench perimeter per unit projected area that is much larger than that of a straight rectangular trench. At the same depth and area, the spiral trench provides a larger surface area due to its longer effective perimeter, breaking through the linear growth limit of rectangular trenches and further increasing the capacitance density of the capacitor.

[0045] This invention also provides a method for fabricating a silicon capacitor structure with low equivalent series resistance. Figure 4 This is a schematic flowchart illustrating a method for fabricating a silicon capacitor structure with low equivalent series resistance provided by the present invention. The method for fabricating a silicon capacitor structure with low equivalent series resistance can be used to fabricate silicon capacitor structures with low equivalent series resistance as described in the above embodiments. Figure 4 As shown, the fabrication method of a silicon capacitor structure with low equivalent series resistance includes the following steps: Step 101: Provide a silicon substrate and form a trench network on the front side of the silicon substrate through an etching process.

[0046] Specifically, Figures 5 to 12 This is a cross-sectional structural diagram illustrating each step of the fabrication method for a silicon capacitor structure with low equivalent series resistance. For example... Figure 5 As shown, multiple trenches are formed on the silicon substrate 1 by semiconductor etching process. The multiple trenches constitute the trench network 2. The semiconductor etching process can be dry etching process or wet etching process. The formation of the trench network 2 provides a physical basis for achieving high capacitance density. The depth, shape and distribution of a single trench directly determine the final performance of the capacitor.

[0047] Step 102: A stacked capacitor structure is deposited within the trench network and on the front side of the silicon substrate; wherein the stacked capacitor structure includes at least one stacked structure consisting of a bottom electrode, a dielectric layer and a top electrode.

[0048] In some embodiments, with Figure 3 Taking the structure shown as an example, the stacked capacitor structure includes a double stacked layer structure, which includes a first bottom electrode 10, a first dielectric layer 11, a first top electrode 12, a second dielectric layer 13, and a second top electrode 14. The first top electrode 12 is reused as the second bottom electrode. like Figure 6 As shown, after the trench network 2 is formed, a first bottom electrode 10 is formed on the front side of the silicon substrate 1, so that the first bottom electrode 10 covers the bottom and side surfaces of the trench network 2 and the front side of the silicon substrate 1. That is, the first bottom electrode 10 is formed on the front side of the silicon substrate 1 where the trench network 2 is formed. The formed first bottom electrode 10 covers the bottom surface, side surface and top surface of the trench outer structure. The first bottom electrode 10 is a continuous and complete electrode layer, which provides the basis for the subsequent preparation of the dielectric layer and the top electrode.

[0049] In some embodiments, the silicon substrate 1 can be doped to form heavily doped conductive regions on the surface of the trench network 2 and the front side of the silicon substrate 1, thereby constituting the first bottom electrode 10. Doping refers to the process of introducing impurity ions into a semiconductor material to change its conductivity type. Heavily doped conductive regions refer to low-resistance regions formed by high-concentration doping. By selectively performing high-concentration ion doping on the silicon substrate 1, the silicon substrate 1 on the trench surface and around it is transformed from a semiconductor into a good conductor, thereby directly utilizing the heavily doped silicon itself as the first bottom electrode 10 of the capacitor. This method eliminates the need for additional conductive layer deposition, simplifying the process steps and reducing manufacturing costs. Simultaneously, the formed first bottom electrode 10 is naturally integrated with the silicon substrate 1, providing excellent ohmic contact and high reliability.

[0050] like Figure 7 As shown, after the first bottom electrode 10 is formed, a first dielectric layer 11 is deposited on the first bottom electrode 10.

[0051] like Figure 8 As shown, after the first dielectric layer 11 is formed, the first top electrode 12 is formed on the first dielectric layer 11.

[0052] like Figure 9 As shown, after the first top electrode 12 is formed, a second dielectric layer 13 is deposited on the first top electrode 12.

[0053] like Figure 10 As shown, after forming the second dielectric layer 13, a second top electrode 14 is formed on the second dielectric layer 13, so that the second top electrode 14 fills the trench network 2.

[0054] In some embodiments, a bottom electrode and a top electrode are fabricated by an atomic layer deposition process. The bottom electrode mentioned herein includes a first bottom electrode 10 and a first top electrode 12 serving as a second bottom electrode, and the top electrode includes a second top electrode 14.

[0055] Specifically, atomic layer deposition (ALD) is a thin film deposition technology based on self-limiting surface reactions. It allows for precise control of film thickness at the single-atom-layer level and exhibits excellent step coverage and conformal characteristics. The working principle of ALD involves alternately introducing different precursor gases into the reaction chamber. Each precursor reacts chemically with the substrate surface, and the reaction terminates. An inert gas is then introduced, and the film grows layer by layer. Due to this self-limiting growth characteristic, ALD can form highly uniform and flat electrode films within trenches, sidewalls, and openings with extremely high aspect ratios. This ensures the continuity and uniform thickness of the bottom and top electrodes throughout the complex three-dimensional structure, avoiding localized high-resistance points introduced by uneven, discontinuous, or excessively thin films. This process ensures the formation of low-resistance electrodes, which is beneficial for further reducing the overall equivalent series resistance of silicon capacitor structures.

[0056] In some embodiments, the bottom electrode and top electrode can be prepared by chemical vapor deposition (CVD) or physical vapor deposition (PVD), and the dielectric layer can be prepared by CVD, PVD, or atomic layer deposition (ALD).

[0057] In some embodiments, the process for fabricating the top electrode includes an annealing process to reduce the sheet resistance of the top electrode; and / or the process for fabricating the bottom electrode includes an annealing process to reduce the sheet resistance of the bottom electrode. That is, the process for fabricating only the top electrode includes an annealing process to reduce the sheet resistance of the top electrode, or the process for fabricating only the bottom electrode includes an annealing process to reduce the sheet resistance of the bottom electrode, or the process for fabricating the top electrode includes an annealing process to reduce the sheet resistance of the top electrode, and the process for fabricating the bottom electrode includes an annealing process to reduce the sheet resistance of the bottom electrode.

[0058] Specifically, annealing refers to a heat treatment process in which materials are heated to a certain temperature and held for a period of time, followed by slow cooling. Sheet resistance is a parameter that measures the resistivity of the top and bottom electrodes, and is related to their resistivity and thickness. After the top and bottom electrodes are deposited, they are annealed. During annealing, the heat energy can promote grain growth within the top and bottom electrode materials, reduce the number of grain boundaries, and repair lattice defects generated during deposition. This effectively reduces the resistivity of the top and bottom electrodes, thereby reducing their sheet resistance and further lowering the equivalent series resistance of the capacitor.

[0059] Step 103: Multiple electrode interconnect holes are formed by etching process, and a first electrode and a second electrode are formed in the electrode interconnect holes and on the front side of the stacked capacitor structure.

[0060] The top electrode is electrically connected to the first electrode 6 through the electrode interconnection hole 8, and the bottom electrode is electrically connected to the second electrode 7 through the electrode interconnection hole 8. At least one of the top electrode and the bottom electrode is provided with a plurality of electrode interconnection holes 8.

[0061] In some embodiments, with Figure 3 Taking the structure shown as an example, the stacked capacitor structure includes a double-layer stacked structure, which includes a first bottom electrode 10, a first dielectric layer 11, a first top electrode 12, a second dielectric layer 13, and a second top electrode 14. The first top electrode 12 is reused as the second bottom electrode.

[0062] like Figure 11 As shown, after the second top electrode 14 is formed, the second top electrode 14 and the second dielectric layer 13 are etched to form a first through hole 15 exposing the first top electrode 12, and the second top electrode 14, the second dielectric layer 13, the first top electrode 12 and the first dielectric layer 11 are etched to form a second through hole 16 exposing the first bottom electrode 10.

[0063] likeFigure 12 As shown, an insulating layer 9 is then formed on the second top electrode 14, and the insulating layer 9 is etched to form a first electrode interconnection hole 17 exposing the first top electrode 12, a second electrode interconnection hole 18 exposing the first bottom electrode 10, and a third electrode interconnection hole 19 exposing the second top electrode 14; wherein the insulating layer 9 covers the sidewalls of the first electrode interconnection hole 17 and the second electrode interconnection hole 18. The first electrode interconnection hole 17 is a first through hole 15 with its sidewalls covered by the insulating layer 9, and the second electrode interconnection hole 18 is a second through hole 16 with its sidewalls covered by the insulating layer 9.

[0064] Combination Figure 3 and Figure 12 Then, an electrode layer is formed on the insulating layer 9, and the electrode layer is etched to form a first electrode 6 filling the first electrode interconnect 17, and a second electrode 7 filling the second electrode interconnect 18 and the third electrode interconnect 19. Thus, the fabrication of a silicon capacitor structure with low equivalent series resistance is completed.

[0065] This invention also provides an electronic device including a silicon capacitor structure with low equivalent series resistance as described in the above embodiments, thus possessing the beneficial effects described in the above embodiments, which will not be repeated here. Exemplarily, the electronic device includes, but is not limited to, a pressure sensor.

[0066] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A silicon capacitor structure with low equivalent series resistance, characterized in that, include: A silicon substrate, wherein a trench network is formed on the front side of the silicon substrate; A stacked capacitor structure is disposed within the trench network and on the front side of the silicon substrate. The stacked capacitor structure includes at least one stacked structure composed of a bottom electrode, a dielectric layer, and a top electrode. The bottom electrode covers the bottom and side surfaces of the trench network and the front side of the silicon substrate, the dielectric layer covers the bottom electrode, and the top electrode fills the trench network and covers the dielectric layer. The first electrode and the second electrode are disposed on the front side of the stacked capacitor structure. The top electrode is electrically connected to the first electrode through an electrode interconnection hole, and the bottom electrode is electrically connected to the second electrode through an electrode interconnection hole. At least one of the top electrode and the bottom electrode is provided with a plurality of electrode interconnecting holes.

2. The silicon capacitor structure with low equivalent series resistance according to claim 1, characterized in that, The vertical projection of the electrode interconnect hole is offset from the vertical projection of the trench network.

3. The silicon capacitor structure with low equivalent series resistance according to claim 1, characterized in that, The stacked capacitor structure includes multiple stacked layers in a vertical direction, wherein the top electrode of the stacked structure is reused as the bottom electrode of the next stacked structure; The even-numbered layer electrodes are electrically connected to the first electrode through the electrode interconnection holes, and the odd-numbered layer electrodes are electrically connected to the second electrode through the electrode interconnection holes.

4. The silicon capacitor structure with low equivalent series resistance according to claim 3, characterized in that, At least two of the dielectric layers have different dielectric constants.

5. The silicon capacitor structure with low equivalent series resistance according to any one of claims 1-4, characterized in that, The material constituting the bottom electrode includes at least one conductive material selected from electro-polycrystalline silicon, titanium, titanium nitride, tantalum, tantalum nitride, gold, silver, platinum, copper, or tungsten, and the material constituting the top electrode includes at least one material selected from titanium, titanium nitride, tantalum, tantalum nitride, copper, or tungsten.

6. A method for fabricating a silicon capacitor structure with low equivalent series resistance, characterized in that, The method for fabricating a silicon capacitor structure with low equivalent series resistance as described in any one of claims 1-5 includes: A silicon substrate is provided, and a trench network is formed on the front side of the silicon substrate by an etching process; A multilayer capacitor structure is deposited within the trench network and on the front side of the silicon substrate; wherein the multilayer capacitor structure includes at least one multilayer structure consisting of a bottom electrode, a dielectric layer and a top electrode; Multiple electrode interconnect holes are formed by etching process, and a first electrode and a second electrode are formed in the electrode interconnect holes and on the front side of the stacked capacitor structure; wherein, the top electrode is electrically connected to the first electrode through the electrode interconnect holes, and the bottom electrode is electrically connected to the second electrode through the electrode interconnect holes, and at least one of the top electrode and the bottom electrode is provided with multiple electrode interconnect holes.

7. The method for fabricating a silicon capacitor structure with low equivalent series resistance according to claim 6, characterized in that, The stacked capacitor structure includes a double-layer stacked structure, which includes a first bottom electrode, a first dielectric layer, a first top electrode, a second dielectric layer, and a second top electrode, wherein the first top electrode is reused as the second bottom electrode; The deposition of a multilayer capacitor structure within the trench network and on the front side of the silicon substrate includes: The first bottom electrode is formed on the front side of the silicon substrate, such that the first bottom electrode covers the bottom and side surfaces of the trench network and the front side of the silicon substrate; Deposit the first dielectric layer on the first bottom electrode; The first top electrode is formed on the first dielectric layer; Deposit the second dielectric layer on the first top electrode; A second top electrode is formed on the second dielectric layer, such that the second top electrode fills the trench network; The process of forming multiple electrode interconnect holes through an etching process, and forming a first electrode and a second electrode within the electrode interconnect holes and on the front side of the stacked capacitor structure, includes: Etch the second top electrode and the second dielectric layer to form a first via exposing the first top electrode; Etch the second top electrode, the second dielectric layer, the first top electrode, and the first dielectric layer to form a second via exposing the first bottom electrode; An insulating layer is formed on the second top electrode, and the insulating layer is etched to form a first electrode interconnect hole exposing the first top electrode, a second electrode interconnect hole exposing the first bottom electrode, and a third electrode interconnect hole exposing the second top electrode; wherein the insulating layer covers the sidewalls of the first electrode interconnect hole and the second electrode interconnect hole. An electrode layer is formed on the insulating layer, and the electrode layer is etched to form a first electrode that fills the first electrode interconnect hole, and a second electrode that fills the second electrode interconnect hole and the third electrode interconnect hole.

8. The method for fabricating a silicon capacitor structure with low equivalent series resistance according to claim 6 or 7, characterized in that, The process for preparing the top electrode includes an annealing process to reduce the sheet resistance of the top electrode; and / or the process for preparing the bottom electrode includes an annealing process to reduce the sheet resistance of the bottom electrode.

9. The method for fabricating a silicon capacitor structure with low equivalent series resistance according to claim 6 or 7, characterized in that, The bottom electrode and the top electrode are prepared by atomic layer deposition.

10. An electronic device, characterized in that, Including the silicon capacitor structure with low equivalent series resistance as described in any one of claims 1-5.

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