Silicon carbide groove type MOSFET device with multilayer super junction structure
By introducing a multilayer superjunction structure into the MOSFET device, the problem of easy breakdown of trench MOSFET devices under high voltage is solved, higher reverse blocking voltage and conduction current are achieved, and the conduction characteristics and lifespan of the device are improved.
Patent Information
- Application Number
- CN202511687714.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-18
- Publication Date
- 2026-02-17
AI Technical Summary
Existing trench MOSFET devices are prone to breakdown under high voltage. Electric field concentration leads to premature breakdown of the device, and low doping concentration in the drift region results in reduced current density, affecting the conduction characteristics and lifespan of the device.
By adopting a multilayer superjunction structure, an N-type highly doped CSL region and a P-type doped short superjunction are introduced into the MOSFET device to form a multilayer superjunction structure, reducing the drift region thickness and blocking the high electric field at the bottom of the superjunction, optimizing the carrier distribution, and improving the reverse blocking voltage and conduction current of the device.
It improves the reverse blocking voltage of the device, reduces the specific on-resistance, improves the conduction characteristics and current density of the device, enhances the high-voltage application capability of the device, and extends its service life.
Smart Images
Figure CN121548076A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of power semiconductors, and more particularly to a silicon carbide trench MOSFET device with a multilayer superjunction structure. Background Technology
[0002] Power devices, as core components of power electronic systems, must possess characteristics such as high efficiency, high voltage withstand capability, and fast switching. Current mainstream power devices include MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), IGBTs (Insulated-Gate Bipolar Transistors), and SBDs (Schottky Diodes).
[0003] Among them, trench silicon carbide MOSFETs, compared to planar silicon carbide MOSFETs, exhibit lower specific on-resistance due to the absence of the JFET region, demonstrating significant advantages in fields such as new energy vehicles, photovoltaic inverters, and rail transportation. However, due to the presence of the trench structure, the electric field in trench MOSFETs tends to concentrate at the trench corners, leading to premature breakdown. For trench MOSFET devices that need to withstand high voltages, the doping concentration in the drift region is relatively low, resulting in a decrease in current density and consequently an increase in specific on-resistance.
[0004] However, thinning the drift region of a trench MOSFET can reduce the specific on-resistance of the device, thereby improving its conduction characteristics. But this reduces the distance the electric field extends in the drift region, thus lowering the reverse blocking voltage. Furthermore, the electric field spikes generated at the trench corners under high voltage accelerate carrier injection and trap formation, leading to preset voltage drift, reduced gate control over device switching, and decreased device lifespan.
[0005] In view of this, and taking into account the characteristics of semiconductor materials, this invention designs a silicon carbide trench MOSFET device with a multilayer superjunction structure. Summary of the Invention
[0006] The purpose of this invention is to solve the above-mentioned problems in the prior art and to provide a silicon carbide trench MOSFET device with a multilayer superjunction structure.
[0007] To achieve the above objectives, the present invention adopts the following technical solution:
[0008] A silicon carbide trench MOSFET device with a multilayer superjunction structure is formed by multiple cells connected in parallel, each cell comprising:
[0009] N-type doped substrate;
[0010] An N-type doped buffer layer is formed on the N-type doped substrate;
[0011] An N-type doped drift region is formed on the N-type doped buffer layer;
[0012] A superjunction multilayer structure is formed on the N-type doped drift region. The superjunction multilayer structure is composed of at least one set of stacking units stacked repeatedly n times, where n is an integer from 2 to 6. The stacking unit includes: an N-type highly doped CSL region and a P-type doped short superjunction distributed inside the N-type highly doped CSL region.
[0013] N-type doped regions are formed on the topmost superjunction multilayer structure;
[0014] The trench extends downwards from the surface into the N-type doped region;
[0015] A polysilicon gate is isolated within the trench by a gate dielectric layer;
[0016] The P-type doped well region is located above the N-type doped region and on both sides of the trench;
[0017] The N-type highly doped source region is located above the P-type doped well region and adjacent to the sidewall of the trench;
[0018] The P-type highly doped base region is located above the P-type doped well region and is in contact with the N-type highly doped source region;
[0019] The source electrode forms an ohmic contact with the N-type highly doped source region and the P-type highly doped base region;
[0020] The gate electrode is electrically connected to the polysilicon gate.
[0021] The drain electrode is formed on the back side of the N-type doped substrate.
[0022] The doping concentration of the N-type doped substrate is 5 × 10⁻⁶. 18 ~5×10 19 cm -3 The thickness is 300~500μm.
[0023] The doping concentration of the N-type doped buffer layer is 5 × 10⁻⁶. 17 ~5×10 19 cm -3 The thickness is 0.5~1μm.
[0024] The doping concentration of the N-type doped drift region is 5 × 10⁻⁶. 14 ~5×10 16 cm -3 The thickness is 8~20μm.
[0025] The doping concentration of the N-type highly doped CSL region is 5 × 10⁻⁶. 16 ~5×1018 cm -3 The thickness is 0.8~2μm.
[0026] The doping concentration of the p-type doped short superjunction is 5 × 10⁻⁶. 16 ~1×10 19 cm -3 The thickness is 0.5~1.5μm and the width is 0.5~2μm.
[0027] The doping concentration of the N-type highly doped source region is not less than 1×10⁻⁶. 19 cm -3 The depth is 0.2~0.7μm.
[0028] The doping concentration of the P-type doped well region is 5 × 10⁻⁶. 16 ~5×10 17 cm -3 The depth is 0.2~1μm.
[0029] The doping concentration of the highly doped P-type base region is not less than 5 × 10⁻⁶. 19 cm -3 The depth is 0.2~1μm.
[0030] The number of times the stacking unit is repeatedly stacked, n, is 4 or 5.
[0031] Compared with the prior art, the beneficial effects achieved by the technical solution of this invention are:
[0032] 1. This invention employs a superjunction structure. By introducing a highly doped N-type CSL region and a P-type doped short superjunction into the MOSFET device, the drift region thickness is reduced while the P-type doped short superjunction and the highly doped N-type CSL region mutually deplete each other, thus blocking the high electric field at the bottom of the superjunction. This reduces the electric field strength at the gate oxide corner, protecting the gate oxide, and also increases the reverse blocking voltage of the device, improving its reverse blocking capability.
[0033] 2. This invention employs a novel structure combining a P-type doped short superjunction and an N-type highly doped CSL region. By introducing an N-type highly doped CSL region inside the device, the carrier concentration distribution in the on-state is optimized, improving the on-state characteristics of the device, reducing the specific on-resistance, and achieving a higher on-current.
[0034] 3. The MOSFET device of the present invention can be applied to high voltage fields of 1200~1600V, and the device fabrication process is compatible with the existing trench MOSFET device process. Attached Figure Description
[0035] Figure 1 This is a schematic diagram of the cell structure of Embodiment 1 and the comparative example of the present invention;
[0036] Figure 2 This is a comparison of the conduction characteristics of the devices in Embodiments 1 and 2 of the present invention with those of the comparative device;
[0037] Figure 3 This is a comparison of the blocking characteristics of the devices in Embodiments 1 and 2 of the present invention with those of the comparative device;
[0038] Figure 4 This is a comparison of the current density distribution in the upper region of the drift region between Embodiment 1 (a) and Embodiment 2 (b) of the present invention and the comparative device (c). Detailed Implementation
[0039] To make the technical problems, technical solutions and beneficial effects of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments.
[0040] Example 1
[0041] The silicon carbide trench MOSFET device with a multilayer superjunction structure described in Embodiment 1 of this invention is formed by multiple cells connected in parallel. Figure 1 (a) is a schematic diagram of the cell structure of an embodiment of the present invention.
[0042] like Figure 1 As shown, the device includes an N-type doped substrate 12, an N-type doped buffer layer 1 located above the N-type doped substrate 12, an N-type doped drift region 2 located above the N-type doped buffer layer 1, and an N-type highly doped CSL region 3 located above the N-type doped drift region 2. P-type doped short superjunctions 4 are distributed in the 3. The stacking units composed of the N-type highly doped CSL region 3 and the P-type doped short superjunctions 4 are stacked upward to form a superjunction multilayer structure.
[0043] The N-type doped region 5 is located above the stacked unit of the top N-type highly doped CSL region 3 and the P-type doped short superjunction 4.
[0044] The trench extends downward from the surface into the N-type doped region 5; the polysilicon gate 6 is filled in the trench in an isolated manner through the gate dielectric layer;
[0045] The P-type doped well region 8 is located above the N-type doped region 5 and on both sides of the trench;
[0046] The N-type highly doped source region 7 is located above the P-type doped well region 8 and adjacent to the sidewall of the trench;
[0047] The P-type highly doped base region 9 is located above the P-type doped well region 8 and is in contact with the N-type highly doped source region 7;
[0048] The source electrode 10 is located above the N-type highly doped source region 7 and the P-type highly doped base region 9 and forms an ohmic contact;
[0049] The gate electrode 11 is located above the polysilicon gate 6 and is electrically connected to the polysilicon gate 6;
[0050] The drain electrode 13 is located below the N-type doped substrate 12.
[0051] In Embodiment 1 of the present invention, the doping concentration of the N-type doped substrate 12 is 1×10⁻⁶. 19 cm -3 The thickness is 350 μm; the doping concentration of N-type doped buffer layer 1 is 5 × 10⁻⁶. 18 cm -3 The thickness is 1 μm; the doping concentration of N-type doped drift region 2 is 1 × 10⁻⁶. 16 cm -3 It has a thickness of 10μm and can withstand voltages of over 1200V.
[0052] In Embodiment 1 of the present invention, the doping concentration of the P-type doped well region 8 is 5 × 10⁻⁶. 17 cm -3 The depth is 0.5 μm; the doping concentration of the N-type highly doped source region 7 is 1 × 10⁻⁶. 20 cm -3 The depth is 0.3 μm; the doping concentration of the p-type highly doped region 9 is 5 × 10⁻⁶. 19 cm -3 The depth is 0.6μm.
[0053] The stacking units, consisting of a highly doped N-type CSL region 3 and a P-type doped short superjunction 4, are stacked upwards four times, with the doping concentration of the highly doped N-type CSL region being 5 × 10⁻⁶. 16 cm -3 The thickness is 1 μm; the doping concentration of the P-type doped short superjunction inside the N-type highly doped CSL region is 2 × 10⁻⁶. 17 cm -3 It has a thickness of 1.2 μm and a width of 1 μm.
[0054] Example 2
[0055] Unlike Embodiment 1, the stacking units in Embodiment 2 are stacked 5 times.
[0056] Comparative Example
[0057] Figure 1 (b) is a schematic diagram of the MOSFET device cell structure in comparison. Its structure and parameters are completely consistent with those in Example 1 of this invention, except for the N-type highly doped CSL region and the P-type doped short superjunction.
[0058] Figure 2The diagram shows a comparison of the conduction characteristics of the silicon carbide trench MOSFET devices with multilayer superjunction structures of Embodiments 1 and 2 of this invention and a comparative MOSFET device at a gate voltage of 15V. Theoretically, to withstand high voltage, the drift region concentration of the comparative MOSFET device cannot be too high; a lower drift region concentration results in a lower carrier concentration in the forward conduction state, leading to a decrease in the on-state current. Furthermore, because the comparative MOSFET device only has an N-type doped region in the drift region, the electric field concentrates at the bottom of the trench, causing reliability issues and affecting device lifespan. In contrast, the silicon carbide trench MOSFET device of this invention with a multilayer superjunction structure introduces a highly doped N-type CSL region, increasing the carrier concentration in this region, reducing the on-resistance, and enhancing the device's conduction characteristics. The specific on-resistances of the devices of Embodiments 1 and 2 and the comparative device at a gate voltage of 15V and a drain voltage of 5V are 2.27 mΩ∙cm, respectively. 2 2.45mΩ∙cm 2 and 3.65mΩ∙cm 2 Therefore, it can be seen that the conduction characteristics of the device of the present invention have been effectively improved.
[0059] Figure 3 The diagram shows a comparison of the blocking characteristics of the silicon carbide trench MOSFET devices with multilayer superjunction structures of Embodiments 1 and 2 of the present invention with those of a comparative MOSFET device. As can be seen from the diagram, the blocking voltage of the device of Embodiment 1 (1442V) is even slightly higher than that of the comparative MOSFET device (1417V), while the blocking voltage of the device of Embodiment 2 (1623V) is much higher than that of the comparative MOSFET device. This achieves a reduction in on-resistance without a corresponding reduction in blocking voltage, making the device suitable for high-voltage applications up to 1200V.
[0060] Figure 4 The diagram shows the current density distribution in the upper region of the drift region for the silicon carbide trench MOSFET devices with multilayer superjunction structures of Embodiments 1(a) and 2(b) of the present invention, and the comparative MOSFET device structure (c). It can be seen that the devices of Embodiments 1 and 2 have a significant advantage in current density compared to the comparative device. This is because the N-type highly doped CSL region brings lower on-resistance and higher carrier concentration to the device.
[0061] In summary, the silicon carbide trench MOSFET device with a multilayer superjunction structure proposed in this invention has good conduction and reverse blocking characteristics, and the electric field distribution inside the device is more uniform, resulting in improved current density.
[0062] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A silicon carbide trench MOSFET device having a multi-layer super-junction structure formed by a plurality of cells connected in parallel, characterized in that, Each of the cells comprises: an N-type doped substrate (12); an N-type doped buffer layer (1) formed on the N-type doped substrate (12); an N-type doped drift region (2) formed on the N-type doped buffer layer (1); a super junction multilayer structure formed on the N-type doped drift region (2), the super junction multilayer structure being composed of at least one set of stacked units stacked repeatedly n times, wherein n is an integer from 2 to 6, the stacked unit comprising: an N-type highly doped CSL region (3), and a P-type doped short super junction (4) distributed inside the N-type highly doped CSL region (3); an N-type doped region (5) formed on the super junction multilayer structure of the topmost layer; a trench extending downward from the surface into the N-type doped region (5); a polysilicon gate (6) filled in the trench isolated by a gate dielectric layer; a P-type doped well region (8) located above the N-type doped region (5) and on both sides of the trench; an N-type highly doped source region (7) located above the P-type doped well region (8) and adjacent to the sidewall of the trench; a P-type highly doped base region (9) located above the P-type doped well region (8) and in contact with the N-type highly doped source region (7); a source electrode (10) forming ohmic contact with the N-type highly doped source region (7) and the P-type highly doped base region (9); a gate electrode (11) electrically connected with the polysilicon gate (6); a drain electrode (13) formed on the back of the N-type doped substrate (12).
2. A silicon carbide trench-MOSFET device having a multi-layer super-junction structure as set forth in claim 1, wherein: The doping concentration of the N-type doped substrate (12) is 5 × 10⁻⁶. 18 ~5×10 19 cm -3 The thickness is 300~500μm.
3. The SiC trench MOSFET device with multi-layer super-junction structure of claim 1, wherein: The doping concentration of the N-type doped buffer layer (1) is 5 × 10⁻⁶. 17 ~5×10 19 cm -3 The thickness is 0.5~1μm.
4. The SiC trench MOSFET device with multi-layer super-junction structure of claim 1, wherein: The doping concentration of the N-type doped drift region (2) is 5 × 10⁻⁶. 14 ~5×10 16 cm -3 The thickness is 8~20μm.
5. A silicon carbide trench MOSFET device with a multilayer superjunction structure as described in claim 1, characterized in that: The doping concentration of the N-type high-doped CSL region (3) is 5×10 16 ~5×10 18 cm -3 , and the thickness is 0.8~2μm.
6. A silicon carbide trench MOSFET device with a multilayer superjunction structure as described in claim 1, characterized in that: The doping concentration of the P-type doped short super junction (4) is 5×10 16 1×10 19 cm -3 , the thickness is 0.5-1.5 μm, and the width is 0.5-2 μm.
7. A silicon carbide trench MOSFET device with a multilayer superjunction structure as described in claim 1, characterized in that: The N-type high-doped source region (7) has a doping concentration of not less than 1×10 19 cm -3 -3, and a depth of 0.2-0.7 μm.
8. A silicon carbide trench MOSFET device with a multilayer superjunction structure as described in claim 1, characterized in that: The doping concentration of the P-type doped well region (8) is 5x1018 16 5x1018 17 cm -3 , and the depth is 0.2-1 μm.
9. A silicon carbide trench MOSFET device with a multilayer superjunction structure as described in claim 1, characterized in that: The doping concentration of the P-type high-doped base region (9) is not less than 5*10 19 cm -3 -3, and the depth is 0.2-1 μm.
10. A silicon carbide trench MOSFET device with a multilayer superjunction structure as described in claim 1, characterized in that: The number of times n of repeating stacking of the stacked unit is 4 or 5.