IGZO-based neuron transistor device with adaptive threshold and preparation method thereof
By using a single vertical architecture transistor design based on IGZO, the functional fragmentation and structural redundancy problems of adaptive neuron technology are solved. Adaptive threshold adjustment and neuron modeling are realized in a single device, simplifying the device structure, reducing energy consumption and integration costs, and improving the efficiency of neuromorphic computing.
Patent Information
- Application Number
- CN202511667896.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-14
- Publication Date
- 2026-02-17
AI Technical Summary
Existing adaptive neuron technology suffers from functional fragmentation and structural redundancy. Traditional devices struggle to implement adaptive thresholds and neuron models within a single device, leading to high energy consumption and integration complexity.
A single vertical architecture transistor design based on IGZO is adopted. By combining the gate, gate dielectric layer, mesh source, semiconductor layer and drain, an adaptive threshold neuron transistor is realized, which is simplified to a single transistor structure. The neuron triggering characteristics are modulated by the gate voltage and UV light pulse.
The LIF model of a neuron was implemented within a single transistor, simplifying the device structure, reducing power consumption and integration costs, enabling dynamic adjustment of the adaptive threshold, and improving the device's integration density and the efficiency of neuromorphic computing.
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Figure CN121548080A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of adaptive neuron devices, and more particularly to an IGZO-based neuron transistor device with adaptive threshold and a preparation method thereof. BACKGROUND
[0002] The traditional von Neumann architecture causes high energy consumption and high delay problems due to "separation of storage and calculation" leading to frequent data transfer. For example, the power consumption of an IBM supercomputer when processing complex tasks is as high as 1.4 megawatts, and the data transfer energy consumption accounts for more than 60%. This architecture is difficult to meet the energy efficiency needs of edge computing and other scenarios, restricting the popularization and development of AI technology. Neuromorphic computing breaks through the von Neumann bottleneck by simulating the "event-driven" and "compute-in-memory" mechanisms of the human brain, and is expected to achieve ultra-low power consumption and high learning efficiency. Therefore, the development of neuromorphic hardware devices has attracted widespread attention and research in recent years, and is an important way to break through the von Neumann bottleneck in the next generation of artificial intelligence technology. Among them, artificial neuron devices, as key components in neuromorphic computing, are crucial to the development of high-performance neuromorphic devices. They exhibit signal generation and coding functions such as rectified integration, response refractory period, and random triggering, as key electronic devices for signal coding and activation function modules in hardware neuromorphic computing, mainly used for information reasoning and decision-making in hardware systems. Due to its excellent processing capability for time series signals, it is widely used in pulse neural networks that best match the working mechanism of the biological brain.
[0003] Adaptive learning and information processing are the primary basis for the biological brain to adapt to complex and variable environmental conditions. In the biological perception mode, it mainly relies on detection and adaptation capabilities, the former is used to amplify the stimulus signal, and the latter is used to filter the influence of background noise signals. This perception mode enables the biological brain to quickly adapt to various environments, providing the optimal conditions of minimum energy consumption and fastest response speed for brain behavior control. Therefore, achieving adaptive information processing capability at the level of neuromorphic devices is of great significance for high-level artificial intelligence applications such as human-computer interaction, intelligent robots, and intelligent assisted driving, and has attracted a lot of attention. At present, in the field of neuron devices, the main focus is on simplifying the complexity of traditional neuron circuits through new materials and structures, while realizing the key spatiotemporal dynamics of biological neurons, such as threshold adaptation, leaky-integrate-fire model.
[0004] The main technical strategies in recent years can be summarized into three categories:
[0005] 1. Multi-device integration scheme. Mainly use dynamic memristor or phototransistor with charge trapping ability combined with peripheral oscillation circuit, use the randomness of conductive domain or charge trapping to simulate the trigger of neuron, and adjust the oscillation frequency through the peripheral circuit to realize the adaptive trigger of neuron, but it needs multiple devices to cooperate and integrated process. Inconsistency of electrical parameters can easily lead to device integration difficulties, and increase the complexity and area cost of hardware system, weaken the advantages of neuromorphic architecture.
[0006] 2. Scheme for functional expansion through three-terminal synaptic device. Research attempts to simulate synaptic plasticity (such as STP / LTP) through ion migration effects of double-layer transistors (such as indium zinc tin oxide IZTO nanowire devices), or to generate pulses through ion-electron coupling of organic electrochemical transistors (OECTs). Although these devices perform outstandingly in low power consumption (such as 0.0845 fJ / event) and flexible integration, their functions are still limited to synaptic weight adjustment, and cannot integrate a complete LIF neuron model in a single device, and lack an independent threshold regulation end.
[0007] 3. Neuromorphic reconstruction of silicon-based transistors. The latest technological achievements report that standard CMOS transistors can exhibit neural characteristics through non-traditional biasing (such as the floating body MOSFET scheme of the National University of Singapore), but such designs require specific circuit configurations (such as series resistors or additional transistors), and threshold adjustment requires external bias control, which cannot achieve the intrinsic adaptive mechanism of the device.
[0008] In summary, the current adaptive neuron technology still faces two major problems. First, functional fragmentation. Memristor, double-layer transistor and other schemes can only simulate the local behavior of synapses or neurons, such as silicon nanowire neural transistors which implement LIF but have fixed thresholds. Second, structural redundancy. Adaptive threshold requires multiple devices or external circuits to achieve, resulting in limited energy efficiency and integration density. SUMMARY
[0009] The purpose of the present application is to provide an IGZO-based neuron transistor device with adaptive threshold and a preparation method thereof. The present application realizes the threshold adaptive function of neurons on a single vertical architecture transistor based on IGZO semiconductor, and realizes the function of neuron transistor with adaptive threshold at a lower process cost and device size cost.
[0010] The above technical purpose of the present application is achieved by the following technical scheme: an IGZO-based neuron transistor device with adaptive threshold, which is composed of a gate electrode, a gate dielectric layer (insulating layer), a mesh source electrode, a semiconductor layer, and a drain electrode from bottom to top.
[0011] The application is further provided with: the gate is composed of n-type heavily doped Si, the gate dielectric layer (insulating layer) is composed of SiO2, the net source electrode is AgNWs, the semiconductor layer is an IGZO thin film, and the drain electrode is Ag.
[0012] The application further provides a preparation method of the neuron transistor device, which comprises the following four steps:
[0013] S1. Preparation of the gate and the gate dielectric layer;
[0014] S2. Preparation of the net source electrode AgNWs;
[0015] S3. Preparation of the IGZO semiconductor layer;
[0016] S4. Preparation of the drain electrode.
[0017] The application is further provided with: the preparation process of the gate and the gate dielectric layer in S1 is as follows:
[0018] n-type heavy ion doping is performed on 1.5 x 1.5 cm 2 of single crystal Si by means of ion implantation, so that the single crystal Si has high conductivity as an electrode to obtain the gate; then, high-temperature oxidation is adopted to perform an oxidation reaction on the single-side polished Si to generate SiO2 as the gate dielectric layer to insulate the source electrode and the drain electrode.
[0019] The application is further provided with: the preparation process of the passivation layer PVP polymer thin film in S2 is as follows:
[0020] The preparation process of the preparation of the net source electrode AgNWs in S2 is as follows:
[0021] The gate dielectric layer surface is cleaned with ultrapure water, acetone and isopropanol solution respectively by using an ultrasonic cleaning machine, and after cleaning, the gate dielectric layer, i.e., the SiO2 surface, is treated by oxygen plasma; a 5 mg / ml AgNWs solution with isopropanol as the solvent is spin-coated on the SiO2 surface by using a spin coater, as the source electrode of the vertical transistor, and then annealing is performed for 10 min under a nitrogen environment at a temperature of 150 DEG C to obtain the net source electrode.
[0022] The application is further provided with: the time for treating the gate dielectric layer by plasma is 10 min, and the power is 100 W.
[0023] The application is further provided with: the preparation process of the preparation of the IGZO semiconductor layer in S3 is as follows:
[0024] An IGZO thin film is grown above the AgNWs as the channel of the device by adopting a magnetron sputtering process, and the thickness of the IGZO thin film is 300 nm, i.e., the channel distance.
[0025] The application is further provided with the following preparation process of the drain Ag in the S4:
[0026] The electron beam evaporation process is adopted, Ag electrodes, i.e. drains, are evaporated on the surfaces of the IGZO semiconductor thin films through different mask plates, the electron beam current is 230 A, the evaporation time is 60 min, and the thickness of the drains is 40 nm.
[0027] The application is further provided with the following control in the magnetron sputtering process: Ar:O2=100:5, the deposition speed is 1-3 nm / min, and the sputtering power is 120 W.
[0028] The application is further provided with the following thickness of the IGZO thin film: 300 nm.
[0029] In summary, the application has the following beneficial effects:
[0030] The LIF model of the neuron is realized in the single transistor, and the purpose of structural simplification is realized at the hardware level. The LIF function of the artificial neuron can be realized on the single transistor, the multi-component structure of the 1T1R in the traditional scheme is replaced, the device area is reduced, and the process compatibility of the low-temperature IGZO is strong. The current device for intelligent sensing processing needs to rely on additional nonlinear processing of adaptive neuron activation, which is realized through additional circuit design. Although the adaptive neuron activation can enrich the neuromorphic function of the transistor by introducing the additional control circuit at present, the adaptive threshold neuron activation is still missing in a single device. Based on a single transistor, the triggering time and triggering probability of the neuron can be controlled and adjusted through the gate voltage, without the need for peripheral control circuits such as RC circuits and 1T1R circuits, so that the size of the traditional neuron module is greatly reduced.
[0031] The neuron transistor device provided by the application can program the neuron triggering threshold (V TH ) and the triggering time (Delta t) in real time through the gate voltage (V G ), realize the dynamic threshold adaptive function of the hardware level, and solve the problem of fixed triggering threshold in the traditional device technology. The neuron transistor device can modulate the neuron triggering characteristics of the device in a dual-mode manner through V G or UV light pulse as a modulation means, and can realize the dynamic threshold adjustment capability. BRIEF DESCRIPTION OF DRAWINGS
[0032] Figure 1 is a device structure schematic diagram of the adaptive vertical neuron transistor based on IGZO in the embodiment of the application;
[0033] Figure 2Figure 1 is a schematic diagram of a preparation process of a neuron transistor device in an embodiment of the present application. DETAILED DESCRIPTION
[0034] The present application will be further described below in conjunction with the accompanying drawings. Figures 1-2 The present application will be further described below in conjunction with the accompanying drawings.
[0035] Embodiment: Preparation method of IGZO-based neuron transistor device with adaptive threshold, as shown in Figure 1, the preparation method comprises the following four steps: Figure 2
[0036] S1. Preparation of gate and gate dielectric layer: n-type heavy ion doping is performed in a 1.5 x 1.5 cm single crystal Si by ion implantation, so that it has high conductivity as an electrode to obtain a gate; then high-temperature oxidation is used to perform an oxidation reaction on the single-side polished Si to generate SiO2 as a gate dielectric layer to insulate the source / drain, so the gate dielectric layer is also called an insulating layer. 2
[0037] S2. Preparation of mesh source: an ultrasonic cleaning machine is used to clean the surface of the gate dielectric layer with ultrapure water, acetone, and isopropyl alcohol solution respectively, after cleaning, the surface of the gate dielectric layer, i.e. SiO2, is treated by oxygen plasma, the time for treating the gate dielectric layer by plasma is 10 min, and the power is 100 W; a 5 mg / ml AgNWs solution with isopropyl alcohol as the solvent is spin-coated on the surface of SiO2 by using a glue uniformizer as the gate dielectric, and then annealing is performed for 10 min under a nitrogen environment at a temperature of 150°C to obtain a mesh source.
[0038] S3. Preparation of semiconductor layer IGZO thin film: a layer of IGZO thin film is grown above the AgNWs as the channel of the device by using a magnetron sputtering process, and the thickness of the obtained IGZO thin film is 300 nm. In the magnetron sputtering process, Ar:O2 is controlled to be 100:5, the deposition speed is 1–3 nm / min, and the sputtering power is 120 W.
[0039] S4. Preparation of drain: an Ag electrode, i.e. drain, is evaporated on the surface of the IGZO thin film by using an electron beam evaporation process through a mask plate, the electron beam current is 230 A, the evaporation time is 60 min, and the thickness of the drain is 40 nm. The source and drain can also be replaced by ITO / Au, graphene / Ag, etc. Source / drain: Au / Ag → ITO / Au, graphene / Ag (maintain the difference in work function > 0.5 eV).
[0040] The channel can also be replaced by other semiconductor materials, such as In2O3, ZnO, and other oxide semiconductors, which are compatible with the same process.
[0041] The neuron transistor device structure can also adopt a double-gate structure, the threshold value is regulated through a top gate electrode, and the triggering probability is regulated through a back gate, thereby expanding the parameter programming dimension of the LIF model.
[0042] As shown in Figure 1 The neuron transistor device prepared by the above method is composed of a gate electrode, a gate dielectric layer, a passivation layer and a semiconductor layer from bottom to top, and further comprises a source electrode and a drain electrode.
[0043] The specific embodiments are only an explanation of the present application, and are not a limitation of the present application, and those skilled in the art can make modifications to the embodiments without creative contribution according to the needs after reading the specification, and as long as the modifications are within the scope of the claims of the present application, they are protected by the patent law.
Claims
1. A neuronal transistor device with adaptive threshold based on IGZO, characterized by: The neuron transistor device consists of, from bottom to top, a gate, a gate dielectric layer, a mesh source, a semiconductor, and a drain, and is generally a vertical transistor structure.
2. The neuronal transistor device with adaptive threshold based on IGZO according to claim 1, characterized in that: The gate is composed of n-type heavily doped Si, the gate dielectric layer is composed of SiO2, the mesh source is AgNWs, the semiconductor layer is an IGZO thin film, and the drain is Ag.
3. The method for fabricating an adaptive threshold neuronal transistor device based on IGZO according to claim 2, characterized in that: The preparation method includes the following four steps: S1. Fabrication of the gate and gate dielectric layers; S2. Preparation of mesh source AgNWs; S3. Fabrication of the IGZO semiconductor layer; S4. Drain preparation.
4. The method for fabricating an adaptive threshold neuronal transistor device based on IGZO according to claim 3, characterized in that: The fabrication process of the gate and gate dielectric layer in S1 is as follows: Ion implantation was performed on a 1.5 x 1.5 cm specimen. 2 n-type heavy ion doping is performed on single-crystal Si to make it highly conductive as an electrode to obtain the gate; then, high-temperature oxidation is used to generate SiO2 on single-sided polished Si to serve as the gate dielectric layer to insulate the source / drain.
5. The method for fabricating an adaptive threshold neuronal transistor device based on IGZO according to claim 4, characterized in that: The fabrication process of the mesh source AgNWs in S2 is as follows: The gate dielectric layer surface was cleaned with ultrapure water, acetone, and isopropanol solutions using an ultrasonic cleaner. After cleaning, the gate dielectric layer, i.e., the SiO2 surface, was treated with oxygen plasma. A spin coater was used to spin-coat a 5 mg / ml AgNWs solution with isopropanol as the source of the vertical transistor. The surface was then annealed in a nitrogen atmosphere at 150°C for 10 min to obtain a mesh source.
6. The method for fabricating an adaptive threshold neuronal transistor device based on IGZO according to claim 5, characterized in that: The plasma treatment time for the gate dielectric layer is 10 min, and the power is 100 W.
7. The method for fabricating an adaptive threshold neuronal transistor device based on IGZO according to claim 6, characterized in that: The fabrication process for the IGZO semiconductor layer in S3 is as follows: An IGZO thin film with a thickness of 300 nm was grown on top of AgNWs using a magnetron sputtering process to serve as the channel of the device.
8. The method for fabricating an adaptive threshold neuronal transistor device based on IGZO according to claim 7, characterized in that: The preparation process for the drain Ag in S4 is as follows: Electron beam evaporation was used to evaporate Ag electrodes (drain electrodes) on the surface of IGZO semiconductor thin films using different masks. The electron beam current was 230 A, the evaporation time was 60 min, and the thickness of the drain electrode was 40 nm.
9. The IGZO-based neuronal transistor device with adaptive threshold and its fabrication method according to claim 8, characterized in that: In the magnetron sputtering process, Ar:O2 = 100:5, the deposition rate is 1–3 nm / min, and the sputtering power is 120 W.
10. The method for fabricating an adaptive threshold neuronal transistor device based on IGZO according to claim 8, characterized in that: The thickness of the IGZO thin film is 300 nm.