Preparation method of gate oxide layer of trench gate type silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor)

Abstract

The invention relates to a preparation method of a gate oxide layer of a trench gate type silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). The preparation method comprises the following steps of: etching a silicon carbide substrate to form a gate trench and then loading the gate trench into a high-temperature furnace tube; carrying out first-time oxide layer growth on the silicon carbide substrate on which the gate trench is formed at a first temperature in an atmosphere of oxidizing gas; carrying out second oxidation layer deposition on the silicon carbide substrate, and carrying out first high-temperature heat treatment at a second temperature; coating photoresist on the oxide layer at the bottom of the gate trench; removing the photoresist at the bottom of the gate trench after etching the oxide layer on the side wall of the gate trench; performing third oxidation layer deposition on the silicon carbide substrate, and performing second high-temperature heat treatment at a third temperature and in a nitrogen-containing gas atmosphere; and performing third high-temperature heat treatment on the silicon carbide substrate at a fourth temperature and in an inert gas atmosphere to complete the preparation of the gate oxide layer. According to the method, densification and annealing processes are introduced, so that the interface quality is prompted, and the performance and reliability of the device are further improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing, and more particularly to a method for preparing a gate oxide layer of a trench-gate silicon carbide MOSFET. Background Technology

[0002] Silicon carbide (SiC) power devices, with their superior high-temperature, high-frequency, high-voltage, and radiation-resistant properties, have become core components in fields such as new energy vehicles, photovoltaic energy storage, and rail transportation. Structurally, the mainstream SiC MOSFETs are currently divided into two main types: planar gate (SiC DMOSFET) and trench gate (SiC UMOSFET). Among them, trench-type SiC UMOSFETs, by eliminating the JFET region, possess lower specific on-resistance, higher threshold voltage, and stronger current conduction capability. This not only improves the overall performance of the device but also reduces system costs, thus attracting the attention of many new energy vehicle companies, including Jike, Xiaomi, and Volkswagen.

[0003] However, SiC UMOSFETs still face a key challenge in practical applications—gate oxide reliability. Due to the significant electric field concentration at the bottom of the trench during device operation, the electric field strength experienced by the gate oxide layer at this location is much higher than in planar structures, severely impacting the long-term reliability and lifespan of the device. To mitigate this issue, the industry commonly employs a technique of locally thickening the oxide layer at the bottom of the trench, typically making it 4–5 times the thickness of a conventional gate oxide layer (approximately 50 nm), i.e., approximately 200–250 nm, to enhance gate breakdown voltage and suppress electric field peaks.

[0004] However, this hardening process encountered severe material and process matching challenges in actual manufacturing. The fundamental reason lies in the drastically different thermal oxidation rates of SiC materials in different crystal orientations. The gate oxide layer of existing planar SiC MOSFETs is typically grown directly using a thermal oxidation process, which is relatively simple and produces good uniformity. However, in trench structures, the sidewalls and bottom of the trench, formed by etching, have completely different crystal orientations: the sidewalls are typically (11-20) or (1-100) crystal planes, while the bottom of the trench is a (000-1) crystal plane, the so-called "carbon plane." During thermal oxidation, the oxidation rate of the carbon plane is significantly slower than that of the sidewall crystal planes, resulting in an oxide layer thickness at the bottom of the trench being only about half that of the sidewalls under the same oxidation time.

[0005] This difference presents a dilemma: if thermal oxidation is performed based solely on the target bottom thickness (e.g., 200nm), the sidewall oxide layer will overgrow simultaneously due to the slow bottom oxidation rate, potentially exceeding 300nm in actual thickness. Excessively thick sidewall gate oxide significantly increases channel resistance, thereby substantially increasing the overall on-resistance of the device and negating the inherent advantages of SiC UMOSFETs in conduction performance. Conversely, if the process is controlled based on a suitable sidewall thickness, the insufficient thickness of the bottom gate oxide will prevent effective electric field dispersion, leaving the device still exposed to a high risk of gate oxide breakdown.

[0006] Therefore, the core technological challenge in the current manufacturing of SiC UMOSFETs can be summarized as the uncontrollable and uneven oxide layer thickness inside the trench caused by the anisotropic thermal oxidation characteristics of SiC material. The root cause of this problem lies in the mismatch between the material's inherent physical properties and existing thermal oxidation processes, making it difficult for device designers to achieve an ideal balance between "gate oxide reliability" and "conduction performance," thus hindering the further development and wider application of trench-type SiC MOSFETs.

[0007] Therefore, a method for fabricating the gate oxide layer of a trench-gate silicon carbide MOSFET is needed to solve the above problems. Summary of the Invention

[0008] This invention aims to provide a method for fabricating the gate oxide layer of a trench-gate silicon carbide MOSFET, which maintains the thickness of the bottom oxide layer between 200-250 nm and the sidewall gate oxide layer thickness at around 50 nm. This ensures both the shielding effect of the bottom oxide layer on the electric field during device operation and the normal current carrying capacity of the device. Furthermore, the introduction of densification and annealing processes during oxide layer formation improves interface quality, further enhancing the device's performance and reliability. The technical problem to be solved by this invention is achieved through the following technical solution.

[0009] According to a first aspect of this application, a method for preparing a gate oxide layer of a trench-gate silicon carbide MOSFET is provided, comprising the following steps: Step 1: After etching the gate trenches on the silicon carbide substrate, the silicon carbide substrate is loaded into the high-temperature furnace tube; Step 2: In an atmosphere of first temperature and oxidizing gas, the silicon carbide substrate forming the gate trench is grown for the first oxide layer. Step 3: Deposit a second oxide layer on the silicon carbide substrate after the first oxide layer growth is completed, and perform a first high-temperature heat treatment at a second temperature; Step 4: After unloading the silicon carbide substrate from the high-temperature furnace tube, apply photoresist to the oxide layer at the bottom of the gate trench for protection. Step 5: After etching away the oxide layer on the sidewalls of the gate trench using an etching process, remove the photoresist at the bottom of the gate trench; Step 6: Deposit a third oxide layer on the silicon carbide substrate, and perform a second high-temperature heat treatment at a third temperature and in a nitrogen-containing gas atmosphere; Step 7: Perform a third high-temperature heat treatment on the silicon carbide substrate at the fourth temperature and in an inert gas atmosphere to complete the preparation of the gate oxide layer.

[0010] Preferably, in step 1, the gate trench is etched using a dry trench etching process, wherein the dry trench etching process is inductively coupled plasma etching or reactive ion etching.

[0011] Preferably, in step 2, the first temperature is 1100℃-1300℃, and the oxidizing gas is one of oxygen, nitric oxide, or nitrogen dioxide.

[0012] Preferably, the thickness of the oxide layer formed after the first oxide layer growth is 5-15 nm.

[0013] Preferably, in step 3, a second oxide layer is deposited using a CVD process, and the thickness of the second oxide layer is 150-250 nm.

[0014] Preferably, the second temperature is 800℃-1100℃, and the first high-temperature heat treatment is carried out in an atmosphere of a single gas of nitrogen, hydrogen and argon or a mixture of two or more of them.

[0015] Preferably, in step 6, a third oxide layer is deposited using thermal oxidation, atomic layer deposition, or LPCVD processes, and the thickness of the deposited oxide layer is 45-60 nm.

[0016] Preferably, the third temperature is 1100℃-1300℃, and the nitrogen-containing gas is a single nitrogen-containing gas or a mixture of two or more nitrogen-containing gases, including nitric oxide, nitrogen, nitrogen dioxide, nitrous oxide, and ammonia.

[0017] Preferably, the fourth temperature is 1200℃-1400℃, and the inert gas is a single gas or a mixture of two or more gases selected from argon, nitrogen, and hydrogen.

[0018] Preferably, the duration of the first high-temperature treatment, the second high-temperature treatment, and the third high-temperature treatment is 30-180 minutes.

[0019] According to an embodiment of this application, the method for fabricating the gate oxide layer of this trench-gate silicon carbide MOSFET has the following advantages: First, silicon oxide is grown on the etched SiC gate trench using an oxidation method to ensure the interface quality between SiC and SiO2. Then, SiO2 of about 200nm is grown using CVD to ensure the SiO2 thickness at the bottom of the trench to improve the gate oxide reliability of the device. Next, the oxide layer is subjected to high-temperature annealing heat treatment to make the oxide layer more dense. Then, a photolithography process is performed to retain the oxide layer at the bottom of the trench while etching away the sidewall oxide layer. After resist removal, a gate oxide layer of approximately 50 nm is grown on the sidewalls. After two high-temperature annealing processes, the final oxide layer of the trench gate is fully formed. The sidewall oxide layer, with a thickness of approximately 50 nm, provides good interface quality; the bottom oxide layer, with a thickness of approximately 200 nm, effectively protects the gate oxide layer and improves the reliability of the gate dielectric. Attached Figure Description

[0020] Figure 1 This is a flowchart of the steps in a method for preparing a gate oxide layer for a trench-gate silicon carbide MOSFET according to the present invention; Figure 2 This is a schematic diagram of the structure after the first oxide layer deposition on a silicon carbide substrate according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure after the second oxide layer deposition on the silicon carbide substrate according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of a silicon carbide substrate after photolithography in an embodiment of the present invention; Figure 5 This is a schematic diagram of the structure after etching the oxide layer on the silicon carbide substrate according to an embodiment of the present invention; Figure 6 This is a schematic diagram of the structure of a silicon carbide substrate after the third oxide layer deposition, according to an embodiment of the present invention. Detailed Implementation

[0021] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0022] It should be noted that the above detailed descriptions are exemplary and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0023] like Figure 1 As shown, a method for preparing the gate oxide layer of a trench-gate silicon carbide MOSFET in one embodiment of this application includes the following steps: Step 1: After etching the gate trenches on the silicon carbide substrate, the silicon carbide substrate is loaded into the high-temperature furnace tube; In this step, a dry trench etching process is used to etch the gate trench. This dry trench etching process can be either inductively coupled plasma etching (ICP) or reactive ion etching (RIE). Taking the fabrication of the gate trench of a SiC UMOSFET using inductively coupled plasma (ICP) etching as an example, the specific steps are as follows: Photoresist is coated on a SiC substrate, and the patterned window of the gate trench is precisely formed by photolithography and development. Using photoresist as a mask, in a specific gas atmosphere (usually a fluorine-containing gas, such as S) ICP etching is performed under these conditions. By independently controlling the plasma density and bias voltage, a high etching rate and good anisotropy are achieved, thereby forming gate trenches with steep sidewalls and flat bottoms. After etching, the photoresist mask is completely removed and the surface is cleaned to obtain a clean and uncontaminated trench surface, preparing it for subsequent gate oxide growth.

[0024] Step 2: In an atmosphere of initial temperature and oxidizing gas, perform the first oxide layer growth on the silicon carbide substrate forming the gate trench, such as... Figure 2 As shown; In this step, the first temperature is 1100℃-1300℃, and the oxidizing gas is one of oxygen, nitric oxide, or nitrogen dioxide. The thickness of the oxide layer formed after the first oxide layer growth is 5-15 nm. This oxide layer is a SiO2 oxide layer. Growing silicon oxide using an oxidation method ensures the quality of the SiC and SiO2 interface. The specific steps are as follows: Under the protection of an inert gas (such as argon or nitrogen), the temperature of the reaction chamber is rapidly raised to the target temperature (1100°C–1300°C), and the wafer temperature is stabilized and uniform. A selected oxidizing gas (such as high-purity gas) is introduced into the reaction chamber. NO or N The oxidation reaction is carried out under set high temperature and pressure. By precisely controlling the oxidation temperature and time (usually within a few minutes to tens of minutes), a dense and uniform silicon dioxide film with a thickness of 5–15 nm is grown on the silicon carbide surface.

[0025] After oxidation is complete, the oxidizing gas supply is stopped, and the wafer is cooled under an inert atmosphere until it reaches a safe temperature before being removed. This high-temperature process effectively improves the quality of the oxide layer and reduces the interface state density.

[0026] Step 3: Perform a second oxide layer deposition on the silicon carbide substrate after the first oxide layer growth, such as... Figure 3 As shown, a first high-temperature heat treatment is performed at a second temperature; In this step, a second oxide layer is deposited using a CVD process, with a thickness of 150-250 nm. The specific method is as follows: The cleaned SiC substrate is fed into the CVD reaction chamber and heated to a set temperature (e.g., 300-450°C). The most commonly used gas introduced into the reaction chamber is silane (SiO2). ) and laughing gas ( A mixture of gases (O) reacts chemically on the surface of silicon carbide to form solid silicon dioxide (Si). And it is evenly deposited on the sidewalls and bottom of the trench; After deposition, the film is subjected to high-temperature annealing in an inert gas atmosphere (such as nitrogen) to improve the density and electrical properties of the oxide layer. The second temperature of this step is 800℃-1100℃, and the first high-temperature heat treatment is carried out in an atmosphere of a single gas of nitrogen, hydrogen and argon or a mixture of two or more of them for 30-180 minutes. This process can overcome the limitation of SiC substrate crystal orientation on oxidation rate, and form a uniform silicon dioxide film on the surface of different crystal orientations of the trench, effectively solving the problem of non-uniformity in thermal oxidation process.

[0027] Step 4: After unloading the silicon carbide substrate from the high-temperature furnace tube, apply photoresist to the oxide layer at the bottom of the gate trench for protection, such as... Figure 4 As shown; In this step, the temperature of the high-temperature furnace tube is reduced to the temperature required for the unloading process, and the silicon carbide substrate after high-temperature heat treatment is unloaded. The silicon carbide substrate undergoes coating, photolithography, and development processes, and the oxide layer at the bottom of the trenches is protected with photoresist. The specific steps are as follows: Photoresist coating: First, a layer of photoresist is uniformly coated onto the surface of the silicon carbide wafer after oxide layer deposition using a spin coating method. By controlling the rotation speed, a photoresist film with uniform thickness that can well cover the trench structure is obtained.

[0028] Soft baking: Soft baking is then performed, in which the solvent in the photoresist is evaporated by moderate heating, so that it is solidified and stabilized, in preparation for subsequent exposure.

[0029] Photolithography (exposure): A specially designed photomask is used, with a pattern designed to expose the trench sidewalls and wafer planar areas while precisely covering and protecting the trench bottom. After aligning the photomask with the wafer, ultraviolet light exposure is performed, causing a photochemical reaction in the photoresist in the illuminated areas.

[0030] Development: After exposure, the image is treated with a specific developer. The developer dissolves the photoresist areas exposed to ultraviolet light during exposure (i.e., the trench sidewalls and wafer planes), while the photoresist at the bottom of the trenches that was not exposed is retained.

[0031] Hard baking: Finally, hard baking is performed, which strengthens the remaining photoresist by reheating it, forming a corrosion-resistant barrier, thereby reliably protecting the critical oxide layer at the bottom of the trench in subsequent wet or dry etching processes.

[0032] Step 5: After etching away the oxide layer on the sidewalls of the gate trench using an etching process, as shown... Figure 5 As shown, the photoresist at the bottom of the gate trench is removed; In this step, anisotropic dry etching is used, such as reactive ion etching (RIE). The specific etching steps are as follows: The wafer, which has been protected with photoresist on the bottom, is sent into the RIE etching chamber; Introduce etching gas (such as fluorine-containing C) or CH In a plasma environment, energetic ions are generated. Under the influence of an electric field, these ions primarily bombard the wafer surface perpendicularly. Vertically oriented ions can effectively bombard and etch away the oxide layer located on the trench sidewalls and wafer planes that is not protected by photoresist. Due to the directionality of ion bombardment, horizontally oriented photoresist can effectively block the etching of the underlying oxide layer. Endpoint detection and resist removal: The etching process is monitored through endpoint detection technology, and etching is stopped immediately once the sidewall oxide layer is completely removed.

[0033] Finally, the remaining photoresist is removed through a photoresist stripping process, resulting in a trench structure with clean sidewalls and a well-preserved thick oxide layer at the bottom.

[0034] Step 6: Deposit a third oxide layer on the silicon carbide substrate, such as... Figure 6 As shown, a second high-temperature heat treatment was performed at the third temperature in a nitrogen-containing gas atmosphere; In this step, a third oxide layer is deposited using thermal oxidation, atomic layer deposition, or LPCVD processes, with the deposited oxide layer having a thickness of 45-60 nm.

[0035] Taking atomic layer deposition (ALD) as an example, the specific steps for the third oxide layer deposition are as follows: The cleaned silicon carbide wafer is fed into the ALD reaction chamber and heated to a suitable temperature (usually 200-300°C).

[0036] Precursor pulse and surface reaction steps: First precursor pulse: A silicon source precursor (such as trimethylaluminum, TMA, or SiC) is pulsed into the cavity. This allows it to be chemically adsorbed onto the wafer (including all surfaces within the trenches), forming a monolayer molecular film.

[0037] Purging: Inert gas (such as argon or nitrogen) is introduced to completely purge away any remaining precursors and byproducts.

[0038] Second precursor pulse and film formation: Second precursor pulse: The pulse introduces an oxygen source (such as water vapor), O or It reacts chemically with the adsorbed silicon source precursor molecules to generate silicon dioxide (Si). The film is thinned and byproducts are released.

[0039] Purging: Inert gas is introduced again to purge and ensure that reaction byproducts are completely removed.

[0040] Cycling and Thickness Control: The four steps described above (pulse A-purge-pulse B-purge) constitute a complete ALD cycle, and each cycle can precisely grow an oxide layer of a specific thickness (approximately 0.1-0.2 nm). By precisely setting the number of cycles, an oxide layer of the target thickness (45-60 nm) can be obtained, achieving nanoscale precision control.

[0041] Choosing the ALD process can form a completely uniform and defect-free oxide layer on the sidewalls and bottom of trenches with a large depth-to-width ratio, fundamentally solving the problem of inhomogeneity caused by differences in crystal orientation in thermal oxidation.

[0042] The third temperature is 1100℃-1300℃, and the nitrogen-containing gas is a single nitrogen-containing gas or a mixture of two or more nitrogen-containing gases, including nitric oxide, nitrogen, nitrogen dioxide, nitrous oxide, and ammonia. The second high-temperature heat treatment lasts for 30-180 minutes.

[0043] Step 7: Perform a third high-temperature heat treatment on the silicon carbide substrate at the fourth temperature and in an inert gas atmosphere to complete the preparation of the gate oxide layer.

[0044] In this step, the fourth temperature is 1200℃-1400℃, the inert gas is a single gas or a mixture of two or more gases, namely argon, nitrogen and hydrogen, and the time for the third high-temperature treatment is 30-180 minutes.

[0045] The above-described method for fabricating the gate oxide layer of a trench-gate silicon carbide MOSFET has the following advantages: First, silicon oxide is grown on the etched SiC gate trench using an oxidation method to ensure the interface quality between SiC and SiO2. Then, SiO2 of about 200nm is grown using CVD to ensure the SiO2 thickness at the bottom of the trench to improve the gate oxide reliability of the device. Next, the oxide layer is subjected to high-temperature annealing heat treatment to make the oxide layer more dense. Then, a photolithography process is performed to retain the oxide layer at the bottom of the trench while etching away the sidewall oxide layer. After resist removal, a gate oxide layer of approximately 50 nm is grown on the sidewalls. After two high-temperature annealing processes, the final oxide layer of the trench gate is fully formed. The sidewall oxide layer, with a thickness of approximately 50 nm, provides good interface quality; the bottom oxide layer, with a thickness of approximately 200 nm, effectively protects the gate oxide layer and improves the reliability of the gate dielectric.

[0046] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0047] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that the embodiments of this application described herein can be implemented in sequences other than those illustrated or described herein.

[0048] Furthermore, the terms “comprising” and “having”, and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such process, method, product, or apparatus.

[0049] For ease of description, spatial relative terms such as "above," "on top of," "on the upper surface of," "above," etc., are used herein to describe the spatial positional relationship of a device or feature as shown in the figures to other devices or features. It should be understood that spatial relative terms are intended to encompass different orientations in use or operation beyond the orientation of the device as described in the figures. For example, if the device in the figures were inverted, a device described as "above" or "on top of" other devices or structures would subsequently be positioned as "below" or "under" other devices or structures. Thus, the exemplary term "above" can include both "above" and "below." The device may also be positioned in other different ways, such as rotated 90 degrees or in other orientations, and the spatial relative descriptions used herein will be interpreted accordingly.

[0050] In the detailed description above, reference has been made to the accompanying drawings, which form part of this document. In the drawings, similar symbols typically identify similar parts unless the context otherwise indicates otherwise. The illustrated embodiments described in the detailed specification, drawings, and claims are not intended to be limiting. Other embodiments may be used and other changes may be made without departing from the spirit or scope of the subject matter presented herein.

[0051] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for fabricating a gate oxide layer of a trench-gate silicon carbide MOSFET, characterized in that, The method comprises the following steps: Step 1: after etching the gate trench on the silicon carbide substrate, the silicon carbide substrate is loaded into a high-temperature furnace tube; Step 2: the silicon carbide substrate with the gate trench is subjected to first oxidation layer growth in an atmosphere of a first temperature and an oxidizing gas; Step 3: the silicon carbide substrate with the first oxidation layer growth is subjected to second oxidation layer deposition and first high-temperature heat treatment at a second temperature; Step 4: after the silicon carbide substrate is unloaded from the high-temperature furnace tube, photoresist is coated on the oxidation layer at the bottom of the gate trench for protection; Step 5: after the oxidation layer on the sidewall of the gate trench is etched away by using an etching process, the photoresist at the bottom of the gate trench is removed; Step 6: the silicon carbide substrate is subjected to third oxidation layer deposition and second high-temperature heat treatment at a third temperature and in an atmosphere containing nitrogen gas; Step 7: the silicon carbide substrate is subjected to third high-temperature heat treatment at a fourth temperature and in an atmosphere of an inert gas, so as to complete the preparation of the gate oxide layer.

2. The trench-gate silicon carbide MOSFET gate-level oxidation layer preparation method according to claim 1, characterized in that, In step 1, the dry trench etching process, i.e. inductive coupled plasma etching or reactive ion etching, is used for etching the gate trench.

3. The method of claim 1, wherein the trench-gate SiC MOSFET gate-level oxide is formed by: In step 2, the first temperature is 1100-1300℃, and the oxidizing gas is one of oxygen, nitric oxide and nitrogen dioxide.

4. The method of claim 1, wherein the trench-gate silicon carbide MOSFET gate- level oxide layer is formed by: The thickness of the oxidation layer generated after the first oxidation layer growth is 5-15nm.

5. The method of claim 1, wherein the trench-gate silicon carbide MOSFET gate- level oxide layer is formed by: In step 3, the CVD process is used for second oxidation layer deposition, and the thickness of the second oxidation layer deposition is 150-250nm.

6. The method of claim 1, wherein the trench-gate silicon carbide MOSFET gate- level oxide layer is formed by: The second temperature is 800-1100℃, and the first high-temperature heat treatment is performed in an atmosphere of a single gas or a mixed gas of two or more of nitrogen, hydrogen and argon.

7. The method of claim 1, wherein the trench-gate silicon carbide MOSFET gate- level oxide layer is formed by: In step 6, the third oxidation layer deposition is performed by using the thermal oxidation, atomic layer deposition or LPCVD process, and the thickness of the deposited oxidation layer is 45-60nm.

8. The method of claim 1, wherein the trench-gate silicon carbide MOSFET gate- level oxide layer is formed by: The third temperature is 1100-1300℃, and the nitrogen-containing gas is one of nitric oxide, nitrogen, nitrogen dioxide, nitrous oxide and ammonia.

9. The method of producing a trench-gate silicon carbide MOSFET gate-level oxide layer according to Claim 1, wherein The fourth temperature is 1200-1400℃, and the inert gas is one of argon, nitrogen and hydrogen or a mixed gas of two or more thereof.

10. The method of claim 1, wherein the trench-gate silicon carbide MOSFET gate- level oxide layer is formed by: The time of the first high-temperature treatment, the second high-temperature treatment and the third high-temperature treatment is 30-180min.

Images