Display substrate and preparation method thereof, display panel and display device

Abstract

The invention discloses a display substrate and a preparation method thereof, a display panel and a display device. The display substrate comprises a substrate and at least one first transistor, and the first transistor is located on one side of the substrate; the first transistor comprises a first active layer, a first grid electrode and a second grid electrode; the first grid electrode is located on one side, away from the substrate, of the first active layer; the second grid electrode is located on the side, close to the substrate, of the first active layer, is coupled with the first grid electrode and the first active layer and is used for controlling on-off of the first active layer based on an electric signal provided by the first grid electrode. Under the condition that on-off of the first active layer is controlled based on an electric signal provided by the first grid electrode, capacitance of a control end formed by connecting the two capacitors in series is smaller, so that the size of the first active layer and the thickness of the first insulating layer and the thickness of the second insulating layer are not increased, the sub-threshold swing of the first transistor is increased, and gray scale expansion under low brightness is improved.

Description

Technical Field

[0001] This application belongs to the field of display panel technology, and particularly relates to a display substrate and its preparation method, a display panel and a display device. Background Technology

[0002] Currently, organic light-emitting diode (OLED) displays and flat panel displays based on light-emitting diode (LED) technologies are widely used and have become the mainstream in display devices due to their advantages such as high image quality, energy saving, thin body, and wide range of applications. Among these technologies, display devices that use low-temperature polycrystalline silicon (LTPS) and metal oxide (Oxide) as the first active layer materials of thin-film transistors have attracted much attention. Summary of the Invention

[0003] To address the problems existing in the prior art, the purpose of this application is to provide a display substrate and its preparation method, a display panel, and a display device.

[0004] A first aspect of this application provides a display substrate, comprising: a substrate; at least one first transistor, the first transistor being located on one side of the substrate; the first transistor comprising a first active layer, a first gate, and a second gate; the first gate being located on the side of the first active layer away from the substrate; and the second gate being located on the side of the first active layer close to the substrate, wherein the orthographic projection of the second gate on the substrate at least partially overlaps with the orthographic projection of the first active layer on the substrate, and the orthographic projection of the second gate on the substrate at least partially overlaps with the orthographic projection of the first gate on the substrate.

[0005] In one embodiment, the orthographic projection of the first active layer on the substrate and the orthographic projection of the first gate on the substrate do not overlap.

[0006] Preferably, the first active layer includes a channel region and a first doped region and a second doped region located on both sides of the channel region; a portion of the orthogonal projection of the second gate on the substrate at least partially overlaps with the orthogonal projection of the channel region on the substrate, and another portion of the orthogonal projection of the second gate on the substrate at least partially overlaps with the orthogonal projection of the first gate on the substrate.

[0007] In one embodiment, a barrier layer is further included, located on the side of the first active layer away from the substrate, wherein the orthographic projection of the barrier layer on the substrate at least partially overlaps with the orthographic projection of the channel region on the substrate.

[0008] In one embodiment, the barrier layer is made of conductive metal.

[0009] In one embodiment, the first transistor further includes a first source and a first drain, the first source being connected to the first doped region and the first drain being connected to the second doped region.

[0010] In one embodiment, a first insulating layer, a second insulating layer, and a third insulating layer are sequentially stacked along a direction away from the substrate; the second gate is disposed on the side of the first insulating layer near the substrate, the first active layer is disposed on the side of the second insulating layer near the substrate, and the first gate is disposed on the side of the second insulating layer away from the substrate.

[0011] In one embodiment, a second transistor is further included, one end of which is electrically connected to the second gate.

[0012] A second aspect of this application provides a method for fabricating a display substrate, comprising: constructing a substrate, a second gate, and a semiconductor layer sequentially from bottom to top, and patterning the semiconductor layer; implanting doped ions into a portion of the semiconductor layer to obtain a first active layer; constructing a first gate on the side of the first active layer away from the substrate; wherein the second gate is coupled to both the first gate and the first active layer, and is used to control the on / off state of the first active layer based on an electrical signal provided by the first gate.

[0013] A third aspect of this application provides a display panel, including a display substrate as described above and a plurality of light-emitting units disposed on the display substrate, wherein a first transistor of the display substrate corresponds one-to-one with the light-emitting units and the first transistor is electrically connected to the corresponding light-emitting unit.

[0014] A fourth aspect of this application provides a display device including a display substrate as described above.

[0015] The beneficial effects of this application embodiment compared with the prior art are as follows: the second gate is coupled to the first gate and the first active layer respectively, thereby forming two capacitors between the second gate and the first gate and between the second gate and the first active layer respectively. The capacitance of the control terminal formed by the two capacitors connected in series is small. If the on and off of the first active layer is controlled based on the electrical signal provided by the first gate, the subthreshold swing of the first transistor can be increased without increasing the size of the first active layer and the thickness of the first insulating layer and the second insulating layer, thereby improving the grayscale development of the display substrate at low brightness. Attached Figure Description

[0016] Figure 1This is a cross-sectional schematic diagram of a display substrate provided in an embodiment of this application; Figure 2 This is another cross-sectional schematic diagram of a display substrate provided in an embodiment of this application; Figure 3 A cross-sectional schematic diagram of a second transistor provided in an embodiment of this application; Figure 4 A flowchart illustrating a method for fabricating a display substrate according to an embodiment of this application; Figure 5 A cross-sectional schematic diagram of the device structure obtained after performing step S100; Figure 6 This is a cross-sectional schematic diagram of the device structure obtained by first constructing the first gate and barrier layer and then implanting doped ions. Figure 7 This is a schematic diagram of a display device provided in an embodiment of this application.

[0017] Reference numerals: 10, display substrate; 20, display device; 100, substrate; 200, first transistor; 210, first active layer; 211, channel region; 212, first doped region; 213, second doped region; 214, first source; 215, first drain; 220, first gate; 230, second gate; 240, barrier layer; 300, first insulating layer; 400, second insulating layer; 500, third insulating layer; 600, second transistor; 610, second active layer; 620, fourth gate; 630, second source; 640, second drain; 700, semiconductor layer. Detailed Implementation

[0018] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0019] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0020] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0021] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0022] In the field of display panel technology, for display devices composed of Organic Light Emitting Diodes (OLEDs), Thin Film Transistors (TFTs) are the core components of OLEDs, and the performance of TFT devices directly affects the display effect of the display device. In recent years, the technological development of TFT devices constructed from oxides such as indium gallium zinc oxide (IGZO), indium tin oxide (IZO), and indium oxide (InO) has gradually matured, becoming the preferred material for the backplane of large-size products in high-generation Active-matrix Organic Light-Emitting Diodes (AMOLEDs).

[0023] However, current TFT devices struggle to balance mobility (Mob) and subthreshold swing (SS). When using high-mobility materials to construct TFT devices, the subthreshold swing becomes very small, failing to meet the low grayscale requirements of AMOLED displays. Traditional TFT device manufacturing typically increases the subthreshold swing by increasing the device channel length or the thickness of the insulating layer. However, due to the limited space within the display, increasing the channel length has limited effectiveness in increasing the subthreshold swing, while increasing the thickness of the insulating layer can easily lead to excessive device stress and excessive etching pressure.

[0024] Therefore, this application is made in order to at least alleviate or solve the above-mentioned technical problems to some extent.

[0025] Figure 1 A schematic diagram of a display substrate provided in an embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and the details are as follows: The display substrate includes a substrate 100 and at least one first transistor 200. The first transistor 200 is located on one side of the substrate 100. One first transistor 200 can correspond to one light-emitting unit.

[0026] The substrate 100 can be made of a flexible material, such as at least one of polyethylene terephthalate (PET), polyimide (PI), and cyclic olefin polymer (COP). The substrate 100 can also be made of a rigid material, such as glass.

[0027] Specifically, the first transistor 200 includes a first active layer 210, a first gate 220, and a second gate 230.

[0028] The first gate 220 is located on the side of the first active layer 210 away from the substrate 100. The second gate 230 is located on the side of the first active layer 210 close to the substrate 100. The orthographic projection of the second gate 230 on the substrate 100 at least partially overlaps with the orthographic projection of the first active layer 210 on the substrate 100, and the orthographic projection of the second gate 230 on the substrate 100 at least partially overlaps with the orthographic projection of the first gate 220 on the substrate 100.

[0029] The second gate 230 is used to control the switching on and off of the first active layer 210 based on the electrical signal provided by the first gate 220. The first transistor 200 can be a driving thin-film transistor (DTFT). Since the second gate 230 is coupled to both the first gate 220 and the first active layer 210, two capacitors are formed between the second gate 230 and the first gate 220, and between the second gate 230 and the first active layer 210, respectively. The capacitance of the control terminal formed by the two capacitors connected in series is small. When the switching on and off of the first active layer 210 is controlled based on the electrical signal provided by the first gate 220, the subthreshold swing of the first transistor 200 is increased.

[0030] It should be noted that the formula for calculating the subthreshold swing is: (1) In equation (1), k is the Boltzmann constant, T is the temperature, q is the charge of the electron, and C is the temperature. d C is the capacitance per unit area of ​​the depletion region. it Let SS be the capacitance per unit area of ​​the surface where the active layer contacts the dielectric layer, and C be the subthreshold swing. OX C is the total capacitance of the gate of the first transistor 200. OX The calculation formula is: (2) In equation (2), C OX1 C is the first coupling capacitance formed between the second gate 230 and the first gate 220. OX2 It is the second coupling capacitor formed between the second gate 230 and the first active layer 210.

[0031] Therefore, compared to traditional transistors, according to equation (2), in this embodiment, after forming two coupling capacitors through the first gate 220, the second gate 230, and the first active layer 210, the total capacitance C is... OX It will increase. In the total capacitance C OX After the increase, according to equation (1), the subthreshold swing SS of the first transistor 200 will decrease accordingly to meet the requirements of the display substrate for low grayscale expansion.

[0032] The first active layer 210 can be made of metal oxides. Specifically, the metal oxides can include oxides such as indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium tin oxide (IZO), and indium oxide (InO).

[0033] For example, in one embodiment, a portion of the orthographic projection of the second gate 230 on the substrate 100 at least partially overlaps with the orthographic projection of the first active layer 210 on the substrate 100, and another portion of the orthographic projection of the second gate 230 on the substrate 100 at least partially overlaps with the orthographic projection of the first gate 220 on the substrate 100. In this case, the second gate 230 can be coupled to both the first gate 220 and the first active layer 210.

[0034] In some embodiments, the orthographic projection of the first gate 220 on the substrate 100 does not overlap with the orthographic projection of the first active layer 210 on the substrate 100.

[0035] It is understandable that there is no direct capacitive coupling between the first gate 220 and the first active layer 210, but only indirect electrical signal control is achieved through the second gate 230, which helps to more accurately regulate the on / off characteristics of the first active layer 210.

[0036] In one embodiment, such as Figure 2 As shown, the first active layer 210 includes a channel region 211 and a first doped region 212 and a second doped region 213 located on both sides of the channel region 211.

[0037] The first doped region 212 and the second doped region 213 can be obtained by implanting dopant ions of a certain concentration into the semiconductor material, thereby realizing the conductor of the semiconductor material. The first doped region 212 and the second doped region 213 can form ohmic contacts with the corresponding metal electrodes. By controlling the voltage coupled from the second gate 230 to the channel region 211, the on and off states of the active region can be controlled.

[0038] Specifically, the first doped region 212 and the second doped region 213 can be obtained by implanting boron ions, fluorine ions, or other ions into the semiconductor material. This embodiment does not limit the specific structure of the first doped region 212 and the second doped region 213 or the doping ions.

[0039] In one embodiment, a portion of the orthographic projection of the second gate 230 onto the substrate 100 at least partially overlaps with the orthographic projection of the channel region 211 onto the substrate 100.

[0040] When a portion of the orthographic projection of the second gate 230 on the substrate 100 overlaps at least partially with the orthographic projection of the channel region 211 on the substrate 100, the second gate 230 and the channel region 211 can be coupled to form a second coupling capacitor. The specific parameters of the second coupling capacitor are determined by the spacing between the second gate 230 and the channel region 211, the dielectric material between the second gate 230 and the channel region 211, and the overlapping area between the second gate 230 and the channel region 211.

[0041] In some embodiments, the orthographic projection of the channel region 211 on the substrate 100 at least partially overlaps within the orthographic projection of the second gate 230 on the substrate 100. At this time, the channel region 211 and the second gate 230 are fully coupled. Under the condition that the size of the channel region 211 and other parameters remain unchanged, the capacitance of the second coupling capacitor formed reaches its maximum value.

[0042] In one embodiment, such as Figure 2 As shown, the display substrate also includes a barrier layer 240, which is located on the side of the first active layer 210 away from the substrate 100. The orthographic projection of the barrier layer 240 on the substrate 100 at least partially overlaps with the orthographic projection of the channel region 211 on the substrate 100.

[0043] The barrier layer 240 can be used as an implantation mask for the channel region 211 when implanting ions into the first doped region 212 and the second doped region 213. At the same time, the barrier layer 240 can also block light to prevent light from shining into the channel region 211 and affecting the performance of the first transistor 200.

[0044] In one embodiment, the barrier layer 240 is made of conductive metal and can serve as the third gate of the first transistor 200. The third gate can also be used to control the on / off state of the first active layer 210. The barrier layer 240 can be made of the same material as the first gate 220 and connected to the corresponding control circuit to obtain a control signal.

[0045] It is understandable that, since the material of the third gate is a conductive metal, the third gate can achieve the effects of blocking ion implantation and light shielding. At the same time, when necessary, the third gate can also replace the first gate 220 and the second gate 230 to control the first transistor 200.

[0046] In one embodiment, such as Figure 2 As shown, the first transistor 200 also includes a first source 214 and a first drain 215. The first source 214 is connected to the first doped region 212, and the first drain 215 is connected to the second doped region 213.

[0047] The first source electrode 214 specifically includes a first source electrode, and the first drain electrode 215 specifically includes a first drain electrode. The first source electrode and the first drain electrode can be connected to the first doped region 212 and the second doped region 213 respectively through corresponding vias. The first source electrode and the first drain electrode can be connected to other circuits. The specific location and size of the first source electrode and the first drain electrode can be set according to actual needs. This embodiment does not limit the parameters of the first source electrode and the first drain electrode.

[0048] The first source electrode and the first drain electrode can be formed from pure metal materials or alloy materials such as molybdenum, aluminum, titanium, copper, and tungsten. They can also be formed from a stacked combination of different metals. Either the first source electrode or the first drain electrode can be used to electrically connect to a light-emitting unit such as an OLED or LED. When the first transistor 200 is turned on, it can transmit a driving electrical signal, which can then be used to illuminate the corresponding light-emitting unit.

[0049] In some embodiments, the first source electrode and the first drain electrode may be disposed on the side of the barrier layer 240 away from the substrate 100.

[0050] In one embodiment, such as Figure 2 As shown, the display substrate also includes a first insulating layer 300, a second insulating layer 400 and a third insulating layer 500, which are sequentially stacked along a direction away from the substrate 100.

[0051] The second gate 230 is disposed on the side of the first insulating layer 300 near the substrate 100, the first active layer 210 is disposed on the side of the second insulating layer 400 near the substrate 100, and the first gate 220 and the barrier layer 240 are disposed on the side of the second insulating layer 400 away from the substrate 100.

[0052] The first gate 220 and the barrier layer 240 can be made of the same material. By setting the first gate 220 and the barrier layer 240 in the same layer, the number of process layers during the fabrication of the display substrate can be reduced, thereby reducing the complexity of the display substrate fabrication process and reducing manufacturing costs.

[0053] The first insulating layer 300 and the second insulating layer 400 are used to support and fix the first active layer 210, the first gate 220, the second gate 230, and the barrier layer 240. Specifically, the first insulating layer 300 and the second insulating layer 400 can be gate insulating layers (GI). The third insulating layer 500 can specifically be an inter-layer dielectric (ILD).

[0054] The materials of the first insulating layer 300, the second insulating layer 400, and the third insulating layer 500 can be inorganic materials of oxide or nitride. The first insulating layer 300, the second insulating layer 400, and the third insulating layer 500 can all be deposited using at least one of silicon nitride, silicon oxide, or silicon oxynitride via chemical vapor deposition (CVD). The materials of the first insulating layer 300, the second insulating layer 400, and the third insulating layer 500 can be the same or different.

[0055] In this embodiment, because the method of constructing a first coupling capacitor and a second coupling capacitor is used to increase the subthreshold swing, a thinner first insulating layer 300 and a thinner second insulating layer 400 can be used.

[0056] A conductive layer may also be provided on the side of the third insulating layer 500 away from the substrate 100. The conductive layer can be electrically connected to the inside of the display substrate through corresponding vias, or it can be electrically connected to external circuits.

[0057] It is understood that the conductive layer may include a first source electrode and a first drain electrode.

[0058] Specifically, the third insulating layer 500 can cover the side surface of the second insulating layer 400, the first gate 220 and the barrier layer 240 away from the substrate 100, thereby protecting the second insulating layer 400, the first gate 220 and the barrier layer 240.

[0059] In one embodiment, the display substrate further includes a voltage initialization circuit connected to the second gate 230, which is used to initialize the voltage of the second gate 230.

[0060] Before the second gate 230 receives an electrical signal from the first gate 220, its voltage can be initialized by a voltage initialization circuit. This stabilizes the voltage of the second gate 230 and prevents instability in the conduction threshold of the first transistor 200 caused by voltage instability in the second gate 230. The initialization voltage of the second gate 230 can also be set according to the specific requirements of the first transistor 200.

[0061] Specifically, in some embodiments, the voltage initialization circuit includes a second transistor 600, one end of which can be electrically connected to the second gate 230, and the other end of which can be connected to an initialization voltage source. When the second transistor 600 is turned on, it can provide an initialization voltage to the second gate 230. The second transistor 600 can be an STFT device.

[0062] In some embodiments, the second transistor 600 includes a second active layer 610, a fourth gate 620, a second source 630, and a second drain 640. The second active layer 610 and the first active layer 210 can be disposed on the same layer, the fourth gate 620 can be disposed on the same layer as the first gate 220, and the second source 630, the second drain 640, the first source 214, and the first drain 215 can be disposed on the same layer.

[0063] The second drain 640 can be connected to the second gate 230 through a corresponding via. When the second transistor 600 is turned on, the second transistor 600 can provide an initialization voltage to the second gate 230.

[0064] Figure 4 A flowchart of a method for fabricating a display substrate according to an embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and are described in detail below: The method for preparing a display substrate includes steps S100 to S300.

[0065] Step S100: Construct a substrate, a second gate, and a semiconductor layer sequentially from bottom to top, and pattern the semiconductor layer.

[0066] Specifically, after forming the second gate 230 and before constructing the semiconductor layer 700, a first insulating layer 300 can be constructed first, resulting in a device structure as shown below. Figure 5 As shown.

[0067] Step S200: Dopant ions are implanted into a portion of the semiconductor layer to obtain the first active layer.

[0068] Step S300: Construct a first gate on the side of the first active layer away from the substrate.

[0069] The second gate 230 is coupled to the first gate 220 and the first active layer 210 respectively, and is used to control the on / off state of the first active layer 210 based on the electrical signal provided by the first gate 220.

[0070] The preparation method of this example can be used to prepare a display substrate as described in any of the above embodiments.

[0071] In some embodiments, step S300 may be executed before step S200, specifically, as follows: Figure 6 As shown, a second insulating layer 400, a first gate 220, and a barrier layer 240 can be constructed on the first insulating layer 300 and the semiconductor layer 700, wherein the barrier layer 240 can be used as an implantation mask for doped ions, thereby reducing the manufacturing process and cost of constructing additional masks.

[0072] One embodiment of this application provides a display panel, which includes a display substrate as described in any of the above embodiments and a plurality of light-emitting units disposed on the display substrate. A first transistor 200 of the display substrate corresponds one-to-one with a light-emitting unit and is electrically connected to the corresponding light-emitting unit.

[0073] It is understood that when the first transistor 200 is turned on, it can transmit a driving electrical signal to the corresponding light-emitting unit to light up the light-emitting unit. The specific structure of the light-emitting unit and the specific parameters of the driving electrical signal are not limited in this application embodiment.

[0074] In one embodiment, a first transistor 200 can form a driving unit with an adjacent second transistor 600. The driving unit can correspond one-to-one with the light-emitting unit and the driving unit is electrically connected to the corresponding light-emitting unit.

[0075] Specifically, multiple light-emitting units can be arranged in a certain array on the display substrate according to actual needs, but this embodiment does not limit them.

[0076] The multiple light-emitting units may include light-emitting units of three colors, specifically, the three colors of light-emitting units are red light-emitting units, green light-emitting units and blue light-emitting units.

[0077] Figure 7 A schematic diagram of a display device according to an embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and the details are as follows: The display device 20 includes a display substrate 10 or a display panel as described in any of the above embodiments. Since the display device 20 includes the display substrate 10 of any of the above embodiments, the display device 20 has the beneficial effects of the display substrate 10 of any of the above embodiments, which will not be described again here.

[0078] The display device 20 in this application embodiment includes, but is not limited to, mobile phones, personal digital assistants (PDAs), tablet computers, e-books, televisions, access control systems, smart landline phones, control consoles, and other devices with display functions.

[0079] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0080] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0081] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A display substrate, characterized by, Comprising: a substrate (100); at least one first transistor (200) located on one side of the substrate (100); the first transistor (200) comprising a first active layer (210), a first gate (220) and a second gate (230); the first gate (220) is located on the side of the first active layer (210) away from the substrate (100); the second gate (230) is located on the side of the first active layer (210) close to the substrate (100), the orthogonal projection of the second gate (230) on the substrate (100) at least partially overlaps with the orthogonal projection of the first active layer (210) on the substrate (100), and the orthogonal projection of the second gate (230) on the substrate (100) at least partially overlaps with the orthogonal projection of the first gate (220) on the substrate (100). 2.The display substrate of claim 1, wherein, The orthogonal projection of the first active layer (210) on the substrate (100) and the orthogonal projection of the first gate (220) on the substrate (100) do not overlap each other; Preferably, the first active layer (210) comprises a channel region (211) and first and second doped regions (212, 213) located on both sides of the channel region (211); a part of the orthogonal projection of the second gate (230) on the substrate (100) at least partially overlaps with the orthogonal projection of the channel region (211) on the substrate (100), and another part of the orthogonal projection of the second gate (230) on the substrate (100) at least partially overlaps with the orthogonal projection of the first gate (220) on the substrate (100). 3.The display substrate of claim 2, wherein, Further comprising a barrier layer (240) located on the side of the first active layer (210) away from the substrate (100), the orthogonal projection of the barrier layer (240) on the substrate (100) at least partially overlaps with the orthogonal projection of the channel region (211) on the substrate (100). 4.The display substrate of claim 3, wherein, The material of the barrier layer (240) is a conductive metal. 5.The display substrate of claim 2, wherein, The first transistor (200) further comprises a first source (214) and a first drain (215), the first source (214) is connected with the first doped region (212), and the first drain (215) is connected with the second doped region (213). 6.The display substrate of claim 1, wherein, Further comprising a first insulating layer (300), a second insulating layer (400) and a third insulating layer (500) sequentially stacked in the direction away from the substrate (100); The second gate (230) is located on the side of the first insulating layer (300) close to the substrate (100), the first active layer (210) is located on the side of the second insulating layer (400) close to the substrate (100), and the first gate (220) is located on the side of the second insulating layer (400) away from the substrate (100). 7.The display substrate of any one of claims 1 to 6, wherein, Further comprising a second transistor (600), one end of the second transistor (600) is electrically connected with the second gate (230).

8. A method for preparing a display substrate, characterized in that, Comprising: A substrate (100), a second gate (230) and a semiconductor layer (700) are sequentially constructed from bottom to top, and the semiconductor layer (700) is subjected to a patterning process; Part of the semiconductor layer (700) is implanted with doped ions to obtain a first active layer (210); A first gate (220) is constructed on a side of the first active layer (210) away from the substrate (100); wherein the second gate (230) is coupled with the first gate (220) and the first active layer (210) respectively, and is used to control the on-off of the first active layer (210) based on an electrical signal provided by the first gate (220).

9. A display panel, characterized by, The display substrate (10) comprises a plurality of light emitting units arranged on the display substrate (10), and the first transistor (200) of the display substrate (10) corresponds to the light emitting units one by one and is electrically connected with the corresponding light emitting units.

10. A display device, characterized by comprising: The display substrate (10) comprises the display substrate (10) according to any one of claims 1 to 7.

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