TGV through hole filling method
By depositing a seed layer in TGV vias through a stepwise sputtering and cooling alternating process, the void defect problem caused by metal surface roughness in TGV vias was solved, achieving defect-free filling and high yield of TGV vias.
Patent Information
- Application Number
- CN202511641602.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-11
- Publication Date
- 2026-02-17
AI Technical Summary
In the prior art, during the sputtering of the seed layer in TGV vias, the high bias power and thick metal layer lead to increased surface roughness of the metal, making it difficult for the electroplating solution to wet evenly, resulting in void defects, which affects the reliability of electrical connections and the yield of devices.
A seed layer is deposited in the TGV via by alternating step sputtering and cooling. This alternating sputtering and cooling method suppresses the coarsening and growth of metal grains, reduces the surface roughness of the seed layer, and wets the seed layer before electroplating to ensure uniform coverage of the electroplating solution.
It achieves defect-free filling of TGV vias, resulting in smooth surfaces, reduced metal surface roughness, improved electroplating wetting effect, and ensures complete filling of TGV vias and high device yield.
Smart Images
Figure CN121548290A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the fields of semiconductor manufacturing and advanced packaging technology, and in particular to a method for filling TGV vias. Background Technology
[0002] With the continuous increase in the size of artificial intelligence chips and the expansion of packaging substrate area, higher demands are being placed on advanced packaging technologies. Among them, TGV (Through Glass Via) technology is considered one of the key technologies for next-generation advanced packaging due to its ability to significantly improve interlayer connection density and enhance signal integrity of high-speed circuits. Currently, TGV vias typically use copper filling to achieve electrical connections between the front and back sides of the glass substrate. The conventional process flow includes laser-induced drilling, wet etching for hole formation, sputtering seed layer, electroplating for hole filling, and chemical mechanical polishing.
[0003] However, in actual electroplating and via filling processes, it has been found that during the sputtering of the seed layer, to improve the bottom coverage of the aspect ratio via, a higher bias power and a thicker metal layer are typically used, with the metal layer thickness reaching 3μm. This results in a significant increase in the surface roughness of the metal, thereby reducing its wettability. The electroplating solution struggles to form a uniform wetting film on the rough surface, hindering the complete filling of the via with metal, ultimately leading to void defects. This severely affects the reliability of electrical connections, resulting in a decrease in device yield. Summary of the Invention
[0004] The purpose of this invention is to overcome the shortcomings of the prior art by providing a method for filling TGV interconnects, which eliminates voids in the TGV interconnects and results in high device yield.
[0005] To achieve the above objectives, the technical solution adopted by the present invention is: a method for filling TGV through-holes, comprising the following steps:
[0006] Form TGV vias on the insulating substrate;
[0007] Seed layers were deposited in the TGV vias by alternating steps of sputtering and cooling.
[0008] TGV cavity filling is performed using an electroplating process;
[0009] The filled TGV vias are planarized to remove excess metal and form TGV interconnects.
[0010] Furthermore, the specific steps of the step-by-step sputtering and cooling alternation process are as follows: the seed layer deposition process is divided into N cyclic steps to be performed until the seed layer reaches a predetermined total thickness, where N≥15, and each cyclic step includes: a sputtering sub-step to deposit a portion of the seed layer in the TGV via; and a cooling sub-step to reduce the temperature of the insulating substrate after the sputtering sub-step.
[0011] Furthermore, after the sputtering step, the method for reducing the temperature of the insulating substrate is either static cooling or cooling by introducing cooling gas.
[0012] Furthermore, the sputtering sub-steps are performed at least 15 times, with each sputtering sub-step lasting 20 to 30 seconds.
[0013] Furthermore, the cooling time for each cooling sub-step is 120 to 180 seconds.
[0014] Furthermore, during the stepwise sputtering deposition of the seed layer, the applied bias power is maintained at no more than 200W.
[0015] Furthermore, before performing TGV via filling through electroplating, the insulating substrate with the seed layer deposited is placed in a vacuum bath for 2 minutes to wet it. After completion, a water film is covered on the wafer metal film.
[0016] Furthermore, the seed layer is a Ti / Cu composite layer.
[0017] Furthermore, the thickness of the seed layer is 2-6 μm.
[0018] Due to the application of the above technical solution, the present invention has the following advantages compared with the prior art:
[0019] This invention employs a stepwise sputtering and cooling alternation mode during seed layer deposition. By decomposing the continuous high-temperature sputtering process into multiple short and controllable sub-steps and forcibly cooling them in between, the coarsening and growth of metal grains and island growth are suppressed. This significantly reduces the surface roughness of the seed layer from over 150 nm to below 50 nm, resulting in a smooth and flat seed layer surface. The smooth seed layer surface allows the electroplating solution to achieve instantaneous and uniform wetting, completely solving the problem of electroplating voids caused by poor wetting. This achieves defect-free and complete filling of TGV through-holes.
[0020] In addition, by reducing the bias power of the step sputtering from 250W to no more than 200W, the excessive bombardment effect of high-energy ions on the deposited metal film is effectively weakened, thereby further reducing the roughness of the metal surface, improving the electroplating wetting effect, and enhancing the filling effect of TGV vias.
[0021] Secondly, this method can be implemented on existing equipment without huge investment. By simply optimizing process parameters and procedures, it can bring about significant improvements in quality and efficiency, and has extremely high industrial application value. Attached Figure Description
[0022] The technical solution of the present invention will be further described below with reference to the accompanying drawings:
[0023] Figure 1 This is a schematic flowchart of a method for filling TGV through holes according to the present invention. Detailed Implementation
[0024] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.
[0025] This invention provides a method for filling TGV vias to solve the problem of void defects in TGV vias formed when sputtering seed layers in the prior art, which seriously affects the reliability of electrical connections and leads to device yield problems.
[0026] For ease of understanding, the specific processes in the embodiments of this application are described below. Please refer to [link / reference]. Figure 1 The present application embodiment provides a method for filling a TGV through-hole, which includes the following steps:
[0027] S1. Form TGV vias on the insulating substrate.
[0028] In this example, the insulating substrate is preferably a glass wafer, such as borosilicate glass; at the same time, it is also suitable for insulating substrates of TGV technology, such as quartz, sapphire, etc., and glass wafers will be used instead of insulating substrates in the following text.
[0029] The specific steps for forming the TGV via in step S1 are as follows: First, the glass wafer is cleaned by a wet cleaning process. The cleaned glass wafer is then placed on a laser equipment stage for laser-induced drilling to modify the glass at the drilling location. Next, a certain concentration of HF acid solution is prepared, and the modified glass wafer is placed in the solution. A wet etching process is then performed for a certain period of time to form the TGV via.
[0030] S2. A seed layer is deposited in the TGV via by alternating step sputtering and cooling. The seed layer in step S2 is a Ti / Cu composite layer, which is a metal seed layer.
[0031] Specifically, the steps include the following: First, a Ti adhesion layer with a thickness of about 500 nm is deposited. This thickness is set to ensure that a continuous, defect-free film is formed within the high aspect ratio TGV via, so as to provide sufficient adhesion and prevent subsequent layer peeling.
[0032] Then, a Cu seed layer with a total thickness of about 2-6 μm is deposited. This thickness is necessary to provide a low-resistance conductive path, ensuring that the current can be evenly distributed to the bottom of the hole during subsequent electroplating to fill the hole.
[0033] The deposition of the Cu seed layer is performed using a stepwise sputtering and cooling alternation method, dividing the Cu layer deposition process into at least fifteen consecutive cyclic steps until the seed layer reaches a predetermined total thickness. Each cyclic step is as follows:
[0034] Sputtering sub-step: A portion of the seed layer is deposited inside the TGV via. The sputtering power of Cu is 16KW, and the bias power is no more than 200W. The duration of each sputtering sub-step is 20~30 seconds. Setting the bias power to no more than 200W can reduce the downward bombardment effect, ensuring the coverage of sputtered metal at the bottom of the via while reducing the roughness of the metal surface.
[0035] Cooling sub-step: After each sputtering sub-step is completed, sputtering is stopped immediately, and the wafer is placed in the cavity for active or passive cooling for 120 to 180 seconds. Passive cooling refers to static cooling, while active cooling involves introducing cooling gas to lower the temperature.
[0036] The above sputtering and cooling steps are repeated at least 15 times until the Cu seed layer reaches the predetermined total thickness.
[0037] The reason for using the above-mentioned step-by-step sputtering and cooling alternation is that under the action of bias power, long-term sputtering will cause the wafer surface temperature to rise sharply, reaching over 180°C. At high temperatures, atoms are more likely to form island-like films, which increases the surface roughness of the metal film. The roughness at room temperature is less than 50nm. Therefore, by introducing a cooling method for step-by-step sputtering, the surface roughness of TiCu can be improved, thereby achieving defect-free and complete filling after TGV via filling.
[0038] Finally, atomic force microscopy measurements showed that the surface roughness of the Cu seed layer was reduced to below 50 nm after using this process, exhibiting excellent surface smoothness.
[0039] S3. TGV hole filling is performed through electroplating.
[0040] Before the electroplating process in step S3, the glass wafer with the seed layer deposited needs to be placed in a vacuum bath for 2 minutes to wet it. After that, a complete and uniform water film without back-drip phenomenon can be observed on its surface. There is no water film covering the edge of the glass wafer within 2 mm to 10 mm. The smaller the distance of the water film covering the edge of the wafer, the better it indicates that the electroplating solution can uniformly cover most of the wafer surface and the better the wettability. Then, the glass wafer is placed in an acidic copper sulfate electroplating bath for the corresponding electroplating process until the TGV through-hole is completely filled with copper.
[0041] S4. Flatten the TGV vias after filling, remove excess metal, and form TGV interconnects.
[0042] In step S4, a chemical mechanical polishing process is used to grind away excess copper and Ti seed layers on the surface of the glass wafer, making the surface of the glass wafer planar and finally forming independent, flat TGV interconnect holes.
[0043] The following examples illustrate this.
[0044] Example 1
[0045] This embodiment provides a method for forming high-yield TGV interconnect vias, the specific steps of which are as follows:
[0046] S1. A glass wafer is cleaned using a wet cleaning process to remove surface contaminants. The clean glass wafer is then placed on the stage of a UV laser drilling device for laser-induced drilling, which modifies the glass in the target area. The modified glass wafer is then subjected to a wet etching process to form TGV through-holes.
[0047] S2, Deposition of Ti / Cu seed layer:
[0048] Step 1: Deposit a Ti film with a thickness of approximately 500 nm as an adhesion layer;
[0049] The second step involves breaking down the deposition process of a Cu layer with a total thickness of approximately 3 μm into 15 consecutive cyclic steps.
[0050] Sputtering sub-step: In each cycle, the sputtering power of Cu is set to 16kW, the bias power is set to 150W, and the duration of each sputtering sub-step is 25 seconds;
[0051] Cooling sub-step: After each sputtering sub-step is completed, immediately stop all sputtering power supplies and place the glass wafer in the sputtering chamber for cooling. The cooling time lasts for 150 seconds.
[0052] This sputtering cycle of 25 seconds to 150 seconds of cooling is strictly repeated 20 times until the Cu seed layer reaches the predetermined total thickness of 3 μm.
[0053] S3. Remove the wafer with the seed layer deposited from the sputtering chamber and immediately transfer it to a vacuum wetting device for 2 minutes of wetting treatment; then, electroplate the glass wafer until the TGV vias are completely filled with copper and an appropriate amount of plating is formed on the surface.
[0054] S4. Using chemical mechanical polishing, excess copper plating, Cu seed layer and Ti adhesion layer on the surface of the glass wafer are ground away, so that the surface of the glass wafer is re-exposed and achieves nanoscale flatness, and finally a smooth TGV interconnect hole is formed inside the glass wafer.
[0055] Finally, scanning electron microscopy revealed that the internal filling of the TGV interconnect holes was dense, with no voids, gaps or other defects, achieving a 0% void rate.
[0056] Example 2: Comparison of effects under different bias power
[0057] Glass wafer filling tests were conducted on experimental groups A, B, and C. Except for the difference in bias power, the other main process parameters were the same as in Example 1. The bias powers of experimental groups A, B, and C were 100, 200, and 220, respectively.
[0058] Comparative Example 1 used the same glass wafer and TGV vias as Example 1, but adopted a conventional process in the seed layer deposition stage: Ti thickness 500nm, Cu thickness 3μm, Cu sputtering bias power 250W, sputtering was completed in one go without intermediate cooling steps, and the surface roughness of the resulting Cu seed layer was as high as 160nm. After subsequent electroplating to fill the vias, TGV cross-section inspection revealed that more than 10% of the vias contained obvious void defects.
[0059] The relevant performance parameters of the filling methods of experimental groups A, B, C and Comparative Example 1 are shown in the table below. The surface roughness was measured using AFM (Atomic Force Microscopy).
[0060]
[0061] As shown in the table above, within a bias power range of 100W to 200W, the method of this invention can maintain the surface roughness below 80nm. At the same time, there is no water film covering the wafer edge within 2mm to 10mm. The smaller the distance of the water film-free area within the wafer edge, the better the electroplating solution can uniformly cover most of the wafer surface and the better the wettability. This allows the electroplating solution to fully penetrate into the area inside the holes, resulting in a hole filling void rate of less than 3%. The final technical effect is far superior to conventional processes.
[0062] The comparison between experimental group A and experimental group B shows that when the bias power is below 100W, the ion bombardment energy and flux are insufficient, resulting in poor coverage and continuity of the seed layer at the bottom of the TGV via, which in turn affects the filling effect of electroplating.
[0063] Furthermore, comparing experimental groups B and C, an increase in void ratio was observed when the bias power exceeded 200W. This is because as the bias power increases, the roughness also increases, which leads to poor wettability of the electroplating solution, thereby increasing the void ratio. This proves that a bias power of 200W is the better choice.
[0064] Example 3: Comparison of the effects of sputtering and cooling cycles compared to single sputtering
[0065] In this embodiment, experimental groups D and E were added, using the same steps and parameters as in Example 1. The difference lies in the number of sputtering and cooling cycles for experimental groups D and E: 5 and 15, respectively. The performance parameters obtained from the experiments conducted on experimental groups D, E, Example 1, and Comparative Example 1 are compared in the table below:
[0066]
[0067] As shown in the table above, compared with Examples 1, 2, 3 and 4 and Comparative Example 1, with the increase of the number of cycles, the method of the present invention also reduced the surface roughness of the metal to below 50 nm and the void rate of the vias to 0%. This fully demonstrates that the method can effectively reduce roughness, has good wetting effect, and low void rate of the vias. 2. As the number of cycles N increases from 1 to 5 and then to 20, the surface roughness gradually decreases and the void rate of the vias also approaches zero. This proves that when N≥15, the more cycles there are, the lower the void rate of the vias. This proves that step-by-step sputtering and alternating cooling can effectively improve the yield of the product.
[0068] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.
Claims
1. A method for filling TGV through-holes, characterized in that, Includes the following steps: Form TGV vias on the insulating substrate; Seed layers were deposited in the TGV vias by alternating steps of sputtering and cooling. TGV cavity filling is performed using an electroplating process; The filled TGV vias are planarized to remove excess metal and form TGV interconnects.
2. The method for filling TGV through-holes as described in claim 1, characterized in that: The specific steps of the step-by-step sputtering and cooling alternation process are as follows: the seed layer deposition process is divided into N cyclic steps and executed until the seed layer reaches a predetermined total thickness, where N≥15. Each cyclic step includes: a sputtering sub-step, in which a portion of the seed layer is deposited in the TGV via; and a cooling sub-step, in which the temperature of the insulating substrate is reduced after the sputtering sub-step.
3. The method for filling TGV through holes as described in claim 2, characterized in that: The method for reducing the temperature of the insulating substrate after the sputtering sub-step is either static cooling or cooling by introducing cooling gas.
4. The method for filling TGV through holes as described in claim 2, characterized in that: The sputtering sub-steps are performed at least 15 times, and each sputtering sub-step lasts for 20 to 30 seconds.
5. The method for filling TGV through-holes as described in claim 2, characterized in that: The cooling time for each cooling sub-step is 120 to 180 seconds.
6. The method for filling TGV through holes as described in claim 1, characterized in that: During the stepwise sputtering deposition of the seed layer, the applied bias power is maintained at no more than 200W.
7. The method for filling TGV through holes as described in claim 1, characterized in that: Before performing TGV via filling through electroplating, the insulating substrate with the seed layer deposited is placed in a vacuum bath for 2 minutes to wet it. After completion, a water film is covered on the wafer metal film.
8. The method for filling TGV through holes as described in claim 1, characterized in that: The seed layer is a Ti / Cu composite layer.
9. The method for filling TGV through holes as described in claim 1, characterized in that: The thickness of the seed layer is 2-6 μm.