Semiconductor package, method of packaging semiconductor die, and interposer with extended high bandwidth memory offset

Abstract

The invention relates to a semiconductor package, a method of packaging a semiconductor die, and an interposer with extended high bandwidth memory offset. A semiconductor package includes an interposer, a number of first integrated circuit (IC) dies, one or more second IC dies, and one or more dummy dies. The first IC die, the second IC die, and the dummy die are implemented on the interposer. The dummy die is configured to enable a pin of the first IC die to be routed to a selected circuit of the second IC die while conforming to a predefined routing rule.

Description

[0001] Information related to divisional application

[0002] This application is a divisional application of Chinese Patent Application No. 202210166056.9, filed on February 22, 2022, entitled "Semiconductor Packaging, Method for Packaging Semiconductor Dies and Intermediate Layer with Extended High-Bandwidth Memory Offset".

[0003] Cross-references

[0004] This application claims priority to Provisional Application No. 63 / 164,480, filed on March 22, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0005] This description generally relates to Ethernet communication, and more specifically to the extended high-bandwidth memory (HBM) offset in a 2.5D intermediary layer. Background Technology

[0006] Semiconductor integration has evolved to the point where integrated circuit (IC) devices are placed side-by-side on silicon or organic interposers. Interposers typically provide high-density connections between ICs along their facing edges. Unlike 3D interposers, in 2.5D interposers, there is no stacking of dies on the die itself; instead, the dies are packaged on the surface of the silicon interposer. The dies are incorporated into a single package within a single plane and placed on the silicon interposer using flip-chip technology. Typically, ICs used in 2.5D interposers include custom application-specific integrated circuits (ASICs) and high-bandwidth memory (HBM).

[0007] like Figure 1A As shown, one or more HBM devices can be connected to the ASIC along a given edge of the ASIC. Minimum and maximum spacing rules typically exist between dies, and thousands of connections exist between each HBM and its associated ASIC, routed in an interposer layer. A common practice is to place each HBM at the center of the pin of its associated PHY circuitry (e.g., transceiver) within the ASIC. However, this is not always feasible due to IC size mismatches; therefore, the HBM should be offset from the corresponding pin on the ASIC (see [link to documentation]). Figure 1A and 1B ). Summary of the Invention

[0008] In one aspect, this disclosure relates to a semiconductor package comprising: an interposer; a plurality of first integrated circuit (IC) dies; one or more second IC dies; and one or more dummy dies, wherein the plurality of first IC dies, the one or more second IC dies, and the one or more dummy dies are implemented on the interposer, and wherein the one or more dummy dies are configured to enable pins of the plurality of first IC dies to be routed to selected circuitry of the one or more second IC dies while conforming to predefined routing rules.

[0009] In another aspect, this disclosure relates to a method of packaging semiconductor dies, the method comprising: placing a plurality of first integrated circuit (IC) dies on an interposer; placing one or more second IC dies on the interposer; and placing one or more dummy dies on the interposer, wherein placing the one or more dummy dies includes configuring the one or more dummy dies to enable pins of the plurality of first IC dies to be routed to selected circuitry of the one or more second IC dies while conforming to predefined routing rules.

[0010] In a further aspect, this disclosure relates to an intermediary layer having an extended high-bandwidth memory (HBM) offset, the intermediary layer comprising: a plurality of HBM dies; two or more application-specific integrated circuits (ASICs); and one or more dummy dies placed on the intermediary layer, wherein the size and placement of the one or more dummy dies are configured to enable pins of the plurality of HBM dies to be routed to selected circuits of the one or more ASIC dies while conforming to predefined routing rules; and wherein the one or more dummy dies are placed at the configured placement locations on the intermediary layer. Attached Figure Description

[0011] Certain features of the subject matter are set forth in the appended claims. However, for illustrative purposes, several embodiments of the subject matter are illustrated in the following figures.

[0012] Figure 1A and 1B This is a diagram illustrating an example of a semiconductor integration scheme.

[0013] Figure 2 This is a diagram illustrating examples of semiconductor integration schemes based on various aspects of the subject technology.

[0014] Figure 3 This is a diagram illustrating examples of semiconductor integration schemes based on various aspects of the subject technology.

[0015] Figure 4 This is a flowchart illustrating an example of a semiconductor integration method based on some aspects of the subject technology.

[0016] Figure 5 It is an electronic system in which some aspects of the subject technology can be implemented. Detailed Implementation

[0017] The detailed description set forth below is intended as a description of various configurations of the subject matter technology, and not as representing the only configuration in which the subject matter technology can be practiced. The accompanying drawings are incorporated herein and form part of the detailed description, containing specific details for providing a thorough understanding of the subject matter technology. However, the subject matter technology is not limited to the specific details set forth herein, and can be practiced without one or more of the specific details. In some examples, structures and components are shown in the form of block diagrams to avoid obscuring the concepts of the subject matter technology.

[0018] This subject matter relates to methods and systems for providing an integrated circuit with an extended high-bandwidth memory (HBM) offset within a 2.5D interposer. The disclosed solution inserts a dummy die between the application-specific integrated circuit (ASIC) and the HBM to increase the available escape area. This allows for a 45-degree routing to extend the offset from the physical layer (PHY) circuitry of the ASIC to the HBM pins. In inexpensive processes suitable for filling empty areas of the interposer, a metal dummy die can be used to meet design rules. In some implementations, multiple dummy dies can be used. Depending on the application, the dummy dies can be the same or different sizes. Die-to-die spacing rules (e.g., requirements for the spacing between dies) can still be maintained when using this subject matter.

[0019] The subject matter technique includes several advantageous features. For example, increased HBM offset is possible, and the ASIC size does not need to increase for routing to the HBM. Furthermore, the dummy die inserted between the ASIC and HBM increases the escape area, thereby allowing routing to complete. Routing can be 45-degree or orthogonal, and any arbitrary offset is acceptable as long as it does not affect signal integrity. Other routing rules include minimum / maximum metal width, minimum / maximum metal spacing, and metal density (defined as the proportion of metal area to the total available area). The subject matter technique can be used in any semiconductor integration using a 2.5D interposer, and is not limited to integrating HBMs and ASICs.

[0020] Figure 1A and 1BThis diagram illustrates examples of semiconductor integration schemes 100A and 100B. In example semiconductor integration scheme 100A, three HBM dies 110 (110-1, 110-2, and 110-3) are integrated with an ASIC die 120 on interposer 102. Each HBM die 110 has a size of 11 × 11 mm, and the ASIC die 120 has a size of 20 × 20 mm. The HBM dies 110 must be connected to the PHY of the ASIC die 120. The pin connection (routing) from HBM 110-2 to PHY 124 is straightforward because it is centered with its corresponding PHY 124. HBM dies 110-1 and 110-3 require offset because the number of connection routes is large, potentially several thousand (e.g., over 2,000) wires, and they need to be distributed over a finite width W. The magnitude of the offset is geometrically limited and is set by a 45-degree routing rule projected from the HBM. For example, a 45-degree projection can be used to route HBM 110-3 to PHY126. However, HBM die 110-1 cannot be routed in the same way. Figure 1A What is seen is routed. One solution is to increase the size of the ASIC die 120 so that the PHY 122 can correctly route to the pins of the HBM die 110-1 using a 45-degree route. This solution increases chip area and manufacturing cost, and may not even be feasible in some cases, such as when the ASIC reticle (negative mask) area is limited. The subject matter technology addresses the problem discussed in this paper.

[0021] Figure 1B This example demonstrates a semiconductor integration solution 100B, integrating multiple ASIC dies with multiple HBM dies. In this example, ASIC dies 140 and 150 are integrated with HBM dies 130 (130-1, 130-2, 130-3, and 130-4) on one side and HBM dies 160 (160-1, 160-2, 160-3, and 160-4) on the other side. HBM dies 130-2, 130-3, 160-2, and 160-3 are centered with their corresponding PHYs for ASIC dies 140 and 150 and can be correctly routed. However, route 132 for HBM dies 130-1 and 130-4 has similar issues to the routing for HBM dies 160-1 and 160-4, as discussed above. Figure 1A The techniques disclosed in this paper provide solutions for various scenarios without increasing the size of the ASIC, as discussed below.

[0022] Figure 2This is a diagram illustrating an example of a semiconductor integration scheme 200 according to various aspects of the subject matter technology. In the semiconductor integration scheme 200, several first integrated circuit (IC) dies, such as HBM dies 210 (210-1, 210-2, and 210-3), are integrated with second IC dies, such as ASIC dies 250. The HBM dies 210 and ASIC dies 250 are similar to... Figure 1A The HBM die 110 and ASIC die 120 are integrated on the interposer layer 202. An additional feature of the main technology is a virtual die D, which is inserted between the HBM die 210 and the ASIC die 250 on the metal layer of the interposer layer 202.

[0023] Virtual die D increases the available routing area from the ASIC to the HBM, allowing 45-degree routes to extend from the pins of the HBM die 210-1 to the corresponding PHY 252, which would be impossible without Virtual Die D, as mentioned above. Figure 1A The routing from the pins of HBM dies 210-2 and 210-3 to the corresponding PHYs 254 and 256 of the ASIC die 250 is also implemented on its corresponding virtual die D. In some aspects, the virtual die D may be implemented as a single virtual die. In some implementations, the size of the virtual die may vary to maintain die-to-die spacing regularity. In some implementations, the virtual die D may be implemented using a metal such as aluminum, copper, or other suitable materials.

[0024] Figure 3 This is a diagram illustrating an example of a semiconductor integration scheme 300 according to various aspects of the subject matter technology. In the semiconductor integration scheme 300, several first integrated circuit (IC) dies, such as HBM dies 310 (310-1, 310-2, and 310-3) and HBM dies 360 (360-1, 360-2, and 360-3), are integrated with one or more second IC dies, such as ASIC dies 340 and 350. The HBM dies 310 and 360 and the ASIC dies 340 and 350 are similar to... Figure 1B HBM dies 130 and 160 and ASIC dies 140 and 150 are integrated on interposer 302. An additional feature of the subject matter technology is a virtual die D, which is inserted between ASIC dies 340 and 350 on the metal layer of interposer 302.

[0025] The virtual die D increases the ASIC-to-ASIC space, resulting in a sufficient available routing area to allow 45-degree routing from the pins of HBM dies 310-1 and 310-4 to their corresponding PHYs 342 and 352. Similarly, the virtual die D provides a sufficient available routing area to allow 45-degree routing from the pins of HBM dies 360-1 and 360-4 to their corresponding PHYs 344 and 354. In some aspects, the virtual die D may be implemented as a single metal virtual die. In some embodiments, the size of the virtual die D may be varied to maintain die-to-die spacing regularity. In some embodiments, the virtual die D may be implemented using a metal such as aluminum, copper, or other suitable materials.

[0026] As mentioned above Figure 2 and 3 As described in the example implementations, the subject matter technique uses dummy dies at appropriate locations on the intermediary layer to increase the offset between dies (e.g., HBM die to ASIC die). This allows for 45-degree routing of corner dies without increasing the die size, such as that of the ASIC die, which would be impossible without the dummy dies of the subject matter technique. In some implementations, some of the routes may be orthogonal routes instead of 45-degree routes, depending on the geometry of the dies on the intermediary layer. The disclosed technique allows routing using any arbitrary die-to-die offset distance, as long as signal integrity is maintained. Therefore, the disclosed technique enables larger die-to-die (e.g., HBM die to ASIC die) offsets and / or smaller die (e.g., ASIC die) sizes.

[0027] Figure 4 This is a flowchart illustrating an example of a semiconductor integration method 400 according to some aspects of the subject matter technology. The method 400 includes integrating a plurality of first IC dies (e.g., ... Figure 2 210) is placed in the intermediary layer (e.g., Figure 2 (410) on 202). The method also includes placing one or more second IC dies (e.g., Figure 2 The 250) is placed on the intermediate layer (420). The method further includes configuring one or more virtual dies (e.g., ) while conforming to predefined routing rules. Figure 2 (D) The virtual die is placed on the interposer layer so that the pins of the first IC die can be routed to the selected circuitry (430) of the second IC die.

[0028] Figure 5This is an electronic system in which aspects of the subject matter technology can be implemented. Electronic system 500 may be a portable communication device and / or part of a portable communication device, such as a smartphone, smartwatch, tablet, desktop computer, or network switch in a data center or enterprise network. Electronic system 500 may include various types of computer-readable media and interfaces for various other types of computer-readable media. Electronic system 500 includes a bus 508, one or more processing units 512, system memory 504 (and / or buffers), ROM 510, permanent storage device 502, input device interface 514, output device interface 506, and one or more network interfaces 516, or subsets and variations thereof.

[0029] Bus 508 collectively represents all system, peripheral, and chipset buses communicatively connecting multiple internal devices of electronic system 500. In one or more embodiments, bus 508 communicatively connects one or more processing units 512 to ROM 510, system memory 504, and permanent storage device 502. One or more processing units 512 retrieve instructions to be executed and data to be processed from these different memory units in order to perform the processes of this disclosure. In different embodiments, one or more processing units 512 may be a single processor or a multi-core processor. In one or more aspects, one or more processing units 512 may be used to execute instructions to cause Figure 4 Method 4 is executed.

[0030] ROM 510 stores static data and instructions required by one or more processing units 512 and other modules of electronic system 500. On the other hand, permanent storage device 502 can be a read-write memory device. Permanent storage device 502 can be a non-volatile memory cell that stores instructions and data even when electronic system 500 is turned off. In one or more embodiments, a mass storage device (e.g., a magnetic disk or optical disk and its corresponding disk drive) can be used as permanent storage device 502.

[0031] In one or more embodiments, removable storage devices such as floppy disks, flash memory drives, and their corresponding disk drives can be used as permanent storage devices 502. Similar to permanent storage device 502, system memory 504 can be a read-write memory device. However, unlike permanent storage device 502, system memory 504 can be volatile read-write memory, such as random access memory (RAM). System memory 504 can store any of the instructions and data that one or more processing units 512 may need during operation. In one or more embodiments, the processes of this disclosure are stored in system memory 504, permanent storage device 502, and / or ROM 510. One or more processing units 512 retrieve instructions to be executed and data to be processed from these different memory units to perform the processes of one or more embodiments.

[0032] Bus 508 is also connected to input and output device interfaces 514 and 506. Input device interface 514 enables a user to communicate information and select commands to the electronic system 500. Input devices that can be used with input device interface 514 may include, for example, an alphanumeric keypad and a pointer device (also known as a "cursor control device"). For example, output device interface 506 enables the display of images generated by the electronic system 500. Output devices that can be used with output device interface 506 may include, for example, a printer and a display device such as a liquid crystal display, a light-emitting diode display, an organic light-emitting diode display, a flexible display, a flat panel display, a solid-state display, a projector, or any other device for outputting information. One or more embodiments may include a device that serves as both an input and output device, such as a touch screen. In these embodiments, feedback provided to the user may be any form of sensory feedback, such as visual feedback, auditory feedback, or tactile feedback; input from the user may be received in any form, including sound, voice, or tactile input.

[0033] Finally, as Figure 5 As shown, bus 508 also couples electronic system 500 to one or more networks and / or one or more network nodes via one or more network interfaces 516. In this way, electronic system 500 may be part of a computer network (e.g., a local area network or a wide area network), an intranet, or a network (e.g., the Internet) within a network(s). Any or all components of electronic system 500 may be used in conjunction with this disclosure.

[0034] Schemes within the scope of this disclosure may be implemented, in whole or in part, using tangible computer-readable storage media (or multiple tangible computer-readable storage media of one or more types) that encode one or more instructions. The tangible computer-readable storage media may also be non-transitory.

[0035] Computer-readable storage media can be any storage medium that can be read, written, or otherwise accessed by a general-purpose or special-purpose computing device (including any processing electronics and / or processing circuitry capable of executing instructions). For example, without limitation, computer-readable media can contain any volatile semiconductor memory, such as RAM, DRAM, SRAM, T-RAM, Z-RAM, and TTRAM. Computer-readable media can also contain any non-volatile semiconductor memory, such as ROM, PROM, EPROM, EEPROM, NVRAM, flash memory, nvSRAM, FeRAM, FeTRAM, MRAM, PRAM, CBRAM, SONOS, RRAM, NRAM, racetrack memory, FJG, and millipede memory.

[0036] Furthermore, the computer-readable storage medium may comprise any non-semiconductor memory, such as optical disc storage devices, magnetic disk storage devices, magnetic tape, other magnetic storage devices, or any other medium capable of storing one or more instructions. In one or more embodiments, the tangible computer-readable storage medium may be directly coupled to a computing device, while in other embodiments, the tangible computer-readable storage medium may be indirectly coupled to a computing device, for example, via one or more wired connections, one or more wireless connections, or any combination thereof.

[0037] Instructions can be directly executable or used to develop executable instructions. For example, instructions can be implemented as executable or non-executable machine code, or as instructions in a high-level language that can be compiled to produce executable or non-executable machine code. Furthermore, instructions can also be implemented as data or contain data. Computer executable instructions can also be organized in any format, including routines, subroutines, programs, data structures, objects, modules, applications, applets, and functions. As those skilled in the art recognize, the details of the number, structure, sequence, and organization of instructions can vary significantly without altering the basic logic, functionality, processing, and output.

[0038] While the above discussion primarily concerns microprocessors or multi-core processors that execute software, one or more implementations are executed by one or more integrated circuits, such as ASICs or FPGAs. In one or more implementations, such integrated circuits execute instructions stored on the circuit itself.

[0039] Those skilled in the art will understand that the various illustrative blocks, modules, elements, components, methods, and algorithms described herein can be implemented as electronic hardware, computer software, or a combination of both. To illustrate this interchangeability between hardware and software, the various illustrative blocks, modules, elements, components, methods, and algorithms have been generally described above in terms of their functionality. Whether this functionality is implemented as hardware or software depends on the specific application and design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in different ways for each specific application. Various components and blocks can be arranged in different ways (e.g., in different orders or in different ways), all without departing from the scope of the subject matter. Furthermore, the various functional blocks do not need to be directly connected (although they are illustrated in this way in the figures for convenience).

[0040] It should be understood that any particular order or hierarchy of blocks in the disclosed process is a specification of the instance method. Based on design preferences, it should be understood that a particular order or hierarchy of blocks in the process may be rearranged, or all specified blocks may not be executed. Any of the blocks may be executed concurrently. In one or more embodiments, multitasking and parallel processing may be advantageous. Furthermore, the separation of the various system components in the embodiments described above should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0041] As used in this specification and any claim of this application, the terms "base station," "receiver," "computer," "server," "processor," and "memory" refer to electronic or other technical devices. These terms do not include persons or groups of people. For the purposes of this specification, the term "display" means displaying on an electronic device.

[0042] As used herein, the phrase “at least one” following a series of items, using the terms “and” or “or” to separate any of the items, modifies the list as a whole rather than each part of the list (i.e., each item). The phrase “at least one” does not require selection of at least one of every listed items; rather, the phrase allows for the inclusion of at least one of any of the items, and / or at least one of any combination of items, and / or at least one of each of the items. For example, the phrases “at least one of A, B, and C” or “at least one of A, B, or C” each refer only to A, B, or C; any combination of A, B, and C; and / or at least one of each of A, B, and C.

[0043] The predicates “configured to,” “operable to,” and “programmed to” do not imply any specific tangible or intangible modification to the subject, but are intended to be used interchangeably. In one or more embodiments, a processor or component configured to monitor and control operation may also mean a processor programmed to monitor and control operation, or an operable processor to monitor and control operation. Similarly, a processor configured to execute code can be interpreted as a processor programmed to execute code or operable processor to execute code.

[0044] Phrases such as "aspect," "the aspect," "on the other hand," "some aspects," "one or more aspects," "implementation," "the implementation," "another implementation," "some implementations," "one or more implementations," "embodiment," "the embodiment," "another embodiment," "some embodiments," "one or more embodiments," "configuration," "the configuration," "another configuration," "some configurations," "one or more configurations," "subject matter," "the disclosure," and other variations thereof are used for convenience and do not imply that disclosures associated with such phrases are essential to the subject matter or that such disclosures apply to all configurations of the subject matter. Disclosures associated with such phrases may apply to all configurations, or one or more configurations. Disclosures associated with such phrases may provide one or more instances. For example, the phrase "aspect" or "some aspects" may refer to one or more aspects, and vice versa, and this also applies to the other phrases mentioned above.

[0045] The term “exemplary” is used herein to mean “serving as an example, illustration, or description.” Any embodiment described herein as “exemplary” or “example” is not necessarily to be construed as being more preferred or advantageous than other embodiments. Furthermore, with regard to the terms “comprising,” “having,” etc., as used in this description or claims, such terms are intended to be inclusive in a manner similar to the term “including,” since “including” is interpreted as “comprising” when used as a transitional word in a claim.

[0046] All structural and functional equivalents of the elements of the various aspects described in this disclosure that are known or subsequently known to a person skilled in the art are expressly incorporated herein by reference and are intended to be covered by the claims. Furthermore, nothing disclosed herein is intended specifically for public use, whether or not such disclosure is expressly listed in the claims. Pursuant to 35 USC § 112(f), no claim element shall be interpreted unless the element is expressly stated using the phrase “component for…” or, in the case of a method claim, the element is stated using the phrase “step for…”.

[0047] The preceding description is provided to enable those skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Therefore, the claims are not intended to be limited to the aspects presented herein, but should be given the full scope consistent with the language of the claims, wherein elements referred to in the singular are not intended to mean “one and only one,” but rather “one or more,” unless otherwise specifically stated. Unless otherwise specifically stated, the term “some” refers to one or more. A masculine pronoun (e.g., his) includes feminine and neuter pronouns (e.g., her and its), and vice versa. Titles and subtitles (if any) are for convenience only and do not limit this disclosure.

Claims

1. A semiconductor package comprising: an interposer; a plurality of first integrated circuit (IC) dies; one or more second IC dies; and one or more virtual dies, wherein the plurality of first IC dies, the one or more second IC dies, and the one or more virtual dies are implemented on the interposer, and wherein the one or more virtual dies are configured to enable routing of pins of the plurality of first IC dies to selected circuits of the one or more second IC dies while complying with predefined routing rules.

2. The semiconductor package of claim 1, wherein the plurality of first IC dies comprise a plurality of high bandwidth memory (HBM) dies.

3. The semiconductor package of claim 1, wherein the one or more second IC dies comprise one or more application specific integrated circuit (ASIC) dies.

4. The semiconductor package of claim 3, wherein the selected circuits of the one or more second IC dies comprise physical layer (PHY) circuits of the one or more ASIC dies.

5. The semiconductor package of claim 1, wherein the one or more virtual dies are placed between the plurality of first IC dies and the one or more second IC dies.

6. The semiconductor package of claim 1, wherein the one or more virtual dies are placed among the one or more second IC dies.

7. The semiconductor package of claim 6, wherein the one or more virtual dies comprise metal dies implemented in a metal layer of the interposer.

8. The semiconductor package of claim 7, wherein the one or more virtual dies are different in size.

9. The semiconductor package of claim 7, wherein the predefined routing rules comprise 45-degree and orthogonal routing rules.

10. The semiconductor package of claim 1, wherein the one or more virtual dies are configured to enable routing with various offsets between the plurality of first IC dies and the one or more second IC dies.

11. A method of packaging semiconductor dies, the method comprising: placing a plurality of first integrated circuit (IC) dies on an interposer; placing one or more second IC dies on the interposer; and placing one or more virtual dies on the interposer, wherein placing the one or more virtual dies comprises configuring the one or more virtual dies to enable routing of pins of the plurality of first IC dies to selected circuits of the one or more second IC dies while complying with predefined routing rules.

12. The method of claim 11, wherein the plurality of first IC dies comprise a plurality of high bandwidth memory (HBM) dies, and wherein the one or more second IC dies comprise one or more application specific integrated circuit (ASIC) dies.

13. The method of claim 11, wherein placing the one or more virtual dies comprises placing the one or more virtual dies among the one or more second IC dies. ​ ​ 14. The method of claim 11, wherein placing the one or more dummy dies comprises placing the one or more dummy dies between the plurality of first IC dies and the one or more second IC dies.

15. The method of claim 11, wherein placing the one or more dummy dies comprises placing one or more metal dies in a metal layer of the interposer.

16. The method of claim 11, wherein complying with the predefined routing rules comprises complying with 45 degree and orthogonal routing rules.

17. The method of claim 11, further comprising configuring the one or more dummy dies to enable routing with various offsets between the plurality of first IC dies and the one or more second IC dies.

18. An interposer with extended high bandwidth memory (HBM) offset, the interposer comprising: a plurality of HBM dies; two or more application specific integrated circuits (ASICs); and one or more dummy dies placed on the interposer, wherein a size and a placement location of the one or more dummy dies are configured to enable pins of the plurality of HBM dies to be routed to selected circuits of the one or more ASIC dies while complying with predefined routing rules; and wherein the one or more dummy dies are placed at the configured placement location on the interposer.

19. The interposer of claim 18, wherein the configured placement location on the interposer comprises between the two or ASICs, and wherein the placement of the one or more dummy dies comprises placement of one or more metal dies in a metal layer of the interposer.

20. The interposer of claim 18, the configured placement location on the interposer comprises between the plurality of HBM dies and the two or more ASIC dies, and wherein complying with the predefined routing rules comprises complying with 45 degree and orthogonal routing rules. ​

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