Chip packaging method and chip packaging structure
By combining pre-processed copper pillar arrays with packaging technology, the complex process problems in the fabrication of copper pillars for silicon bridge chips have been solved, resulting in improved chip reliability and reduced costs.
Patent Information
- Application Number
- CN202511604910.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-04
- Publication Date
- 2026-02-17
AI Technical Summary
Existing technologies suffer from problems such as poor etching, sputtering film peeling, and copper plating voids during the fabrication of silicon bridge chips, which affect chip performance and reliability, and also result in long preparation cycles and high costs.
The copper pillar array preform is fabricated using a pre-processing method and bonded to the wafer along with the silicon bridge chip. After wafer-level molding, the base is directly ground off to form an independent electrical connection, eliminating complex process steps.
This improved chip reliability, shortened the manufacturing cycle, and reduced manufacturing costs.
Smart Images
Figure CN121548334A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a chip packaging method and a chip packaging structure. BACKGROUND
[0002] With the huge market demand for high-performance, high-bandwidth, and low-power chips, advanced packaging such as 2.5D and 3D integration has gradually been adopted in the fields of high-performance computing, AI, automotive electronics, 5G / 6G communication, etc. to increase product competitiveness. As one of the advanced packaging technologies, silicon bridge technology supports high-frequency, high-bandwidth, and low-latency applications, and has relatively low cost compared to traditional silicon interposers, so it has attracted widespread attention in the industry.
[0003] The silicon bridge chip is made of semiconductor manufacturing process, and the precision of the line width and line spacing of the metal layer trace is very high. In advanced packaging containing a silicon bridge chip, the silicon bridge chip is generally used to connect high-speed signals of two or more chips. These high-speed signal traces benefit from the high-precision line width and line spacing of the silicon bridge chip, avoiding long-distance horizontal winding and cross-layer connection, with shorter trace distance and smaller insertion loss. Generally, the silicon bridge chip is embedded in a substrate or a plastic encapsulation layer, and a copper pillar for connecting the chip and the ball grid array needs to be prepared in the substrate or the plastic encapsulation layer.
[0004] Taking the copper pillar of the plastic encapsulation layer as an example, at present, in the advanced packaging containing the silicon bridge chip, the preparation method of the copper pillar is as follows: TiCu seed layer sputtering is performed on a carrier, photoresist coating, photoetching, Cu pillar electroplating, photoresist removal, and TiCu seed layer etching are performed, and finally the copper pillar for connecting the chip and the ball grid array is obtained.
[0005] In the above process of preparing the copper pillar, due to the complex processes such as etching, PVD (physical vapor deposition) sputtering, and electroplating, problems such as etching failure, sputtering film peeling, and copper electroplating gap are prone to occur, which further affects the performance and reliability of the chip; moreover, the etching, sputtering, and electroplating steps involve many process procedures, and the preparation period is long; and many precision equipment are involved in the preparation process, and the manufacturing cost is high. SUMMARY
[0006] The chip packaging method and the chip packaging structure provided by the present application can improve the reliability of the chip, shorten the preparation period, and reduce the preparation cost.
[0007] In a first aspect, the present application provides a chip packaging method, which comprises: preparing a copper pillar array preform, the copper pillar array preform comprising a copper pillar array and a base connecting each copper pillar in the copper pillar array; bonding the copper pillar array preform and a silicon bridge chip on a first carrier; Carrying out wafer level plastic packaging to obtain a plastic packaging structure; Grinding a first surface of the plastic packaging structure to completely grind off the base of the copper pillar array preform, expose the copper pillars and the bumps of the silicon bridge chip, and make pads connecting the copper pillars and the bumps of the silicon bridge chip; Setting a second carrier on top of the pads connecting the copper pillars and the bumps of the silicon bridge chip, and turning over the wafer to remove the first carrier; Grinding a second surface of the plastic packaging structure until the copper pillars and the through silicon vias of the silicon bridge chip are exposed; Making pads connecting the copper pillars and the through silicon vias of the silicon bridge chip on the second surface of the plastic packaging structure, and making bumps on top of the pads; Setting a third carrier on top of the bumps, and turning over the wafer to remove the second carrier; Soldering a core particle on top of the pads connecting the copper pillars and the bumps of the silicon bridge chip, and filling the bottom of the core particle with underfill glue; De-bonding the third carrier to obtain a chip packaging structure after cutting.
[0008] Optionally, the making of the copper pillar array preform comprises: making the copper pillar array preform by high-precision mechanical processing or 3D powder metallurgy.
[0009] Optionally, the height of each copper pillar in the copper pillar array is slightly higher than the height of the silicon bridge chip.
[0010] Optionally, the ratio of the height to the diameter of each copper pillar in the copper pillar array is less than 3:1.
[0011] Optionally, the base of the copper pillar array preform is a grid structure.
[0012] Optionally, the height of the base of the copper pillar array preform is 100 um.
[0013] Optionally, the making of the pads connecting the copper pillars and the bumps of the silicon bridge chip comprises: directly making the pads connecting the copper pillars and the bumps of the silicon bridge chip on top of the copper pillars and the bumps of the silicon bridge chip; or first making a redistribution layer connecting the copper pillars and the bumps of the silicon bridge chip on top of the copper pillars and the bumps of the silicon bridge chip, and then making the pads connecting the redistribution layer on top of the redistribution layer.
[0014] Optionally, the making of the pads connecting the copper pillars and the through silicon vias of the silicon bridge chip on the second surface of the plastic packaging structure comprises: directly making the pads connecting the copper pillars and the through silicon vias of the silicon bridge chip on the second surface of the plastic packaging structure; or A redistribution layer connecting the copper pillars and the through-silicon via of the silicon bridge chip is formed above the second surface of the plastic package structure, and then a pad connecting the redistribution layer is formed above the redistribution layer.
[0015] Optionally, the pad above the second surface of the plastic package structure is a C4 pad, and the bump above the pad is a C4 bump.
[0016] In a second aspect, the application provides a chip package structure, which comprises a silicon bridge chip and a core particle, the silicon bridge chip is provided with a copper pillar array around, the copper pillar array is formed by a copper pillar array preform; wherein, A pad connecting the copper pillar array and the bump of the silicon bridge chip is arranged above the bump of the silicon bridge chip, and the core particle is welded above the pad connecting the copper pillar array and the bump of the silicon bridge chip, and the bottom of the core particle is filled with a bottom filling glue; A pad connecting the copper pillar array and the through-silicon via of the silicon bridge chip is arranged below the through-silicon via of the silicon bridge chip, and a bump is arranged below the pad connecting the copper pillar array and the through-silicon via of the silicon bridge chip.
[0017] Optionally, the height of each copper pillar in the copper pillar array is slightly higher than the height of the silicon bridge chip.
[0018] Optionally, the ratio of the height to the diameter of each copper pillar in the copper pillar array is less than 3:1.
[0019] The chip package method and the chip package structure provided by the embodiments of the application adopt a pre-processing method to form the copper pillar array, the copper pillar array preform and the silicon bridge chip are pasted on a carrier wafer together in the packaging stage, after wafer-level plastic packaging, the plastic package layer is ground directly until the base connecting the copper pillar array is removed, and each copper pillar forms an independent electrical connection. Compared with the prior art, the application adopts a combination of pre-processed copper pillar array and packaging process, which eliminates the complex process involved in the fabrication of copper pillars in the chip packaging process, reduces the process risk in the fabrication of copper pillars in the chip packaging process, improves the reliability of the chip, shortens the preparation period, and reduces the preparation cost. BRIEF DESCRIPTION OF DRAWINGS
[0020] Figure 1 The flowchart of the chip package method provided by the embodiments of the application is shown in the figure; Figures 2 to 17 The structure diagram corresponding to each step of the chip package method provided by the embodiments of the application is shown in the figure. DETAILED DESCRIPTION
[0021] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present application.
[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application.
[0023] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The devices can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. It will be understood that the terms "comprises" and / or "comprising", or "includes" and / or "including" when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.
[0024] The embodiment of the present application provides a chip packaging method, as shown in the figure, the method comprises: Figure 1 S101, a copper pillar array preform is made, the copper pillar array preform comprises a copper pillar array and a base connecting each copper pillar in the copper pillar array; S102, the copper pillar array preform and a silicon bridge chip are bonded on a first carrier; S103, wafer level plastic packaging is performed to obtain a plastic packaging structure; S104, the first surface of the plastic packaging structure is ground to completely grind off the base of the copper pillar array preform, expose the copper pillar and the bump of the silicon bridge chip, and make a pad connecting the copper pillar and the bump of the silicon bridge chip; Optionally, the pad connecting the copper pillar and the bump of the silicon bridge chip can be made in the following two ways: The pad connecting the copper pillar and the bump of the silicon bridge chip is directly made above the copper pillar and the bump of the silicon bridge chip; or A redistribution layer connecting the copper pillar and the bump of the silicon bridge chip is first made above the copper pillar and the bump of the silicon bridge chip, and then a pad connecting the redistribution layer is made above the redistribution layer.
[0025] S105, a second carrier is arranged above the pad connecting the copper pillar and the bump of the silicon bridge chip, and the wafer is turned over to remove the first carrier; S106, the second surface of the plastic packaging structure is ground until the copper pillar and the through silicon via of the silicon bridge chip are exposed; S107, a pad connecting the copper pillar and the through silicon via of the silicon bridge chip is made above the second surface of the plastic packaging structure, and a bump is made above the pad; Optionally, the pad connecting the copper pillar and the through silicon via of the silicon bridge chip above the second surface of the plastic packaging structure can be made in the following two ways: The pad connecting the copper pillar and the through silicon via of the silicon bridge chip is directly made above the second surface of the plastic packaging structure; or A redistribution layer connecting the copper pillar and the through silicon via of the silicon bridge chip is first made above the second surface of the plastic packaging structure, and then a pad connecting the redistribution layer is made above the redistribution layer.
[0026] S108, a third carrier is arranged above the bump, and the wafer is turned over to remove the second carrier; S109, a core particle is welded above the pad connecting the copper pillar and the bump of the silicon bridge chip, and a bottom filling glue is filled at the bottom of the core particle; S110, the third carrier is debonded, and a chip packaging structure is obtained after cutting.
[0027] The chip packaging method provided by the embodiment of the present application adopts a pre-processing mode to manufacture the copper column array, and the copper column array preform and the silicon bridge chip are pasted on the carrier wafer in the packaging stage. After wafer-level plastic packaging is completed, the plastic packaging layer is ground directly until the base connecting the copper column array is removed, and each copper column forms an independent electrical connection. Compared with the prior art, the present application adopts a combination of pre-processed copper column array and packaging process, which eliminates the complex process involved in the manufacture of copper columns in the chip packaging process, reduces the process risks in the manufacture of copper columns in the chip packaging process, thereby improving the reliability of the chip, shortening the preparation period, and reducing the preparation cost.
[0028] The chip packaging method of the present application will be described in detail below in conjunction with specific embodiments.
[0029] The chip packaging method provided by the embodiment includes the following steps: S201, manufacturing a copper column array preform 10.
[0030] Alternatively, the copper column array preform can be manufactured by high-precision mechanical processing or 3D powder metallurgy, but is not limited thereto. When the copper column array preform is manufactured by 3D powder metallurgy, the simple and large-scale control of grain morphology can be achieved by optimizing the 3D printing powder size, and a part with a precision better than 20 um can be manufactured.
[0031] As shown in Figure 2 The copper column array preform 10 includes a copper column array 11 and a base 12 connecting each copper column in the copper column array 11. The height of the base 12 is about 100 um, and the spacing between each copper column in the copper column array 11 is determined according to the size of the packaged chip. The height of each copper column is slightly higher than the height of the silicon bridge chip, for example. Considering the processing difficulty of the preform, the ratio between the height and the diameter of each copper column is preferably 3:1 or less.
[0032] S202, bonding the prepared copper column array preform 10 and the silicon bridge chip 20 on the first carrier wafer 13 to obtain the structure as shown in Figure 3 .
[0033] Alternatively, the prepared copper column array preform 10 and the silicon bridge chip 20 can be bonded on the first carrier wafer 13 using a die bonding film.
[0034] As shown in Figure 4 , it is a top view of the structure as shown in Figure 3 , wherein the base 12 of the copper column array preform 10 is a grid structure.
[0035] S203, wafer-level plastic packaging is performed so that the plastic packaging material fills the gaps between each copper column in the copper column array 11 to obtain the structure as shown inFigure 5 The plastic package structure is shown in FIG. 2.
[0036] Since the base 12 of the copper pillar array preform 10 is a grid structure, the plastic package material can leak through the grid of the base 12 to the bottom of the base 12, filling the gaps between the copper pillars of the copper pillar array 11.
[0037] S204, grinding the first surface of the plastic package structure, completely grinding off the base 12 of the copper pillar array preform 10, exposing the copper pillar array 11, and exposing the bumps 21 of the silicon bridge chip 20, obtaining a structure as shown in FIG. 3. Figure 6
[0038] The first surface is the upper surface in the structure shown in FIG. 2. Figure 5
[0039] S205, making pads 14 connecting the copper pillars and the bumps 21 of the silicon bridge chip 20 above the first surface of the plastic package structure, obtaining a structure as shown in FIG. 4. Figure 7
[0040] S206, setting a second carrier 15 above the pads 14 connecting the copper pillars and the bumps 21 of the silicon bridge chip 20 in a temporary bonding manner, obtaining a structure as shown in FIG. 5. Figure 8
[0041] S207, flipping the wafer, debonding the first carrier 13, obtaining a structure as shown in FIG. 6. Figure 9
[0042] S208, grinding the second surface of the plastic package structure until the through silicon via 22 of the silicon bridge chip 20 is exposed, obtaining a structure as shown in FIG. 7. Figure 10
[0043] The second surface is the upper surface in the structure shown in FIG. 5. Figure 9
[0044] S209, making C4 pads 16 connecting the copper pillars and the through silicon via 22 of the silicon bridge chip 20 above the second surface of the plastic package structure, obtaining a structure as shown in FIG. 8. Figure 11
[0045] S210, making C4 bumps 17 above the C4 pads 16, obtaining a structure as shown in FIG. 9. Figure 12
[0046] S211, setting a third carrier 18 above the C4 bumps 17, and temporarily bonding, obtaining a structure as shown in FIG. 10. Figure 13
[0047] S212. Flip the wafer, debond it, and remove the second carrier 15 to obtain the following: Figure 14 The structure shown.
[0048] S213. The core chip 31 is soldered above the pad 14 of the bump 21 connecting the copper pillar and the silicon bridge chip 20, to obtain the following: Figure 15 The structure shown.
[0049] S214. Fill the bottom of the core granule 31 with a filler 19 to obtain the following: Figure 16 The structure shown.
[0050] S215. Debond the material, remove the third carrier 18, and cut it to obtain the following: Figure 17 The chip packaging structure shown.
[0051] The chip packaging method provided in this invention employs a pre-fabrication method to create a copper pillar array. During the packaging stage, the copper pillar array prefabricated component is bonded together with the silicon bridge chip onto a carrier. After wafer-level molding, the molding layer is directly ground until the base connecting the copper pillar array is removed, and each copper pillar forms an independent electrical connection. Compared with existing technologies, this invention combines pre-fabricated copper pillar arrays with the packaging process, eliminating the complex processes involved in fabricating copper pillars during chip packaging. This reduces the process risks associated with fabricating copper pillars during chip packaging, thereby improving chip reliability, shortening the manufacturing cycle, and reducing manufacturing costs.
[0052] This invention also provides a chip packaging structure, such as... Figure 17 As shown, the chip packaging structure includes a silicon bridge chip 20 and a die 31. A copper pillar array 11 is disposed around the silicon bridge chip 20, and the copper pillar array 11 is formed by a copper pillar array prefabrication method; wherein, A pad 14 is provided above the bump 21 of the silicon bridge chip 20 to connect the copper pillar array 11 and the silicon bridge chip bump 21. A chip 31 is soldered above the pad 14 connecting the copper pillar array 11 and the silicon bridge chip bump 21. The bottom of the chip 31 is filled with underfill adhesive 19. Below the silicon via 22 of the silicon bridge chip 20, a pad 16 is provided to connect the copper pillar array 11 and the silicon via 22 of the silicon bridge chip. Below the pad 16 connecting the copper pillar array 11 and the silicon via 22 of the silicon bridge chip, a bump 17 is provided.
[0053] Optionally, the height of each copper pillar in the copper pillar array 11 is slightly higher than the height of the silicon bridge chip 20.
[0054] Optionally, the ratio of the height to the diameter of each copper pillar in the copper pillar array 11 is less than 3:1.
[0055] The chip packaging structure provided in this invention uses a copper pillar array for connecting the chip and the ball grid array, which is formed by a copper pillar array prefabrication method. This eliminates the complex process involved in making copper pillars during chip packaging, reduces the process risks involved in making copper pillars during chip packaging, thereby improving chip reliability, shortening the manufacturing cycle, and reducing manufacturing costs.
[0056] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.
Claims
1. A chip packaging method, characterized by, The method comprises: manufacturing a copper pillar array preform, the copper pillar array preform comprising a copper pillar array and a base connecting each copper pillar in the copper pillar array; bonding the copper pillar array preform and a silicon bridge chip on a first carrier; carrying out wafer level molding to obtain a molded structure; grinding a first surface of the molded structure to completely grind away the base of the copper pillar array preform, expose the copper pillars and the bumps of the silicon bridge chip, and manufacture pads connecting the copper pillars and the bumps of the silicon bridge chip; arranging a second carrier above the pads connecting the copper pillars and the bumps of the silicon bridge chip, and turning over the wafer to remove the first carrier; grinding a second surface of the molded structure until the copper pillars and the through silicon vias of the silicon bridge chip are exposed; manufacturing pads connecting the copper pillars and the through silicon vias of the silicon bridge chip above the second surface of the molded structure, and manufacturing bumps above the pads; arranging a third carrier above the bumps, and turning over the wafer to remove the second carrier; soldering a core particle above the pads connecting the copper pillars and the bumps of the silicon bridge chip, and filling the bottom of the core particle with underfill glue; de-bonding the third carrier to obtain a chip packaging structure after cutting.
2. The method of claim 1, wherein, The manufacturing of the copper pillar array preform comprises: manufacturing the copper pillar array preform by high-precision mechanical processing or 3D powder metallurgy.
3. The method according to claim 1 or 2, characterized in that, The height of each copper pillar in the copper pillar array is slightly higher than the height of the silicon bridge chip.
4. The method according to claim 1 or 2, characterized in that, The ratio of the height to the diameter of each copper pillar in the copper pillar array is less than 3:
1.
5. The method according to claim 1 or 2, characterized in that, The base of the copper pillar array preform is a grid structure.
6. The method of claim 1, wherein, The manufacturing of the pads connecting the copper pillars and the bumps of the silicon bridge chip comprises: directly manufacturing the pads connecting the copper pillars and the bumps of the silicon bridge chip above the copper pillars and the bumps of the silicon bridge chip; or first manufacturing a redistribution layer connecting the copper pillars and the bumps of the silicon bridge chip above the copper pillars and the bumps of the silicon bridge chip, and then manufacturing the pads connecting the redistribution layer above the redistribution layer.
7. The method of claim 1, wherein, The manufacturing of the pads connecting the copper pillars and the through silicon vias of the silicon bridge chip above the second surface of the molded structure comprises: directly manufacturing the pads connecting the copper pillars and the through silicon vias of the silicon bridge chip above the second surface of the molded structure; or first manufacturing a redistribution layer connecting the copper pillars and the through silicon vias of the silicon bridge chip above the second surface of the molded structure, and then manufacturing the pads connecting the redistribution layer above the redistribution layer.
8. A chip package structure, characterized by, The chip packaging structure comprises a silicon bridge chip and a core particle, the silicon bridge chip is surrounded by a copper pillar array, and the copper pillar array is formed by a copper pillar array preform; wherein, a pad connecting the copper pillar array and the bumps of the silicon bridge chip is arranged above the bumps of the silicon bridge chip, a core particle is soldered above the pad connecting the copper pillar array and the bumps of the silicon bridge chip, and the bottom of the core particle is filled with underfill glue; a pad connecting the copper pillar array and the through silicon vias of the silicon bridge chip is arranged below the through silicon vias of the silicon bridge chip, and a bump is arranged below the pad connecting the copper pillar array and the through silicon vias of the silicon bridge chip.
9. The chip package structure of claim 8, wherein, The height of each copper pillar in the copper pillar array is slightly higher than the height of the silicon bridge chip.
10. The chip package structure of claim 8, wherein, The ratio of height to diameter of each copper pillar in the array of copper pillars is less than 3:1.