Vehicle-mounted control device

Abstract

Provided is an in-vehicle control device capable of specifying data time efficiency for input data of a time synchronization type application program, enabling the time synchronization type application program to refer to the latest value, and capable of shortening latency. A vehicle-mounted control device (1) is provided with a plurality of computing devices (13) and control units (12, 52) for controlling the plurality of computing devices (13). The control unit (12, 52) controls the plurality of computing devices (13) such that the plurality of computing devices (13) execute a second time-synchronized application having a dependency relationship with the first time-synchronized application during a cycle in which the first time-synchronized application is executed.

Description

Technical Field

[0001] This invention relates to vehicle control devices, and specifically to improving the development efficiency of software in multi-core onboard controllers for automobiles. Background Technology

[0002] Automotive control systems consist of multiple Electronic Control Units (ECUs). Each ECU needs to process sensor inputs, calculate target values ​​for control processing, and control actuators to meet strict time constraints (deadlines). With increasing functionality, multi-core System-on-Chip (SoCs) with multiple high-performance CPUs are being adopted. To reduce costs and save space, there is a trend towards integrating ECUs in closely related functional groups such as autonomous driving, powertrain, and chassis, as well as integrating ECUs in near-front-mounted groups within the vehicle. Furthermore, with further improvements in safety and comfort, functions are becoming increasingly sophisticated, leading to larger-scale and more complex software implementations.

[0003] In automotive control systems, feature additions and load sharing of existing functions occur during development (re-examination of the execution core). These need to be implemented in a way that meets deadlines, but this not only involves ensuring the real-time performance of the object software, but also the potential propagation of effects to software utilizing the computation results due to changes in the execution time of the object software, which could lead to increased design time due to impact analysis.

[0004] In addition, this phenomenon also occurs when updating software after sales, and a solution is hoped for.

[0005] As one solution, the Logical Execution Time (LET) paradigm, a time-synchronized design method, is proposed. LET is a design methodology that fixes the input time of a periodically executed application at the beginning of the LET interval and the output time at the end of the LET interval, thus allowing the application's computation to end between input and output. For example, even when adding functionality to an application running in a new, specific core, it is only necessary to investigate whether the computation of each application running in that core has ended by the output time, without needing to consider the propagation of effects on other applications, thereby reducing design time.

[0006] Therefore, if the scalability to support additional functions is taken into consideration, it is preferable to set the granularity of the application program composed of ECUs to a granularity (group unit) based on load distribution.

[0007] However, if applications are defined in functional units, each application in LET requires one cycle from input to output, which leads to latency degradation.

[0008] According to the technology described in Patent Document 1, when applying a time-synchronization design method to applications with different execution cycles, by preparing multiple buffers (multiple buffers) for exchanging data between applications, and setting the input and output buffers as different entities, exclusive control such as semaphores is not required, thereby eliminating access wait time and improving CPU utilization efficiency.

[0009] Existing technical documents

[0010] Patent documents

[0011] Patent Document 1: Japanese Patent Application Publication No. 2022-14679 Summary of the Invention

[0012] The problem the invention aims to solve

[0013] However, in the technology described in Patent Document 1, since the method of initial input and final output in the cycle remains unchanged, the deterioration of delay, which is the subject of this invention, cannot be resolved.

[0014] The present invention was made to solve the above-mentioned problems, and its purpose is to provide an in-vehicle control device that can specify data age for input data of time-synchronized applications, so that even time-synchronized applications can refer to the latest value and reduce latency.

[0015] Problem-solving methods

[0016] To achieve the above objectives, the present invention is configured as follows.

[0017] The vehicle control device of the present invention includes a plurality of computing devices and a control unit that controls the plurality of computing devices. The control unit controls the plurality of computing devices in such a way that the plurality of computing devices execute a second time-synchronized application that is dependent on the first time-synchronized application during the execution cycle of the first time-synchronized application.

[0018] The effects of the invention

[0019] The present invention provides an in-vehicle control device that can specify the timeliness of input data for time-synchronized applications, so that even time-synchronized applications can refer to the latest values, thereby reducing latency.

[0020] According to the vehicle control device of the present invention, for systems requiring low latency, it is possible to easily add functions or distribute the load of existing applications, thereby improving development efficiency. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the vehicle control device in Embodiment 1.

[0022] Figure 2 This is a functional block diagram of the vehicle control device in Embodiment 1.

[0023] Figure 3 This is a diagram illustrating an example of data flow information in Embodiment 1.

[0024] Figure 4 This is a diagram illustrating an example of software execution information in Embodiment 1.

[0025] Figure 5 This is a diagram illustrating an example of the expected value of data timeliness and data timeliness correction information in Example 1.

[0026] Figure 6A This is a diagram illustrating the execution flow of a time sequence when the present invention is not applicable.

[0027] Figure 6B This is a diagram illustrating the execution flow of a time sequence when the present invention is not applicable.

[0028] Figure 7 This is a diagram illustrating the data access process for data timeliness using multiple buffers in Embodiment 1.

[0029] Figure 8 This is a diagram illustrating the execution flow of the time series in Example 1.

[0030] Figure 9 This is a diagram illustrating an example of the estimated data timeliness value in Example 1.

[0031] Figure 10 This is a diagram illustrating an example of a multi-buffer system in Embodiment 1.

[0032] Figure 11 This is a diagram illustrating an example of the local buffer in Embodiment 1.

[0033] Figure 12 This is a diagram illustrating an example of a buffer index in Embodiment 1.

[0034] Figure 13 This is a diagram illustrating an example of a cyclic counter in Embodiment 1.

[0035] Figure 14 This is a diagram illustrating the processing flow of the data timeliness calculation unit in Embodiment 1.

[0036] Figure 15 This is the processing flow of the data timeliness synchronization correction unit in Example 1.

[0037] Figure 16 This is the processing flow of the application startup section in Embodiment 1.

[0038] Figure 17 This is a diagram illustrating the processing flow of the data timeliness corresponding buffer management unit in Embodiment 1.

[0039] Figure 18 This is a diagram illustrating the processing flow of the data timeliness corresponding buffer reference section in Embodiment 1.

[0040] Figure 19 This is a diagram illustrating the processing flow of the data timeliness corresponding buffer update unit in Embodiment 1.

[0041] Figure 20 This is a diagram illustrating the processing flow of the application unit in Embodiment 1.

[0042] Figure 21 This is a schematic diagram of the vehicle control device in Embodiment 2.

[0043] Figure 22 This is a functional block diagram of the vehicle control device in Embodiment 2.

[0044] Figure 23 This is a diagram illustrating the processing flow of the data timeliness synchronization correction unit in Embodiment 2.

[0045] Figure 24 This is a diagram illustrating an example of software execution information in Embodiment 2.

[0046] Figure 25 This is a diagram illustrating an example of the estimated data timeliness value in Example 2.

[0047] Figure 26 This is a diagram illustrating an example of the expected data timeliness and data timeliness correction information in Example 2.

[0048] Figure 27 This is a diagram illustrating an example of software execution correction information in Embodiment 2.

[0049] Figure 28 This is a diagram illustrating the data access process for data timeliness using multiple buffers in Embodiment 2.

[0050] Figure 29 This is a schematic diagram of the vehicle control device in Embodiment 3.

[0051] Figure 30 This is a functional block diagram of the vehicle control device 3 in Embodiment 3.

[0052] Figure 31 This is a diagram illustrating the processing flow of the data timeliness corresponding buffer reference unit in Implementation Method 3.

[0053] Figure 32 This is a diagram illustrating the processing flow of the data timeliness corresponding buffer update unit in Embodiment 3.

[0054] Figure 33 This is a diagram illustrating the processing flow of the application unit in Embodiment 3.

[0055] Figure 34 This is a schematic diagram of the vehicle control device in Embodiment 4.

[0056] Figure 35 This is a functional block diagram of the vehicle control device in Embodiment 4.

[0057] Figure 36 This is a schematic diagram of the vehicle control device in Embodiment 5.

[0058] Figure 37 This is a functional block diagram of the vehicle control device in Embodiment 5. Detailed Implementation

[0059] The vehicle control device of the present invention estimates the data timeliness of the application group and corrects the data timeliness to make it reach the expected value or not produce jitter. In addition, time-synchronized applications can input data according to a specified data timeliness reference.

[0060] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0061] Example

[0062] <Example 1>

[0063] Figure 1 This diagram illustrates the configuration of the system according to Embodiment 1 of the present invention.

[0064] exist Figure 1 In this embodiment, the vehicle control unit 1 consists of an ECU 12 (control unit) and a development environment 11. The ECU 12 is equipped with multiple CPUs (processors) 13 and a memory 14 for storing programs, sensor input values, calculation results, etc., and is connected to a network 15 for communication with other ECUs, sensors 16, and actuators 17. It is also possible for a single CPU 13 to have multiple cores. Therefore, this invention focuses on an ECU 12 with multiple CPUs 13 or multiple cores.

[0065] Figure 2 This is a functional block diagram illustrating the vehicle control device of Embodiment 1. Figure 2In the development environment 11, the data timeliness calculation unit 113 outputs a data timeliness estimate 114 based on the data flow information 111 and the software execution information 112. Taking the data timeliness estimate 114 as input, the data timeliness synchronization correction unit 115 outputs data timeliness correction information 116 that corrects the jitter in data timeliness.

[0066] In ECU 12, the application startup management unit 121 is executed periodically, periodically updating the loop counter 122. Then, the application 125 is launched based on the software execution information 112. Additionally, the data timeliness corresponding buffer management unit 123 updates the buffer index 124, representing the destination of the multi-buffer 128, according to the loop counter 122. The application 125, via the data timeliness corresponding buffer reference unit 126, refers to the value of the multi-buffer 128 shown in the buffer index 124, copies it to the local buffer 127, and performs calculations. The calculation result is used by the data timeliness corresponding buffer update unit 129 to update the value of the multi-buffer 128 shown in the buffer index 124.

[0067] The data timeliness corresponding buffer reference unit 126 determines the reference destination of the multi-buffer 128 corresponding to the data timeliness based on the buffer index 124.

[0068] Figure 3 This is an example of data stream information from Example 1. Figure 3 In this embodiment, data flow information 111 consists of A1 to A11 of 11 applications 125. Names are assigned to the data flows between applications. For example, data output from A1 and input to A6 is D16. In this embodiment 1, an autonomous driving application is used as the object, but the application of this invention is not limited to this. It can also be applied to powertrain control applications, chassis control applications, and in cases where multiple applications are integrated.

[0069] Figure 4 This is an example of software execution information from Embodiment 1. Software execution information 112 consists of the application's name, content, execution cycle, execution priority, startup information, and the core ID of the executing application. The startup information includes either the "time" at the initial start of the cycle or an "event" that executes after a specific application ends. There may also be events, such as A5, that execute at the end of both applications. The actual state of the application's execution priority is assumed to be the priority of a task, thread, or process. In this invention, the premise is that processing ends within a cycle when each application is executed.

[0070] Figure 5This is an example of the expected value of data timeliness and the data timeliness correction information 116 in Embodiment 1. The expected value of data timeliness and the data timeliness correction information 116 consist of the data name and its corresponding content, as well as the information of the calculated data timeliness.

[0071] Figure 6A and Figure 6B This is the execution flow of the time series when the present invention is not applied. Figure 6A It shows 0ms to 150ms. Figure 6B The time range is shown as 150ms to 400ms.

[0072] When data stream information 111 and software execution information 112 are executed in a time-synchronized application, the latency increases because each application requires one cycle. For example, the critical path that is the main cause of the increased latency is the data flow of A2 or A3, A5, A6, A7, A8, A9, A10, or A11, which takes approximately 400ms from the beginning to the end of data stream information 111. Furthermore, because the cycles of A6 and A7 are different, a phenomenon may occur where data handover cannot occur in the next cycle of A6 (150ms) and cannot occur until the next cycle of A7 (200ms). Figure 6A and 6B As shown, the time (latency) required for all applications to go from input to output is approximately 400ms.

[0073] Figure 7 This describes the data access process that utilizes the multi-buffered data access mechanism of Example 1. Here, as an example, we will focus on the data flow between A6, A7, A9, and A10 of application 125. According to software execution information 112, A6 and A7 operate in CPU 4, and A9 and A10 operate in CPU 6. Applications A6 and A7 have a mutual dependency.

[0074] In this invention, in order to acquire data corresponding to data timeliness, a multi-buffer approach is adopted to manage data according to each data timeliness in the shared data exchanged between applications 125. The method for defining the number of multi-buffers is described later using equation (1).

[0075] According to data stream information 111, input A6 becomes output data D16 of A1 and output data D56 of A5. Figure 5The data timeliness shown represents the expected value, where the data timeliness is 1. A data timeliness of 0 refers to the result calculated within the same period based on the application receiving the object data. A data timeliness of 1 refers to the result calculated in the previous period. In other words, the calculation result of the application executed within the LET Interval of the receiving application has a data timeliness of 0. A data timeliness of N refers to the result calculated in the period N times prior.

[0076] Thus, in this invention, data timeliness is represented by its relative relationship with the receiving application of the object data. That is, it is embodied by relative data timeliness information, which uses a relative relationship to represent the difference in execution time between the applications that generate the data. This enables universal installation.

[0077] Therefore, D16 and D56, which are stored in the shared data (50ms) buffer with a data validity period of 1, are stored in local data buffer 127. Then, this data is used for calculation. The calculation result, D67 and D69, are stored in the shared data (50ms) buffer with a data validity period of 0.

[0078] A7 references data D67 stored in a buffer with a data expiration time of 0 (50ms) in the shared data buffer; A9 references data D69 stored in a buffer with a data expiration time of 1 (50ms) in the shared data buffer; and A10 references data D910 stored in a buffer with a data expiration time of 0 (50ms) in the shared data buffer. In this way, even time-synchronized applications can reference data from buffers with an expiration time of 0, thereby reducing latency.

[0079] The data expiration time needs to be changed on a periodic basis for each application. This is performed by the data expiration corresponding buffer management unit 123 (swap).

[0080] Equation (1) below represents the calculation formula used to determine the number of multiple buffers (multiple buffers for data preparation).

[0081] N buffercounter=MaxDataAge receiver+1・・・(1)

[0082] As shown in equation (1), the number of multiple buffers (N Buffercounter) is the highest number in the request data timeout for the object data plus 1 (MaxDataAge receiver+1). For example, when the request data timeout is 2, the number of multiple buffers is 3.

[0083] The first time-synchronous application is output to multiple buffers 128, and the second time-synchronous application refers to the buffer corresponding to the data timeliness.

[0084] Figure 8 This illustrates the execution flow of the time series in Example 1. Figure 8 In the diagram, dashed arrows between applications represent data communication with a data validity period of 0, while solid arrows represent data communication with a validity period of 1 or more. For example... Figure 8 As shown, the time (latency) required for all applications to go from input to output is approximately 200ms. This is different from not applying... Figure 6A , Figure 6B Compared to the present invention, the time can be greatly shortened.

[0085] Figure 9 This is an example of the estimated data timeliness value 114 in Example 1. Figure 9 In this context, the estimated data timeliness value 114 is composed of the data name, the content corresponding to the data name, and the data timeliness information of the data timeliness calculation unit 113 that stores the results.

[0086] Figure 10 This is an example of the multi-buffer 128 implementation method 1. Figure 10 In this context, the multi-buffer 128 consists of a data name, a buffer index, a data expiration date, and a buffer value.

[0087] Figure 11 This is an example of local buffer 127 in Embodiment 1. Figure 11 In this context, the local buffer 127 consists of a data name and a buffer value.

[0088] Figure 12 This is an example of buffer index 124 in Example 1. Figure 12 In this context, the local buffer 124 consists of a data name and an index.

[0089] Figure 13 This is an example of the loop counter 122 in Embodiment 1. Figure 13 The information from the loop counter 122 is used to construct the system. The loop counter 122 identifies the elapsed time.

[0090] The operation flow of Example 1 will be described in detail below.

[0091] Figure 14 This is the processing flow of the data timeliness calculation unit 113. Based on data flow information and software execution information, the data timeliness calculation unit 113 calculates the data timeliness for at least one piece of data exchanged between applications and outputs it as a data timeliness estimate value 114. The following describes each step.

[0092] ( Figure 14Step 1131)

[0093] The data timeliness calculation unit 113 reads data stream information 111 and software execution information 112.

[0094] ( Figure 14 Step 1132)

[0095] The data timeliness calculation unit 113 determines whether data timeliness has been calculated for each data stream. If there is an uncalculated data stream (true case), the process proceeds to step 1133 to begin calculating the data timeliness of the target data stream; otherwise, the process ends.

[0096] ( Figure 14 Step 1133)

[0097] The data timeliness calculation unit 113 uses software execution information 112 to determine whether the sending-side application and the receiving-side application of the object data stream are running in the same core. If true, proceed to step 1134; if false, proceed to step 113B.

[0098] ( Figure 14 (Step 1134)

[0099] The data timeliness calculation unit 113 uses the software execution information 112 to determine whether the receiving application of the object data stream is executed due to an event trigger. If true, it proceeds to step 1135; if false, it proceeds to step 1136.

[0100] ( Figure 14 Step 1135)

[0101] The data timeliness calculation unit 113 sets the data timeliness value of the object data stream to 0.

[0102] ( Figure 14 Step 1136)

[0103] The data timeliness calculation unit 113 uses software execution information 112 to determine whether the sending application of the object data stream has a higher priority than the receiving application. If true, it proceeds to step 1137; if false, it proceeds to step 1138.

[0104] ( Figure 14 Step 1137)

[0105] The data timeliness calculation unit 113 sets the data timeliness value of the object data stream to 0.

[0106] ( Figure 14 Step 1138)

[0107] The data timeliness calculation unit 113 uses software execution information 112 to determine whether the priorities of the sending application and the receiving application of the object's data stream are equal. If true, it proceeds to step 1139; if false, it proceeds to step 113A.

[0108] ( Figure 14 Step 1139)

[0109] The data timeliness calculation unit 113 sets the data timeliness value of the object data stream to 0-1. The so-called NM value of data timeliness means that jitter is generated in a manner with a minimum value of N and a maximum value of M. For example, a data timeliness of 0-1 means that the data timeliness is sometimes 0 and sometimes 1.

[0110] ( Figure 14 Step 113A)

[0111] The data timeliness calculation unit 113 sets the data timeliness value of the object data stream to 1.

[0112] ( Figure 14 Step 113B)

[0113] The data timeliness calculation unit 113 uses the software execution information 112 to determine whether the receiving application of the object data stream is executed due to an event trigger. If true, proceed to step 113C; if false, proceed to step 113D.

[0114] ( Figure 14 Step 113C)

[0115] The data timeliness calculation unit 113 sets the data timeliness value of the object data stream to 0.

[0116] ( Figure 14 Step 113D)

[0117] The data timeliness calculation unit 113 uses software execution information 112 to determine that no other application is being executed in the core of the application being executed on the receiving side of the object's data stream. If true, proceed to step 113E; if false, proceed to step 113F.

[0118] ( Figure 14 Step 113E)

[0119] The data timeliness calculation unit 113 sets the data timeliness value of the object data stream to 1.

[0120] ( Figure 14 Step 113F)

[0121] The data timeliness calculation unit 113 uses the software execution information 112 to determine whether the receiving application has the highest priority in the core of the receiving application of the execution object data stream. If true, proceed to step 113G; if false, proceed to step 113H.

[0122] ( Figure 14 Step 113G)

[0123] The data timeliness calculation unit 113 sets the data timeliness value of the object data stream to 1.

[0124] ( Figure 14 Step 113H)

[0125] The data timeliness calculation unit 113 uses the software execution information 112 to determine whether all other executed applications in the core of the receiving application of the data stream of the execution object are started by an event from the receiving application. If true, proceed to step 113I; if false, proceed to step 113J.

[0126] ( Figure 14 Step 113I)

[0127] The data timeliness calculation unit 113 sets the data timeliness value of the object data stream to 1.

[0128] ( Figure 14 (Step 113J)

[0129] The data timeliness calculation unit 113 sets the data timeliness value of the object data stream to 0-1.

[0130] Figure 15 This is the processing flow of the data timeliness synchronization correction unit 115. When jitter occurs in the data timeliness of the estimated data timeliness value 114, the data timeliness synchronization correction unit 115 corrects the data timeliness by making the slow or fast value a constant value. The following explains each step.

[0131] ( Figure 15 Step 1151)

[0132] The data timeliness synchronization correction unit 115 reads the estimated data timeliness value 114.

[0133] ( Figure 15 Step 1152)

[0134] The data timeliness synchronization correction unit 115 determines from the data timeliness estimation value 114 whether there is a data stream with data timeliness jitter. If true, proceed to step 1153; if false, proceed to step 1154.

[0135] ( Figure 15 Step 1153)

[0136] The data timeliness synchronization correction unit 115 fixes the data timeliness of a jittery data stream. This fixation can be based on preset content. In this embodiment 1, the data timeliness is set to 1.

[0137] ( Figure 15 Step 1154)

[0138] The data timeliness synchronization correction unit 115 outputs data timeliness correction information 116 based on the estimated data timeliness value 114 and the information related to the data timeliness corrected in this process.

[0139] Figure 16 This is the processing flow of the application startup management department 121. The following is an explanation of each step.

[0140] ( Figure 16 Step 1211)

[0141] The application startup management unit 121 is executed periodically, and the loop counter 122 is incremented (by 1).

[0142] ( Figure 16 Step 1212)

[0143] Application Startup Management 121 reads software execution information 112.

[0144] ( Figure 16 (Steps 1, 2, 1, 3)

[0145] The application startup management unit 121 determines whether there is an application to be launched in the current cycle based on the software execution information 112. For example, it determines whether there is an application that will be launched at a multiple of the minimum cycle among all applications. For example, the minimum cycle in Embodiment 1 is 50ms, so the application startup management unit 121 starts with a 50ms cycle, and the loop counter 122 increments by 1 in 50ms increments. If the application cycle is 100ms, it starts when the loop counter 122 is a multiple of 2. If the determination result is true, it proceeds to step 1214; otherwise, it ends the process flow.

[0146] ( Figure 16 (Steps 1214)

[0147] Application Startup Management Unit 121 starts the application 125 as the object.

[0148] Figure 17 This is the processing flow of the data timeliness response buffer management department 123. The following is an explanation of each step.

[0149] ( Figure 17 Steps 1, 2, 3, and 1)

[0150] The data timeliness corresponding buffer management unit 123 determines whether this is the first execution. If true, it proceeds to step 1232; if false, it proceeds to step 1233.

[0151] ( Figure 17 (Steps 1, 2, 3, 2)

[0152] The data timeliness corresponding buffer management unit 123 sets up multiple buffers 128 according to the data timeliness correction information 116 and the above formula (1).

[0153] ( Figure 17 (Steps 1, 2, 3, 3)

[0154] The data timeliness corresponding buffer management unit 123 determines, based on the loop counter 122, whether there is an application to be executed in the current cycle 125. If true, proceed to step 1234; otherwise, end the processing flow.

[0155] ( Figure 17 (Steps 1, 2, 3, and 4)

[0156] The data validity period corresponding to the buffer management unit 123 switches the data validity period of the multiple buffers 128 for the data output by the started application, according to the loop counter 122, by changing the buffer index of the access destination corresponding to the data validity period. For example, in the multiple buffers 128 set up for a data stream with a maximum data validity period of 2, the buffer index is switched so that the buffer with a data validity period of 0 in the previous cycle is processed as a buffer with a data validity period of 1, the buffer with a data validity period of 1 in the previous cycle is processed as a buffer with a data validity period of 2, and the buffer with a data validity period of 2 in the previous cycle is processed as a buffer with a data validity period of 0. Figure 7 (swap).

[0157] Figure 18 This is the processing flow of the data timeliness corresponding buffer reference unit 126. The following is an explanation of each step.

[0158] ( Figure 18 Step 1261)

[0159] Data timeliness corresponds to the buffer management department 123 reads the buffer index 124.

[0160] ( Figure 18 Step 1262)

[0161] The data timeliness corresponding buffer management unit 123 copies the value of the buffer corresponding to the buffer index 124 to the local buffer 127. At this time, the buffer index 124 represents the reference destination of the data timeliness required by the application 125, so the data value of the desired data timeliness can be referenced.

[0162] Figure 19 This describes the processing flow of the data timeliness corresponding buffer update unit 129. The data timeliness corresponding buffer update unit 129 determines the update destination of the multiple buffers 128 corresponding to the data timeliness based on the buffer index 124. The following explains each step.

[0163] ( Figure 19 Step 1291)

[0164] The data timeliness corresponds to the buffer update section 129, which reads the buffer index 124.

[0165] ( Figure 19 Step 1292)

[0166] The data expiration corresponding buffer update unit 129 copies the output value of application 125 to the buffer corresponding to buffer index 124. Specifically, it uses buffer index 124 to determine the buffer with data expiration of 0 and copies the output value of application 125.

[0167] Figure 20 This is the processing flow of Application Unit 125. The following is an explanation of each step.

[0168] ( Figure 20 Step 1251)

[0169] Application unit 125 uses data timeliness corresponding buffer reference unit 126 to copy the value of multiple buffer 128 to local buffer 127.

[0170] ( Figure 20 Step 1252)

[0171] The application unit 125 uses the input values ​​stored in the local buffer 127 to perform control operations.

[0172] ( Figure 20 Step 1253)

[0173] The application unit 125 uses the data timeliness correspondence buffer update unit 129 to update the value of the multiple buffer 128 according to the result of the control operation.

[0174] ( Figure 20 (Step 1254)

[0175] Application unit 125 publishes events based on software execution information 112. For example, if it is A3, it publishes an event to start A5. A5 starts when the events for A2 and A3 are both available.

[0176] According to this embodiment 1, an in-vehicle control device can be provided. Since multiple CPUs (computing units) 13 are configured to execute a second time-synchronized application that is dependent on the first time-synchronized application during the execution cycle of the first time-synchronized application, the data validity period of the input data of the time-synchronized application can be specified. Even if it is a time-synchronized application, the latest value can be referenced, and the delay can be shortened.

[0177] In addition, according to this embodiment 1, the timeliness of data based on data flow and software execution information can be determined, thereby improving maintainability.

[0178] In addition, according to this embodiment 1, it is possible to detect data streams that jitter during data timeliness, thereby improving maintainability.

[0179] In addition, according to this embodiment 1, the data stream that jitters during data timeliness can be automatically corrected, which can prevent human error and improve design efficiency.

[0180] Furthermore, according to this embodiment 1, by using data access corresponding to data timeliness, data communication within the LET Interval between time-synchronous applications can be performed, thereby shortening the input-to-output delay of the system.

[0181] Furthermore, according to this embodiment 1, since the input and output times between applications are essentially fixed through a multi-buffer swap performed at the beginning of the cycle, even if an application is moved to another core, it is only necessary to verify whether the application ends within a cycle, without needing to perform an impact analysis on other applications, thus improving design efficiency.

[0182] In addition, during the execution cycle of the first time-synchronized application, the CPU (processing unit) 13 that executes the second time-synchronized application that is dependent on the first time-synchronized application can be one CPU 13 or two CPUs 13.

[0183] <Example 2>

[0184] Next, Embodiment 2 of the present invention will be described.

[0185] Example 2 is an example of correcting software execution information to become the expected value when the estimated data timeliness value 114 differs from the expected data timeliness value. The differences from Example 1 will be explained in detail.

[0186] Figure 21 This is a configuration diagram of the vehicle control device 2 in Embodiment 2. The vehicle control device 2 consists of an ECU 22 and a development environment 21.

[0187] Figure 22 This is a functional block diagram of the vehicle control device 2 in Embodiment 2. In Embodiment 2, the data timeliness synchronization correction unit 215 compares the estimated data timeliness value 214 and the expected data timeliness value 217. Under different circumstances, based on the software execution information 212, it updates the software execution information to meet the expected data timeliness value 217 and outputs software execution correction information 218. In addition, the corrected data timeliness is output as data timeliness correction information 216.

[0188] Figure 23 This is the processing flow of the data timeliness synchronization and correction unit 215. The following is an explanation of each step.

[0189] ( Figure 23 Step 2151)

[0190] The data timeliness synchronization correction unit 215 reads the estimated data timeliness value 214, the expected data timeliness value 217, and the software execution information 212.

[0191] ( Figure 23 Step 2152)

[0192] The data timeliness synchronization correction unit 215 compares the estimated data timeliness value 214 and the data timeliness 217 to determine whether there is a data stream with different data timeliness values. If true, it proceeds to step 2153; if false, it proceeds to step 2156.

[0193] ( Figure 23 Step 2153)

[0194] The data timeliness synchronization correction unit 215 determines whether the expected value of the data timeliness of the target data stream is 0. If it is true, it proceeds to step 2154; if it is false, it proceeds to step 2155.

[0195] ( Figure 23 Step 2154)

[0196] The data timeliness synchronization correction unit 215 changes the start condition of the receiving application of the data stream to an event and corrects the data timeliness value of the corresponding data stream to 0.

[0197] ( Figure 23 Step 2155)

[0198] The data timeliness synchronization correction unit 215 changes the startup condition of the receiving application of the data stream to time, and corrects the data timeliness value of the corresponding data stream to the expected value.

[0199] ( Figure 23 Step 2156)

[0200] The data timeliness synchronization correction unit 215 outputs the corrected startup conditions in this process as software execution correction information based on the software execution information 212.

[0201] ( Figure 23 Step 2157)

[0202] The data timeliness synchronization correction unit 215 outputs the data timeliness value corrected in this process based on the estimated data timeliness value 214 as software execution correction information.

[0203] Figure 24 This is an example of software execution information 212 in Embodiment 2.

[0204] Figure 25 This is an example of the estimated data timeliness value 214 in Example 2.

[0205] Figure 26 This is an example of the expected data timeliness value 217 and the data timeliness correction information 216 in Embodiment 2.

[0206] Figure 27 This is an example of software execution correction information 218 in Embodiment 2.

[0207] Figure 28 This is Example 2, which utilizes the data access process corresponding to data timeliness with multiple buffers.

[0208] According to this embodiment 2, in addition to achieving the same effect as in embodiment 1, when the estimated data timeliness value and the expected data timeliness value are inconsistent, the software execution information is automatically corrected to become the expected value, thus improving the design efficiency.

[0209] <Example 3>

[0210] Next, Embodiment 3 of the present invention will be described.

[0211] The example is based on Example 2, where the application explicitly specifies data expiration time. The differences from Examples 1 and 2 are explained in detail.

[0212] In Embodiment 2, the data timeliness corresponding buffer management unit 123 identifies the data timeliness of the data that the application wants to reference based on the data timeliness estimation value 214 or the data timeliness correction information 216, and updates the buffer index 124 of the multi-buffer in such a way as to become the buffer of the data timeliness expectation value 217. At least the second time synchronization type application uses the data timeliness corresponding buffer reference unit 326 to refer to the buffer of data timeliness.

[0213] In addition, the data timeliness corresponding buffer management unit 123 uses the data timeliness corresponding buffer reference unit 326 to specify the data timeliness by the first time synchronization application or the second time synchronization application.

[0214] Figure 29 This is a configuration diagram of the vehicle control device 3 in Embodiment 3. The vehicle control device 3 consists of an ECU 32 and a development environment 31.

[0215] Figure 30 This is a functional block diagram of the vehicle control device 3 in Embodiment 3. Figure 30 In the process, application 325 explicitly specifies the data validity period and accesses the multiple buffer 128 through the data validity period corresponding buffer reference unit 326 and the data validity period corresponding buffer update unit 329.

[0216] Figure 31 This is the processing flow of the data timeliness corresponding buffer reference unit 326. The following is an explanation of each step.

[0217] ( Figure 31 Step 3261)

[0218] The data timeliness corresponds to the buffer reference section 326, which reads the buffer index 124.

[0219] ( Figure 31 Step 3262)

[0220] The specified data validity period is read as a parameter from the data validity period corresponding to the buffer reference unit 326.

[0221] ( Figure 31 Step 3263)

[0222] The data validity period corresponding buffer reference unit 326 reads (copies) the value of the buffer corresponding to the buffer index 124 and the specified data validity period to the local buffer 127.

[0223] Figure 32 This is the processing flow of the data timeliness corresponding buffer update unit 329. The following is an explanation of each step.

[0224] ( Figure 32 Step 3291)

[0225] The data timeliness corresponds to the buffer update section 329, which reads buffer index 124.

[0226] ( Figure 32 Step 3292)

[0227] The specified data validity period is read as a parameter by the data validity period corresponding to the buffer update unit 329.

[0228] ( Figure 32 Step 3293)

[0229] The data timeliness corresponding buffer update unit 329 copies the output value to the buffer corresponding to the buffer index 124 and the specified data timeliness.

[0230] Figure 33 This is the processing flow of Application Unit 325. The following is an explanation of each step.

[0231] ( Figure 33 Step 3251)

[0232] Application unit 325 specifies data validity period, and uses data validity period corresponding buffer reference unit 326 to copy the value of multiple buffers to local buffer 127.

[0233] ( Figure 33 Step 3252)

[0234] Application unit 325 uses the input value of local buffer 127 to perform control operations.

[0235] ( Figure 33 Step 3253)

[0236] Application unit 325 specifies data expiration time, and data expiration time corresponding buffer update unit 329 updates the value of multiple buffers using the result of control operation.

[0237] ( Figure 33 Step 3254)

[0238] Application Section 325 publishes events based on software execution information.

[0239] According to this embodiment 3, in addition to achieving the same effect as in embodiment 1, since the reference and update of multiple buffers can be performed from the data timeliness specified by the application, the data timeliness corresponding buffer reference unit and data timeliness corresponding buffer update unit corresponding to each data timeliness are no longer needed, and the installation efficiency can be expected to be improved and the memory consumption reduced.

[0240] <Example 4>

[0241] Next, Embodiment 4 of the present invention will be described.

[0242] Example 4 is an example of integrating the development environment into the ECU based on Example 1. It focuses on explaining the differences from Examples 1, 2, and 3.

[0243] Figure 34 This is a configuration diagram of the vehicle control device 4 in Embodiment 4. The vehicle control device 4 is composed of an ECU 42.

[0244] Figure 35 This is a functional block diagram of the vehicle control device in Embodiment 4.

[0245] According to this embodiment 4, in addition to achieving the same effects as in embodiment 1, since the development environment is integrated into the ECU 42, when additional functions are added to the vehicle control device 4 after the sale, each ECU can automatically implement design modifications for the additional application, thus improving design efficiency.

[0246] <Example 5>

[0247] Next, Embodiment 5 of the present invention will be described.

[0248] Example 5 is an example of integrating the development environment into the ECU based on Example 2. It focuses on explaining the differences from implementation methods 1, 2, 3, and 4.

[0249] Figure 36 This is a configuration diagram of the vehicle control device 5 according to embodiment 5. The vehicle control device 5 is composed of an ECU 52 (control unit).

[0250] Figure 37 This is a functional block diagram of the vehicle control device 5 in embodiment 5.

[0251] According to this embodiment 5, in addition to achieving the same effect as in this instruction embodiment 1, since the development environment is integrated into the ECU 52, when additional functions are added to the vehicle control device 5 after the sale, each ECU can automatically implement design modifications for the additional application according to the expected value, thus improving design efficiency.

[0252] Symbol Explanation

[0253] 1, 2, 3, 4, 5… Vehicle control unit, 11… Development environment, 12, 52… ECU (Control Unit), 13… CPU (Computing Unit), 14… Memory, 15… Network, 16… Sensor, 17… Actuator, 42, 52… ECU, 111… Data stream information, 112… Software execution information, 113… Data timeliness calculation unit, 114, 214… Estimated data timeliness value, 115, 215… Data timeliness synchronization correction unit, 116, 216… Data timeliness correction information, 121… Application startup management Section, 122…Cycle Counter, 123…Data Timeliness Corresponding Buffer Management Section, 124…Buffer Index, 125, 325…Application Section, 126, 326…Data Timeliness Corresponding Buffer Reference Section, 127…Local Buffer, 128…Multiple Buffers, 129, 329…Data Timeliness Corresponding Buffer Update Section, 212…Software Execution Information, 214…Data Timeliness Estimated Value, 216…Data Timeliness Estimated Information, 217…Data Timeliness Expected Value, 218…Software Execution Correction Information, A1~A11…Application Program.

Claims

1. An in-vehicle control device, comprising: a plurality of arithmetic devices; and a control section that controls the plurality of arithmetic devices, the control section controlling the plurality of arithmetic devices in a manner that the plurality of arithmetic devices execute a second time-synchronous type application program having a dependency relationship with a first time-synchronous type application program within a period in which the first time-synchronous type application program is executed.

2. The in-vehicle control device according to claim 1, characterized in that, a plurality of buffers having at least one buffer defined in accordance with a data age of data to be managed is provided, the first time-synchronous type application program is output to the plurality of buffers, and the second time-synchronous type application program refers to the buffer corresponding to the data age.

3. The in-vehicle control device according to claim 2, characterized by comprising: a cycle counter that identifies the passage of time; an application start management section that periodically updates the cycle counter; a data age corresponding buffer management section that updates a buffer index indicating an access destination of the plurality of buffers corresponding to the data age based on the cycle counter; a data age corresponding buffer reference section that determines a reference destination of the plurality of buffers corresponding to the data age based on the buffer index; and a data age corresponding buffer update section that determines an update destination of the plurality of buffers corresponding to the data age based on the buffer index.

4. The in-vehicle control device according to claim 2, characterized by comprising: a data age calculation section that calculates the data age for at least one or more data exchanged between application programs based on data flow information and software execution information, and outputs as a data age estimation value; and a data age synchronization correction section that corrects the data age in a manner that the data age becomes a constant value at a slow or fast value in the case where jitter occurs in the data age of the data age estimation value.

5. The in-vehicle control device according to claim 2, characterized by comprising: a data age calculation section that calculates the data age for at least one or more data exchanged between application programs based on data flow information and software execution information, and outputs as a data age estimation value; and a data age synchronization correction section that compares the data age estimation value and a data age expectation value, updates software execution information in a manner that satisfies the data age expectation value, and outputs data age correction information and software execution correction information.

6. The in-vehicle control device according to claim 3, characterized in that, the data age corresponding buffer management section identifies the data age of data that an application program wants to refer to based on a data age estimation value or data age correction information, and updates the buffer index of the plurality of buffers in a manner that the buffer becomes a data age expectation value, and at least the second time-synchronous type application program refers to the buffer of the data age using the data age corresponding buffer reference section.

7. The in-vehicle control device according to claim 3 or 6, characterized in that, in the data age corresponding buffer management section, the first time-synchronous type application program or the second time-synchronous type application program specifies a data age to use the data age corresponding buffer reference section.

8. The in-vehicle control device according to claim 2, characterized by the data age is expressed with relative data age information that expresses a difference in execution time between the application programs that generate the reference relationship of the data with a relative relationship.

Images