Ultrasonic chip and ultrasonic module

Abstract

The present specification relates to the technical field of semiconductor technology, and particularly relates to an ultrasonic chip and an ultrasonic module. The ultrasonic chip comprises a circuit layer, a piezoelectric layer and an electrode layer; the circuit layer comprises a substrate, an in-chip circuit of an ultrasonic transmitting circuit is arranged in the substrate, a first pad, a second pad and a first electrode are arranged on the substrate, the electrode layer comprises a second electrode; the first electrode, the second electrode and the piezoelectric layer are used to form an ultrasonic transducer; the in-chip circuit is used to generate an electrical signal and transmit the electrical signal to the first pad, the first pad is used to transmit the electrical signal to an out-chip circuit of the ultrasonic transmitting circuit, the out-chip circuit is used to generate an excitation signal according to the electrical signal and transmit the excitation signal to the second pad, the second pad is used to transmit the excitation signal to the second electrode, so as to drive the ultrasonic transducer to transmit ultrasonic waves, and the in-chip circuit is located in a region outside an ultrasonic region. The embodiment of the present specification can improve the integration of the ultrasonic chip.

Description

Technical Field

[0001] This specification relates to the field of semiconductor technology, and in particular to an ultrasonic chip and an ultrasonic module. Background Technology

[0002] An ultrasonic transmitting circuit drives an ultrasonic transducer to emit ultrasonic waves. When these waves encounter an object being detected (such as a fingerprint), they are reflected, forming an echo. An ultrasonic receiving circuit (also known as an ultrasonic recovery circuit) receives the reflected echo through the ultrasonic transducer. Ultrasonic wave emission requires high-voltage excitation. To reduce the impact of high voltage on the ultrasonic transducer's echo reception, related technologies typically deploy the ultrasonic transducer on one chip (e.g., an ultrasonic chip) and the ultrasonic transmitting circuit on another chip (e.g., a transmitting chip or a driving chip).

[0003] Deploying the ultrasonic transmitting circuit and ultrasonic transducer on different chips reduces chip integration. The chips require a large number of electrical interconnections, which increases the size and assembly cost of the ultrasonic module and reduces its reliability. Summary of the Invention

[0004] This specification provides an ultrasonic chip and an ultrasonic module to improve the integration of the ultrasonic chip.

[0005] This specification provides an example of an ultrasonic chip, including a circuit layer, a piezoelectric layer, and an electrode layer;

[0006] The circuit layer includes a substrate, an on-chip circuit of an ultrasonic transmitting circuit is provided in the substrate, a first pad, a second pad and a first electrode are provided on the substrate, and the electrode layer includes a second electrode.

[0007] The first pad connects to the on-chip circuit, the second pad connects to the second electrode, and the first electrode, the second electrode, and the piezoelectric layer are used to form an ultrasonic transducer.

[0008] The on-chip circuitry is used to generate electrical signals and transmit the electrical signals to the first pad. The first pad is used to transmit the electrical signals to the off-chip circuitry of the ultrasonic transmitting circuit. The off-chip circuitry is used to generate excitation signals based on the electrical signals and transmit the excitation signals to the second pad. The second pad is used to transmit the excitation signals to the second electrode to drive the ultrasonic transducer to emit ultrasonic waves.

[0009] At least a portion of the on-chip circuitry is located outside the ultrasonic region of the circuit layer, the ultrasonic region including the substrate surface region where the first electrode is located and the substrate interior region below the surface region.

[0010] This specification provides an ultrasonic module, including an ultrasonic chip and an off-chip circuit for the ultrasonic transmitting circuit.

[0011] The technical solution of the embodiments in this specification includes an ultrasonic transmitting circuit comprising on-chip circuitry and off-chip circuitry. An on-chip circuit and an ultrasonic transducer are disposed on the ultrasonic chip. Therefore, by placing the on-chip circuitry and the ultrasonic transducer on the same ultrasonic chip, the integration density of the ultrasonic chip can be improved. Compared to the numerous electrical interconnections between chips in related technologies, the number of electrical interconnections required between the off-chip circuitry and the ultrasonic chip is significantly reduced, thereby reducing the size and assembly cost of the ultrasonic module, while improving the reliability of the ultrasonic module. Furthermore, the ultrasonic chip includes a circuit layer, a piezoelectric layer, and an electrode layer. The circuit layer includes a substrate. On-chip circuitry is disposed within the substrate, and a first pad, a second pad, and a first electrode are disposed on the substrate. The first pad connects to the on-chip circuitry. The second pad connects to the second electrode. The first electrode, the second electrode, and the piezoelectric layer are used to form the ultrasonic transducer. The on-chip circuitry can generate electrical signals and transmit them to the first pad. The first pad can transmit the electrical signals to the off-chip circuitry. The off-chip circuitry can generate excitation signals based on the electrical signals and transmit them to the second pad. The second pad can transmit the excitation signals to the second electrode. Therefore, the ultrasonic chip can work in conjunction with off-chip circuitry to emit ultrasonic waves. Furthermore, at least a portion of the on-chip circuitry is located in the non-ultrasonic region of the circuit layer within the ultrasonic chip. This reduces the impact of the on-chip circuitry and its generated electrical signals on the ultrasonic transducer, improving the sensitivity and signal-to-noise ratio of ultrasonic detection. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments or prior art of this specification, the drawings used in the description of the embodiments or prior art will be briefly introduced below. The drawings described below are only some embodiments recorded in this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a schematic diagram of the functional structure of electronic devices in related technologies;

[0014] Figure 2 This is a functional structure diagram of the electronic device in the embodiments of this specification;

[0015] Figure 3 This is a functional structure diagram of the ultrasonic transmitting circuit in the embodiments of this specification;

[0016] Figure 4 This is a functional structure diagram of the non-overlapping circuit in the embodiments of this specification;

[0017] Figure 5 This is a functional structure diagram of the driving circuit in the embodiments of this specification;

[0018] Figure 6 This is a functional structure diagram of the equivalent circuit of the boost circuit and transducer in the embodiments of this specification;

[0019] Figure 7 This is a functional structure diagram of the ultrasonic chip in the embodiments of this specification;

[0020] Figure 8 This is a functional structure diagram of the ultrasonic chip in the embodiments of this specification;

[0021] Figure 9 This is a functional structure diagram of the ultrasonic chip in the embodiments of this specification;

[0022] Figure 10 This is a schematic diagram of the functional structure of the ultrasound region in the embodiments of this specification;

[0023] Figure 11 This is a top view of the ultrasonic chip in the embodiments of this specification;

[0024] Figure 12 This is a functional structural diagram of the ultrasonic transmitting circuit in the embodiments of this specification.

[0025] The following are the reference numerals used in the embodiments of this specification:

[0026] 100. Ultrasonic transmitting circuit; 100-1. On-chip circuit; 100-2. Off-chip circuit; 200. Transducer; 300. Ultrasonic receiving circuit; 400. Analog-to-digital conversion circuit; 500. Ultrasonic chip;

[0027] 101. Control circuit; 102. Signal generation circuit; 103. Boost circuit;

[0028] 1011. Sequential circuit; 1012. Driver circuit;

[0029] 10111, Inverter; 10112, Buffer; 10113, NOR gate; 10114, NOR gate; 10115, Delay circuit; 10117, Buffer; 10118, Buffer; 10121, Switch; 10122, Switch;

[0030] 201, First inductor; 202, First capacitor; 203, Second inductor; 204, Resistor; 301, Second capacitor;

[0031] 501. Circuit layer; 502. Piezoelectric layer; 503. Electrode layer; 504. Protective layer;

[0032] 5011, Substrate; 5012, First Electrode; 5013, Second Pad; 5014, First Pad; 5015, Ultrasonic Region; 5016, Metal Trajectory Layer; 5017, P-type Doped Substrate. Detailed Implementation

[0033] The technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this specification, and not all embodiments. The specific embodiments described herein are only used to explain this disclosure, and not to limit this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure are within the scope of protection of this disclosure. In addition, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0034] Electronic devices (such as smartphones) include ultrasonic modules. Ultrasonic modules achieve ultrasonic detection by emitting ultrasonic waves and receiving their echoes. An ultrasonic module may include an ultrasonic transmitting circuit, an ultrasonic receiving circuit, and an ultrasonic transducer. In related technologies, the ultrasonic receiving circuit and ultrasonic transducer are typically deployed on one chip (e.g., an ultrasonic chip), while the ultrasonic transmitting circuit is deployed on another chip (e.g., a transmitting chip or a driver chip). However, deploying the ultrasonic transmitting circuit and ultrasonic transducer on different chips reduces chip integration. The need for numerous electrical interconnects between chips increases the size and assembly cost of the ultrasonic module, and reduces its reliability. This hinders the miniaturization and reliability improvement of electronic devices.

[0035] For example, please see Figure 1 In related technologies, electronic devices may include an ultrasonic module and a processor. The ultrasonic module and the processor are electrically connected via a printed circuit board (e.g., a flexible printed circuit board). The ultrasonic module includes an ultrasonic chip and a transmitting chip. The ultrasonic chip includes an ultrasonic receiving circuit and an ultrasonic transducer. The transmitting chip includes an ultrasonic transmitting circuit. The ultrasonic chip and the transmitting chip are connected via a printed circuit board (e.g., a flexible printed circuit board). Both the ultrasonic chip and the transmitting chip require a significant amount of space, increasing the size of the ultrasonic module. Furthermore, the printed circuit board needs to support numerous electrical interconnections between the ultrasonic chip and the transmitting chip, increasing the area and number of layers of the printed circuit board. Additionally, the large number of electrical interconnections increases the assembly cost of the ultrasonic module and also increases the probability of signal interference.

[0036] This specification provides an ultrasonic chip. The ultrasonic chip includes on-chip circuitry for an ultrasonic transmitting circuit and an ultrasonic transducer. By centrally deploying the on-chip circuitry for the ultrasonic transmitting circuit and the ultrasonic transducer on the same ultrasonic chip, the integration density of the ultrasonic chip can be improved. For example, please refer to... Figure 2 Electronic devices may include ultrasonic modules and processors. The ultrasonic module and processor are electrically connected via a printed circuit board (e.g., a flexible printed circuit board). The ultrasonic module includes an ultrasonic chip and off-chip circuitry for the ultrasonic transmitting circuit. The ultrasonic chip and off-chip circuitry can be electrically connected via a printed circuit board (e.g., a flexible printed circuit board). The ultrasonic chip includes on-chip circuitry for the ultrasonic transmitting circuit, an ultrasonic receiving circuit, and an ultrasonic transducer. By eliminating the need for a large transmitting chip within the ultrasonic module, the size of the ultrasonic module is reduced. Furthermore, the number of electrical interconnections carried by the printed circuit board between the ultrasonic chip and the off-chip circuitry is reduced, allowing for a decrease in the area and number of layers of the printed circuit board. Additionally, by reducing the number of electrical interconnections between the ultrasonic chip and the off-chip circuitry, the assembly cost of the ultrasonic module is reduced, and the probability of signal interference is decreased.

[0037] Figure 3 These are schematic diagrams of the ultrasonic transmitting circuits in some embodiments of this specification. For example... Figure 3 As shown, the ultrasonic transmitting circuit 100 is electrically connected to the transducer 200 (also known as an ultrasonic transducer). The ultrasonic transmitting circuit 100 generates an excitation signal and transmits the excitation signal to the transducer 200. The transducer 200 emits ultrasonic waves under the action of the excitation signal.

[0038] In some embodiments, the ultrasonic transmitting circuit 100 may include a control circuit 101, a signal generation circuit 102, and a boost circuit 103. The control circuit 101 is connected to the signal generation circuit 102. The signal generation circuit 102 is connected to the boost circuit 103. The control circuit 101 can generate a control signal and transmit it to the signal generation circuit 102. The signal generation circuit 102 can generate a drive signal based on the control signal and transmit the drive signal to the boost circuit 103. The boost circuit 103 can generate an excitation signal based on the drive signal and transmit the excitation signal to the transducer 200.

[0039] In some embodiments, the control circuit 101 is used to generate control signals. The waveform of the control signal can be a square wave, a triangle wave, a sine wave, etc. The control signal can be a periodic timing control signal used to control the operating timing of the signal generation circuit 102. For example, the control signal is used to control the operating state of the components in the signal generation circuit 102 (e.g., controlling the on and off states of a switch). The control circuit 101 can generate one or more control signals, so that the signal generation circuit 102 can generate one or more drive signals based on the one or more control signals generated by the control circuit 101.

[0040] In some embodiments, the control circuit 101 may include a timing circuit 1011 and a driving circuit 1012. The timing circuit 1011 is connected to the driving circuit 1012. The driving circuit 1012 is connected to the signal generation circuit 102. The timing circuit 1011 can generate timing signals. The waveform of the timing signals can be a square wave, a triangle wave, a sine wave, etc. The driving circuit 1012 can amplify the timing signals to obtain control signals, thereby improving the load driving capability.

[0041] As an example, timing circuit 1011 can generate a timing signal. Control circuit 101 may include a drive circuit 1012. The drive circuit 1012 can amplify the timing signal to obtain a control signal. As another example, timing circuit 1011 can generate multiple timing signals. Control circuit 101 may include multiple drive circuits 1012. Multiple drive circuits 1012 can generate multiple control signals. Each drive circuit 1012 can amplify a timing signal to obtain a control signal. The number of multiple control signals can be 2, 3, or 4, etc. The multiple control signals have the same waveform, amplitude, frequency, etc., but different phases. The multiple control signals do not overlap, thus complementing each other and having a delay time (also known as non-overlapping time). For example, the voltage amplitude of each control signal switches between positive and negative values. The moments when the voltage amplitude of the multiple control signals is 0 can be separated by non-overlapping time intervals. The non-overlapping time provides a safe buffer period for the switching of operating states of components in the signal generation circuit 102 (such as the switching between the on and off states of a switch), ensuring that the switching is thorough and risk-free. This improves the safety of the signal generation circuit 102.

[0042] The sequential circuit 1011 can be implemented based on logic gates, or based on flip-flops (e.g., D flip-flops), or based on a microcontroller. For example, the sequential circuit 1011 can be a non-overlapping circuit, which can generate multiple (e.g., two) non-overlapping sequential signals. Figure 4This is a schematic diagram of the non-overlapping circuit structure in some embodiments of this specification. The non-overlapping circuit may include an inverter 10111, a buffer 10112, a NOR gate 10113, a NOR gate 10114, a delay circuit 10115, a delay circuit 10116, a buffer 10117, and a buffer 10118. The clock signal CLK is inverted by the inverter 10111 to obtain the signal... The clock signal CLK is buffered by buffer 10112 to obtain the signal. The output signal of NOR gate 10113 is The output signal of the NOR gate 10114 is... Signal C, after passing through delay circuit 10115, yields signal E. Delay circuit 10115 is formed by cascading multiple buffers. Signal E, after passing through buffer 10117, yields signal PHI1. Signal D, after passing through delay circuit 10116, yields signal F. Delay circuit 10116 is formed by cascading multiple buffers. Signal F, after passing through buffer 10118, yields signal PHI1. Thus, through the cross-feedback of NOR gates 10113 and 10114, complementarity between signals PHI1 and PHI2 can be achieved, and through the delays of delay circuits 10115 and 10116, non-overlapping between signals PHI1 and PHI2 can be achieved.

[0043] The timing signal generated by the timing circuit 1011 has a relatively small current, making it difficult to directly drive the components in the signal generation circuit 102. Therefore, the timing signal generated by the timing circuit 1011 can be transmitted to the drive circuit 1012. The drive circuit 1012 can amplify the timing signal (e.g., amplify the current of the timing signal), thereby improving the load driving capability. The drive circuit 1012 can be implemented based on discrete components (such as switching transistors), or it can be implemented based on an application-specific integrated circuit (ASIC) or a microcontroller. Figure 5 These are schematic diagrams of the drive circuits in some embodiments of this specification. For example... Figure 5 As shown, the driver circuit 1012 includes switching transistors 10121 and 10122. Switching transistor 10121 is an NPN transistor. Switching transistor 10122 is a PNP transistor. The bases of switching transistors 10121 and 10122 are electrically connected, serving as the input terminal of the driver circuit 1012. The emitters of switching transistors 10121 and 10122 are electrically connected, serving as the output terminal of the driver circuit 1012. The collector of switching transistor 10121 can be connected to a power supply. The collector of switching transistor 10122 can be grounded. The input terminal of the driver circuit 1012 can be used to input timing signals. The output terminal of the driver circuit 1012 can output amplified control signals.

[0044] In some embodiments, the waveform of the driving signal generated by the signal generation circuit 102 can be, for example, a square wave, a triangular wave, a sine wave, etc. As an example, the signal generation circuit 102 can generate one driving signal. The boost circuit 103 can generate an excitation signal based on this driving signal to excite the transducer 200 to emit ultrasonic waves. As another example, the signal generation circuit 102 can generate multiple driving signals. The boost circuit 103 can generate an excitation signal based on multiple driving signals. Multiple driving signals can include, for example, two, three, four, etc. The waveforms, amplitudes, frequencies, etc., of the multiple driving signals are the same, but their phases can be different. For example, the signal generation circuit 102 can generate two differential driving signals (…). Figure 1 The phase difference between the two differential drive signals (DRVN and DRVP) can be 180 degrees.

[0045] The excitation signal voltage is higher than the drive signal voltage. The drive signal voltage amplitude range can be 0.5V to 10V. For example, the drive signal voltage can be 0.5V, 0.9V, 1V, 2V, 3V, 5V, 7V, 8V, 9V, or 10V, etc. The excitation signal voltage amplitude range can be 15V to 40V. For example, the excitation signal voltage can be 15V, 20V, 25V, 28V, 30V, 35V, or 40V, etc. Compared to directly using the drive signal to drive the transducer 200 to emit ultrasonic waves, using a higher voltage excitation signal to drive the transducer 200 to emit ultrasonic waves can increase the energy of the ultrasonic waves emitted by the transducer 200, allowing the ultrasonic receiving circuit 300 to receive higher energy echoes. This improves the sensitivity and signal-to-noise ratio of ultrasonic detection.

[0046] In some embodiments, the signal generation circuit 102 includes multiple components (such as switching transistors). These components can switch their operating states according to a control signal, enabling the signal generation circuit 102 to generate a drive signal. The signal generation circuit 102 can be a full-bridge circuit (also known as an H-bridge circuit). For example, in... Figure 3 The signal generation circuit 102 is a full-bridge circuit. Of course, the signal generation circuit 102 can also be other circuits, such as a half-bridge circuit, a push-pull circuit, or an application-specific integrated circuit.

[0047] For example, the signal generation circuit 102 may include a first switching unit and a second switching unit. The first switching unit may include a P-type switch and an N-type switch connected in series, and the second switching unit may include a P-type switch and an N-type switch connected in series. The first switching unit can generate a high-side drive signal, and the second switching unit can generate a low-side drive signal. The boost circuit 103 can generate an excitation signal based on the high-side drive signal and the low-side drive signal.

[0048] In some embodiments, the voltage amplitude of the drive signal is in a small range (e.g., 0.5V~10V). The drive signal generated by the signal generation circuit 102 can be transmitted to the boost circuit 103. The boost circuit 103 can boost the drive signal to obtain an excitation signal. The voltage of the excitation signal is higher than that of the drive signal. The voltage amplitude of the excitation signal is in a large range (e.g., 15V~40V). The excitation signal can excite the transducer 200 to emit ultrasonic waves. The waveform of the excitation signal can be, for example, a square wave, a triangular wave, a sine wave, etc. For example, the boost circuit 103 can be an LC resonant circuit. An LC resonant circuit includes one or more inductors and one or more capacitors. An LC resonant circuit can include an LC series resonant circuit and an LC parallel resonant circuit. The LC resonant circuit can boost the drive signal by a certain multiple (e.g., N times, where N is greater than 1).

[0049] For example, please see Figure 6 The LC resonant circuit includes a first inductor 201, a first capacitor 202, a second inductor 203, and a resistor 204. The first inductor 201 and the first capacitor 202 are connected in parallel and then in series with the second inductor 203 and the resistor 204. The ultrasonic transmitting circuit 100 has two output terminals. These two output terminals output two square waves. Each output terminal can output one or more square waves, for example, 1-100 square waves. The number of square waves output by each output terminal is controllable. The frequency of the square waves output by each output terminal is controllable. The two square waves have the same waveform, amplitude, and frequency, but different phases. The frequency range of the two square waves is 6MHz-50MHz. The voltage amplitude range of the two square waves is 0.9V~5V. The two square waves can be converted into a high-voltage sine wave through the LC parallel resonant circuit. The voltage amplitude range of the sine wave is 20V~30V. Figure 6 In the diagram, the inductance of the first inductor 201 can be represented as L1, the capacitance of the first capacitor 202 as C1, the inductance of the second inductor 203 as L2, the resistance of the resistor 204 as R, and the capacitance of the second capacitor 301 as C2. The voltage applied to the transducer 200 (second capacitor 301) can be represented as... . . . The voltage of the excitation signal is represented by E, the voltage of the driving signal is represented by ω, and the angular frequency is represented by ω = 2πf, where f represents the frequency. The second capacitor 301 can be the equivalent capacitance of the transducer 200. The first inductor 201, the first capacitor 202, the second inductor 203, and the second capacitor 301 can form a coupled double resonant circuit, thus having two resonant points. and . This is the resonant point of the resonant circuit corresponding to the first inductor 201 and the first capacitor 202. This is the resonant point of the resonant circuit corresponding to the second inductor 203 and the second capacitor 301. The frequency of the driving signal. With resonance point and resonance point Matching. Matching can be, for example, the frequency of the drive signal. Near the resonance point and At the frequency of the driving signal Near the resonance point and At that time, the drive signal can be... To achieve a significant boost in voltage. It can include: equal , and The difference is less than or equal to the set threshold. The frequency of the drive signal. The area near the resonance point may include: equal , and The difference is less than or equal to the set threshold. equal , and The difference is less than or equal to a set threshold. In practical applications, the frequency of the drive signal can be determined. And the capacitance value C2 of the second capacitor 301; it can be based on L1, C1, and L2 are determined by C2. For example, C1 can be determined based on business requirements (such as process, cost, impedance matching, etc.); C2 can be determined based on... C1 and C2, using formula Calculate L1 and L2; based on calculate . The multiple between E and the voltage can be the voltage amplification factor N of the boost circuit 103.

[0050] The voltage amplitude of the excitation signal generated by the boost circuit 103 is positively correlated with the voltage swing. The voltage swing is the difference between the maximum and minimum voltage values ​​of a drive signal. For example, the voltage amplitude of the excitation signal is N times the voltage swing.

[0051] In some embodiments, transducer 200, also referred to as an ultrasonic transducer, is used to convert between electrical signals and ultrasonic waves. Transducer 200 can convert the excitation signal generated by boost circuit 103 into mechanical vibration, thereby emitting ultrasonic waves. Transducer 200 can also convert ultrasonic waves into electrical signals (such as ultrasonic signals). Transducer 200 can be a single transducer, or it can be a transducer array containing multiple transducers. The transducer array allows control of the transmission and / or reception direction of the ultrasonic signal, improving resolution and extending the detection range of the ultrasonic waves.

[0052] In some embodiments, with Figure 3 Taking the signal generation circuit 102 as an example, the signal generation circuit 102 may include a first switching unit and a second switching unit. The first switching unit may include switching transistors P1 and P2. The second switching unit may include switching transistors N1 and N2. The control circuit 101 can generate two control signals. One control signal is used to control the first switching unit, and the other control signal is used to control the second switching unit. The signal generation circuit 102 includes two output terminals, thereby outputting two driving signals, such as a high-side drive signal (e.g., DRVP) and a low-side drive signal (e.g., DRVN). The two driving signals are out of phase, and have the same waveform and frequency. The waveform of the driving signal can be, for example, a square wave. During the first half of one cycle of the control signal, switching transistors P1 and N2 are turned on, and switching transistors P2 and N1 are turned off. DRVP is high and DRVN is low. During the second half of one cycle of the control signal, switching transistors P2 and N1 are turned on, and switching transistors P1 and N2 are turned off. DRVN is high and DRVP is low. The high-side drive signal DRVP and the low-side drive signal DRVN can drive the boost circuit 103 to generate an excitation signal.

[0053] For example, the high-side voltage VP of signal generation circuit 102 is AVDD. AVDD is the output voltage of power supply power. Power supply power can be a DC power supply. The low-side voltage VN of signal generation circuit 102 is AVSS. AVSS is the voltage of reference ground of signal generation circuit 102. AVSS can be 0, for example. Then the voltage range of the high-side drive signal DRVP can be AVDD~AVSS, and the voltage amplitude range of the low-side drive signal DRVN can be AVSS~AVDD. The voltage amplitude of the excitation signal generated by boost circuit 103 can be expressed as Vtx=N×AVDD. N is the voltage amplification factor of boost circuit 103.

[0054] In some embodiments, ultrasonic waves are reflected when they encounter the object being detected. An ultrasonic receiving circuit 300 can receive the reflected echo. The ultrasonic receiving circuit 300 may include an amplification circuit and a waveform conversion circuit. A transducer 200 can receive ultrasonic waves and output an ultrasonic signal. The ultrasonic signal output by the transducer 200 is an analog signal. The ultrasonic signal output by the transducer 200 is relatively weak. The amplification circuit can amplify the ultrasonic signal output by the transducer 200 to obtain an amplified ultrasonic signal. The amplification circuit may include a single-stage amplification circuit, or it may include a multi-stage amplification circuit. The amplification circuit may be based on an operational amplifier. The waveform of the amplified ultrasonic signal is irregular and contains noise. The waveform conversion circuit can shape the amplified ultrasonic signal and output a shaped ultrasonic signal. The waveform conversion circuit may include a voltage comparator, a Schmitt trigger, etc. The shaped ultrasonic signal can be used as input to subsequent circuits. For example, the shaped ultrasonic signal can be provided to an analog-to-digital converter 400. The analog-to-digital converter 400 can convert the shaped ultrasonic signal into a digital signal. The digital signal output by the analog-to-digital converter 400 is provided to the processor for processing.

[0055] This specification also provides an ultrasonic chip in its embodiments. The ultrasonic chip can be applied to fingerprint recognition scenarios. In fingerprint recognition scenarios, the ultrasonic chip is an ultrasonic fingerprint recognition chip. The ultrasonic fingerprint recognition chip can emit ultrasonic waves. These ultrasonic waves are reflected upon encountering a fingerprint. Fingerprints are lines of raised and recessed areas on the skin. The reflectivity of raised and recessed areas differs. When ultrasonic waves encounter the raised and recessed areas of a fingerprint, the reflected echoes differ in time and intensity. The ultrasonic fingerprint recognition chip can receive the reflected echoes; it can identify the structural features of the fingerprint based on the echoes. Of course, the ultrasonic chip can also be applied to other scenarios, such as medical imaging and industrial non-destructive testing.

[0056] Figure 7 This is a schematic diagram of the structure of an ultrasonic chip in one of the embodiments of this specification. Figure 7As shown. The ultrasonic chip 500 includes one or more of the following: on-chip circuitry 100-1, transducer 200, ultrasonic receiver circuitry 300, and analog-to-digital converter circuitry 400. On-chip circuitry 100-1 and off-chip circuitry 100-2 together form ultrasonic transmitter circuitry 100. On-chip circuitry 100-1 includes low-voltage circuitry within ultrasonic transmitter circuitry 100. Both on-chip circuitry 100-1 and ultrasonic receiver circuitry 300 operate at relatively low amplitudes (e.g., 3.3V), thus allowing them to be fabricated on the ultrasonic chip 500 using the same or similar processes (e.g., medium-voltage processes). This enables the on-chip circuitry 100-1 to be deployed on the ultrasonic chip 500, improving the integration density of the ultrasonic chip 500. Off-chip circuitry 100-2 includes high-voltage circuitry within ultrasonic transmitter circuitry 100 and can be located off-chip, i.e., not on the ultrasonic chip 500. This reduces the impact of high voltage on the transducer 200 and the ultrasonic receiving circuit 300, thereby improving the sensitivity and signal-to-noise ratio of ultrasonic detection.

[0057] Considering that the timing signal generated by the timing circuit 1011 can be transmitted not only to the driving circuit 1012, but also to other circuits such as the ultrasonic receiving circuit 300, the on-chip circuit 100-1 includes at least the timing circuit 1011. Furthermore, considering that the boost circuit 103 operates at a relatively high voltage, the off-chip circuit 100-2 includes at least the boost circuit 103.

[0058] As one example, the on-chip circuit 100-1 includes a control circuit 101 and a signal generation circuit 102, while the off-chip circuit 100-2 includes a boost circuit 103. This allows as many unit modules from the ultrasonic transmitting circuit 100 as possible to be deployed on the ultrasonic chip 500, thereby maximizing the integration of the ultrasonic chip 500. As another example, the on-chip circuit 100-1 includes a control circuit 101, which includes a timing circuit 1011 and a drive circuit 1012, while the off-chip circuit 100-2 includes a signal generation circuit 102 and a boost circuit 103. The signal generation circuit 102 also operates at a relatively high voltage. By deploying the signal generation circuit 102 and the boost circuit 103 off-chip, the impact of high voltage on the transducer 200 and the ultrasonic receiving circuit 300 can be minimized, thereby maximizing the sensitivity and signal-to-noise ratio of ultrasonic detection. Of course, to provide more flexibility, as another example, the on-chip circuit 100-1 may also include a timing circuit 1011, and the off-chip circuit 100-2 may also include a driving circuit 1012, a signal generation circuit 102, and a boost circuit 103.

[0059] This specification does not specifically limit the implementation method of the off-chip circuit 100-2. For example, the off-chip circuit 100-2 can be a chip. Alternatively, the off-chip circuit 100-2 can also be a discrete component circuit. Furthermore, the off-chip circuit 100-2 can also include interconnected chips and discrete component circuits, thus allowing it to be implemented using a combination of chip and discrete component circuits.

[0060] The ultrasonic chip 500 can emit and receive ultrasonic waves. For example, on-chip circuitry 100-1 can cooperate with off-chip circuitry 100-2 to drive transducer 200 to emit ultrasonic waves. Ultrasonic receiving circuitry 300 receives the echo of the ultrasonic waves through transducer 200 and outputs a shaped echo. Analog-to-digital converter circuitry 400 converts the shaped echo into a digital signal. The digital signal output by analog-to-digital converter circuitry 400 can be transmitted to a processor via a communication interface. The ultrasonic chip 500 may also include a communication interface. The communication interface is used to carry communication protocols such as SPI or IIC for communication between the ultrasonic chip 500 and the processor.

[0061] In some embodiments, the ultrasonic chip 500 may be a stacked structure, which may include multiple stacked functional layers. Figure 8 This is a schematic diagram of the structure of an ultrasonic chip as described in one of the embodiments of this specification. Please refer to it as well. Figure 8 , Figure 9 and Figure 10 The ultrasonic chip 500 may include a circuit layer 501, a piezoelectric layer 502, an electrode layer 503, and a protective layer 504 stacked sequentially.

[0062] In some embodiments, circuit layer 501 may include substrate 5011. Circuitry may be disposed within substrate 5011. For example, one or more of the following may be disposed within substrate 5011: on-chip circuitry 100-1, ultrasonic receiving circuitry 300, analog-to-digital conversion circuitry 400, etc. The material of substrate 5011 may be silicon or other materials (such as glass-based TFTs).

[0063] The substrate 5011 can be used as a carrier for circuits. Therefore, circuits and metal wires for connecting these circuits can be fabricated inside the substrate 5011. For example, one or more of the following can be fabricated inside the substrate 5011: on-chip circuit 100-1, ultrasonic receiving circuit 300, analog-to-digital conversion circuit 400, etc. This reduces signal interference and improves circuit performance.

[0064] In some embodiments, circuit layer 501 includes a first electrode 5012. Electrode layer 503 includes a second electrode. Piezoelectric layer 502 is located between the first electrode 5012 and the second electrode. The first electrode 5012, piezoelectric layer 502, and second electrode are used to form transducer 200. The first electrode 5012 is the lower electrode of transducer 200, and the second electrode is the upper electrode of transducer 200. Any one or more of the first electrode 5012 and the second electrode may be a single electrode, or any one or more of the first electrode 5012 and the second electrode may be an electrode array containing multiple electrodes. For example, the first electrode 5012 may be an electrode array containing multiple electrodes, and the second electrode may be a single electrode. Transducer 200 may be a single transducer, or it may be an array of transducers.

[0065] The piezoelectric layer 502 can be formed of a piezoelectric material. The piezoelectric layer 502 is a thin film material with a certain thickness (e.g., 1µm–100µm). For example, the material of the piezoelectric layer 502 can be a piezoelectric single crystal, including but not limited to quartz (SiO2), lithium niobate (LiNbO3), and lithium tantalate (LiTaO3). Alternatively, the material of the piezoelectric layer 502 can also be a polycrystalline piezoelectric ceramic, including but not limited to lead zirconate titanate (PZT) and barium titanate (BaTiO3). Furthermore, the material of the piezoelectric layer 502 can also be a polymeric piezoelectric material, including but not limited to polyvinylidene fluoride (PVDF) and polypropylene (PP). Finally, the material of the piezoelectric layer 502 can also be a composite material formed from a polymer and a piezoelectric ceramic, including but not limited to PZT / polymer composites (e.g., PZT / PVDF). When emitting ultrasonic waves, the piezoelectric layer 502 generates mechanical vibration under the electric field formed by the first electrode 5012 and the second electrode, thereby radiating ultrasonic waves outward. When receiving ultrasonic waves, the ultrasonic waves act on the piezoelectric layer 502, causing the piezoelectric layer 502 to undergo mechanical deformation. The mechanical deformation generates an electrical signal between the first electrode 5012 and the second electrode.

[0066] Electrode layer 503 can be multilayered, for example, with two or three layers. Electrode layer 503 can be a conductor with good conductivity and a certain thickness (e.g., 1µm–100µm). For example, the material of electrode layer 503 can be a metallic conductive material, including but not limited to copper paste, aluminum paste, nickel paste, and silver paste. Alternatively, the material of electrode layer 503 can be a composite metallic material, including but not limited to silver-coated copper powder (AgCu), silver-nickel alloy paste (AgNi), and silver-tin oxide (AgSnO2) paste. Another example is that the material of electrode layer 503 can be a carbon-based conductive material, including but not limited to graphene, carbon nanotubes, and conductive carbon black paste. Yet another example is that the material of electrode layer 503 can be a conductive polymer, including but not limited to PEDOT, polypyrrole (PPy), and polyaniline (PANI). The fabrication process of piezoelectric layer 502 includes a polarization process, requiring the application of high voltage for polarization. By making electrode layer 503 multilayered, it is beneficial to control the distribution of the high-voltage polarization electric field. Furthermore, by configuring electrode layer 503 as multiple layers, the design of the second electrode becomes more flexible. For example, by configuring electrode layer 503 as multiple layers, the second electrode can include multiple sub-electrodes. Each layer of electrode layer 503 can include or serve as a sub-electrode. The multiple sub-electrodes can be designed with more flexible areas or shapes. For example, the area of ​​the sub-electrode closest to piezoelectric layer 502 is greater than or equal to the area of ​​the sub-electrode farthest from piezoelectric layer 502.

[0067] For example, the second electrode may include sub-electrodes 1, 2, and 3 stacked sequentially. Sub-electrode 1 is the sub-electrode closest to the piezoelectric layer 502, and sub-electrode 3 is the sub-electrode furthest from the piezoelectric layer 502. Sub-electrodes 1, 2, and 3 can be designed with more flexible areas or shapes. For example, the area of ​​sub-electrode 1 can be larger than the area of ​​sub-electrode 2 (e.g., sub-electrode 1 only covers the ultrasound region), and the area of ​​sub-electrode 2 can be larger than the area of ​​sub-electrode 3. Furthermore, the areas or shapes of sub-electrodes 1, 2, and 3 can be different. These features all contribute to the polarization of the piezoelectric layer 502.

[0068] The first electrode 5012 is disposed on the substrate 5011. For example, the first electrode 5012 can be disposed on the surface of the substrate 5011. Thus, the first electrode 5012 is in contact with one surface of the piezoelectric layer 502, and the second electrode is in contact with the other surface of the piezoelectric layer 502.

[0069] In some embodiments, circuit layer 501 may include a first pad 5014. The first pad 5014 may be located on substrate 5011, for example, on the surface of substrate 5011. The first pad 5014 may include a pad of ultrasonic chip 500 for electrical connection between ultrasonic chip 500 and external circuitry. For example, the first pad 5014 is used for electrical connection between one or more of on-chip circuitry 100-1, ultrasonic receiving circuitry 300, analog-to-digital conversion circuitry 400, etc., and external circuitry. The first pad 5014 may be a single pad (PAD), or it may be an array of pads containing multiple pads.

[0070] The first pad 5014 includes at least the pad of the on-chip circuit 100-1. The first pad 5014 is connected to at least the on-chip circuit 100-1. Thus, the on-chip circuit 100-1 can generate electrical signals and transmit electrical signals to the first pad 5014. The first pad 5014 can transmit electrical signals to at least the off-chip circuit 100-2. The off-chip circuit 100-2 can generate excitation signals based on the electrical signals and transmit the excitation signals to the transducer 200.

[0071] Of course, in addition to the pads for the on-chip circuit 100-1, the first pad 5014 may also include other pads for the ultrasonic chip 500, so that other circuits on the ultrasonic chip 500 can be connected to the outside. For example, the first pad 5014 may also include pads for the ultrasonic receiving circuit 300, pads for the analog-to-digital conversion circuit 400, etc.

[0072] In some embodiments, circuit layer 501 may include a second pad 5013. The second pad 5013 may be located on substrate 5011, for example, on the surface of substrate 5011. First pad 5014, second pad 5013, and first electrode 5012 may be located on the same surface of substrate 5011. The second pad 5013 is a pad for transducer 200 and can be connected to the second electrode. The second pad 5013 is used to transmit the excitation signal of off-chip circuit 100-2 to at least the second electrode of transducer 200. Thus, transducer 200 can convert the excitation signal of off-chip circuit 100-2 into mechanical vibration, thereby emitting ultrasonic waves.

[0073] In some scenario examples, the on-chip circuit 100-1 includes a control circuit 101 and a signal generation circuit 102, while the off-chip circuit 100-2 includes a boost circuit 103. The first pad 5014 includes a drive pad, which is connected to the signal generation circuit 102.

[0074] Therefore, control circuit 101 can generate control signals and transmit them to signal generation circuit 102. Signal generation circuit 102 can generate drive signals based on the control signals and transmit them to drive pads. Drive pads can transmit the drive signals to boost circuit 103. Boost circuit 103 can generate excitation signals based on the drive signals and transmit them to second pad 5013. Transducer 200 can convert the excitation signals generated by boost circuit 103 into mechanical vibrations, thereby emitting ultrasonic waves.

[0075] Optionally, the signal generation circuit 102 includes a first switching unit and a second switching unit. The drive signal may include a high-side drive signal generated by the first switching unit and a low-side drive signal generated by the second switching unit. The drive pad may include a first drive pad and a second drive pad. The first drive pad is connected to the first switching unit and is used to transmit the high-side drive signal to the boost circuit 103. The second drive pad is connected to the second switching unit and is used to transmit the low-side drive signal to the boost circuit 103. The boost circuit 103 is used to generate an excitation signal based on the high-side drive signal and the low-side drive signal.

[0076] In some scenario examples, the on-chip circuit 100-1 includes a timing circuit 1011, and the off-chip circuit 100-2 includes a driver circuit 1012, a signal generation circuit 102, and a boost circuit 103. The first pad 5014 includes a timing pad, which is connected to the timing circuit 1011.

[0077] Therefore, timing circuit 1011 can generate timing signals and transmit them to timing pads. The timing pads can then transmit the timing signals to drive circuit 1012. Drive circuit 1012 can generate control signals based on the timing signals and transmit them to signal generation circuit 102. Signal generation circuit 102 can generate drive signals based on the control signals and transmit them to boost circuit 103. Boost circuit 103 can generate excitation signals based on the drive signals and transmit them to second pad 5013. Transducer 200 can convert the excitation signals generated by boost circuit 103 into mechanical vibrations, thereby emitting ultrasonic waves.

[0078] Optionally, the timing signals include a first timing signal and a second timing signal. The timing pads include a first timing pad and a second timing pad. The first timing pad can transmit the first timing signal to the driver circuit 1012. The second timing pad can transmit the second timing signal to the driver circuit 1012. Optionally, the driver circuit 1012 may include a first driver circuit and a second driver circuit. The first timing pad can transmit the first timing signal to the first driver circuit. The second timing pad can transmit the second timing signal to the second driver circuit. The first driver circuit can generate a first control signal based on the first timing signal and transmit the first control signal to the signal generation circuit 102. The second driver circuit can generate a second control signal based on the second timing signal and transmit the second control signal to the signal generation circuit 102. The signal generation circuit 102 can generate a drive signal based on the first control signal and the second control signal and transmit the drive signal to the boost circuit 103.

[0079] In some scenario examples, the on-chip circuit 100-1 includes a control circuit 101, which includes a timing circuit 1011 and a drive circuit 1012. The off-chip circuit 100-2 includes a signal generation circuit 102 and a boost circuit 103. The first pad 5014 includes a control pad, which is connected to the drive circuit 1012.

[0080] Therefore, the timing circuit 1011 can generate timing signals and transmit them to the drive circuit 1012. The drive circuit 1012 can generate control signals based on the timing signals and transmit them to the control pads. The control pads can transmit the control signals to the signal generation circuit 102. The signal generation circuit 102 can generate drive signals based on the control signals and transmit them to the boost circuit 103. The boost circuit 103 can generate excitation signals based on the drive signals and transmit them to the second pad 5013. The transducer 200 can convert the excitation signals generated by the boost circuit 103 into mechanical vibrations, thereby emitting ultrasonic waves.

[0081] Optionally, the drive circuit 1012 includes a first drive circuit and a second drive circuit. The control pads include a first control pad and a second control pad. The first control pad is connected to the first drive circuit. The second control pad is connected to the second drive circuit. The first drive circuit can generate a first control signal based on a timing signal (e.g., a first timing signal) and transmit the first control signal to the first control pad. The first control pad can transmit the first control signal to the signal generation circuit 102. The second drive circuit can generate a second control signal based on a timing signal (e.g., a second timing signal) and transmit the second control signal to the second control pad. The second control pad can transmit the second control signal to the signal generation circuit 102. The signal generation circuit 102 can generate drive signals (e.g., a high-side drive signal and a low-side drive signal) based on the first and second control signals and transmit the drive signals to the boost circuit 103.

[0082] In some embodiments, please refer to Figure 12 . Figure 12 This is a schematic diagram of the on-chip circuit 100-1 within substrate 5011. The on-chip circuit 100-1 can be a stacked structure, including stacked analog circuit layers and metal wiring layers 5016. The analog circuit layer includes a P-type doped substrate 5017. A plurality of P-type switching transistors and / or a plurality of N-type switching transistors are disposed within the P-type doped substrate 5017. These P-type and / or N-type switching transistors are the switching transistors of the on-chip circuit 100-1. The P-type and / or N-type switching transistors are used to generate electrical signals. The metal wiring layer 5016 is used to transmit the generated electrical signals to the first pad 5014. Figure 12 In this context, N-Well (N-well) represents an N-type region embedded in a P-type substrate.

[0083] P-type semiconductors are formed by doping pure semiconductor materials (such as silicon or germanium) with a small amount of trivalent elements (such as boron or aluminum). N-type semiconductors are formed by doping pure semiconductor materials (such as silicon or germanium) with a small amount of pentavalent elements (such as phosphorus or arsenic). The metal trace layer 5016 may include an insulating oxide layer. Metal wiring layers and vias are provided within the insulating oxide layer. Electrical signals are transmitted to the first pad 5014 through the metal wiring layer and vias. The wiring within the insulating oxide layer has the following characteristics: the shortest path to the first pad according to design rules, the thickest via according to design rules, and the thickest trace.

[0084] As an example, the on-chip circuit 100-1 includes a control circuit 101 and a signal generation circuit 102. The plurality of P-type switches and / or the plurality of N-type switches are the switching transistors of the on-chip circuit 100-1, used to form the control circuit 101 and the signal generation circuit 102. A metal trace layer 5016 is used to transmit the drive signal generated by the signal generation circuit 102 to the drive pad. For example, the first pad 5014 includes a drive pad, which includes a first drive pad and a second drive pad. The metal trace layer 5016 is used to transmit the high-side drive signal generated by the signal generation circuit 102 to the first drive pad, and to transmit the low-side drive signal generated by the signal generation circuit 102 to the second drive pad.

[0085] As another example, the on-chip circuit 100-1 includes a timing circuit 1011 and a driving circuit 1012. The plurality of P-type switches and / or the plurality of N-type switches are the switching transistors of the on-chip circuit 100-1, used to form the timing circuit 1011 and the driving circuit 1012. A metal trace layer 5016 is used to transmit the driving signal generated by the driving circuit 1012 to the control pad. For example, the first pad 5014 includes a control pad, which includes a first control pad and a second control pad. The driving circuit 1012 includes a first driving circuit and a second driving circuit. The metal trace layer 5016 is used to transmit a first driving signal generated by the first driving circuit to the first control pad, and to transmit a second driving signal generated by the second driving circuit to the first control pad.

[0086] As another example, the on-chip circuit 100-1 includes a timing circuit 1011. The plurality of P-type switches and / or the plurality of N-type switches are the switching transistors of the on-chip circuit 100-1, used to form the timing circuit 1011. A metal trace layer 5016 is used to transmit the timing signals generated by the timing circuit 1011 to timing pads. For example, a first pad 5014 includes a timing pad, and the timing pad includes a first timing pad and a second timing pad. The metal trace layer 5016 is used to transmit the first timing signal generated by the timing circuit 1011 to the first timing pad, and to transmit the second timing signal generated by the timing circuit 1011 to the second timing pad.

[0087] In some embodiments, the ultrasonic receiving circuit 300 may be electrically connected to the first electrode 5012. Thus, the ultrasonic receiving circuit 300 can receive ultrasonic waves through the first electrode 5012. Additionally, the transducer 200 may emit ultrasonic waves based on an excitation signal from the second electrode. The emission and reception of ultrasonic waves can be achieved based on signals on different electrodes of the transducer 200. This reduces interference between the excitation signal and the ultrasonic signal received through the first electrode 5012.

[0088] In some embodiments, please refer to Figure 11The circuit layer 501 can be divided into an ultrasonic region 5015 and a non-ultrasonic region. The ultrasonic region 5015 may include the surface area where the first electrode 5012 is located and the internal region of the substrate 5011 below the surface area. The non-ultrasonic region may include the area in the circuit layer 501 other than the ultrasonic region 5015. The non-ultrasonic region may include the surface area of ​​the substrate 5011 and the internal region of the substrate 5011 below the surface area.

[0089] In some embodiments, at least a portion of the first electrode 5012 and the ultrasonic receiving circuit 300 may be located in the ultrasonic region 5015. For example, the first electrode 5012 may be located on the surface region of the substrate 5011 of the ultrasonic region 5015, and at least a portion of the ultrasonic receiving circuit 300 may be located within the substrate 5011 of the ultrasonic region 5015. By arranging the first electrode 5012 and at least a portion of the ultrasonic receiving circuit 300 in the ultrasonic region 5015, the wiring complexity inside the ultrasonic chip 500 can be simplified. Of course, the ultrasonic region 5015 may also include other circuits, such as an analog-to-digital converter circuit 400.

[0090] In some embodiments, at least a portion of the on-chip circuitry 100-1, the first pad 5014, and the second pad 5013 may be located in a non-ultrasonic region. This reduces the impact of the operating voltage of the on-chip circuitry 100-1 and the generated electrical signals on other circuits within the ultrasonic chip 500, and also reduces the impact of the excitation signal on other circuits within the ultrasonic chip 500. For example, this reduces the impact on the ultrasonic receiving circuitry 300 and the transducer 200, thereby improving the accuracy of ultrasonic detection.

[0091] In some embodiments, the piezoelectric layer 502 and the electrode layer 503 may be disposed on the ultrasonic region 5015 of the circuit layer 501. For example, the piezoelectric layer 502 may be disposed on the circuit layer 501 and cover the first electrode 5012; the electrode layer 503 may be disposed on the piezoelectric layer 502. In this way, the first electrode 5012 can contact one surface of the piezoelectric layer 502, and the second electrode can contact the other surface of the piezoelectric layer 502, thereby facilitating the formation of the transducer 200 by the first electrode 5012, the piezoelectric layer 502, and the second electrode.

[0092] In some embodiments, the protective layer 504 is used to protect the circuit layer 501, the piezoelectric layer 502, and the electrode layer 503.

[0093] The protective layer 504 is a material with a certain thickness (e.g., 1µm-100µm) and possesses insulation, water resistance, and chemical corrosion resistance. Materials for the protective layer 504 can include, for example, polyester resin, epoxy resin, polyurethane resin, and vinyl ester resin.

[0094] Please see Figure 11 . Figure 11 This is a top view of the ultrasonic chip 500. See also... Figure 11 The area of ​​circuit layer 501 is larger than that of piezoelectric layer 502, electrode layer 503, and protective layer 504. Protective layer 504 covers electrode layer 503 and piezoelectric layer 502. Thus, protective layer 504 protects electrode layer 503 and piezoelectric layer 502. Protective layer 504 covers the ultrasonic region 5015 of circuit layer 501, but does not cover the non-ultrasonic region of circuit layer 501. Thus, protective layer protects ultrasonic region 5015 while facilitating connection of the first pad 5014 and second pad 5013 in the non-ultrasonic region to external circuitry. Piezoelectric layer 502 and electrode layer 503 can cover ultrasonic region 5015. The relationship between piezoelectric layer 502 and electrode layer 503 can be determined according to actual needs. For example, piezoelectric layer 502 can completely cover electrode layer 503 or cover a portion of electrode layer 503. Similarly, electrode layer 503 can completely cover piezoelectric layer 502 or cover a portion of piezoelectric layer 502.

[0095] This specification also provides an ultrasonic module. The ultrasonic module includes an ultrasonic chip and an off-chip circuit 100-2. The ultrasonic chip and the off-chip circuit 100-2 are electrically connected via a printed circuit board (e.g., a flexible printed circuit board).

[0096] Ultrasonic modules can be applied to fingerprint recognition. They emit ultrasonic waves, which are reflected upon encountering a fingerprint. Fingerprints are patterns formed by linear arrangements of raised and recessed areas on the skin. These raised and recessed areas have different reflectivities. When ultrasonic waves encounter these areas, the reflected waves differ in time and intensity. The ultrasonic module can receive these reflected waves and identify the structural features of the fingerprint based on them. Of course, ultrasonic modules can also be applied to other scenarios, such as medical imaging.

[0097] The functional units in the embodiments of this specification can be integrated into one processing unit, or each functional unit can exist physically separately, or two or more functional units can be integrated into one processing unit.

[0098] Those skilled in the art will understand that the descriptions of the various embodiments in this specification have different focuses, and parts not described in detail in a certain embodiment can be referred to in the relevant descriptions of other embodiments. Furthermore, it is understood that those skilled in the art, after reading this specification, can conceive of any combination of some or all of the embodiments listed in this specification without creative effort, and such combinations are also within the scope of disclosure and protection of this specification.

[0099] Although this specification has been described through embodiments, those skilled in the art will understand that the above embodiments are merely illustrative of the core ideas of this specification. Those skilled in the art will appreciate that many variations and modifications are possible with this specification. It is intended that the appended claims encompass these variations and modifications without departing from the spirit of this specification.

Claims

1. An ultrasonic chip, characterized in that, It includes a circuit layer, a piezoelectric layer, and an electrode layer; The circuit layer includes a substrate, and an on-chip circuit of an ultrasonic transmitting circuit and an ultrasonic receiving circuit are provided in the substrate. A first pad, a second pad and a first electrode are provided on the substrate. The electrode layer includes a second electrode, and the ultrasonic receiving circuit is connected to the first electrode. The first pad connects to the on-chip circuit, the second pad connects to the second electrode, and the first electrode, the second electrode, and the piezoelectric layer are used to form an ultrasonic transducer. The on-chip circuitry is used to generate electrical signals and transmit the electrical signals to the first pad. The first pad is used to transmit the electrical signals to the off-chip circuitry of the ultrasonic transmitting circuit. The off-chip circuitry is used to generate excitation signals based on the electrical signals and transmit the excitation signals to the second pad. The second pad is used to transmit the excitation signals to the second electrode to drive the ultrasonic transducer to emit ultrasonic waves. The first pad, the second pad, and at least a portion of the on-chip circuit are located outside the ultrasonic region of the circuit layer, and at least a portion of the ultrasonic receiving circuit is located in the ultrasonic region, which includes the substrate surface region where the first electrode is located and the substrate interior region below the surface region.

2. The ultrasonic chip according to claim 1, characterized in that, The second electrode includes multiple sub-electrodes; The area of ​​the sub-electrode closest to the piezoelectric layer is greater than or equal to the area of ​​the sub-electrode farthest from the piezoelectric layer.

3. The ultrasonic chip according to claim 1, characterized in that, The piezoelectric layer is disposed on the circuit layer and covers the first electrode; The electrode layer is disposed on the piezoelectric layer.

4. The ultrasonic chip according to claim 1, characterized in that, It also includes a protective layer; The protective layer covers the piezoelectric layer and the electrode layer.

5. The ultrasonic chip according to claim 1, characterized in that, The on-chip circuitry includes an analog circuit layer and a metal trace layer; The analog circuit layer includes a P-type doped substrate; a plurality of P-type switching transistors and a plurality of N-type switching transistors are disposed in the P-type doped substrate, and the plurality of P-type switching transistors and the plurality of N-type switching transistors are used to form the on-chip circuit. The metal trace layer is used to transmit the electrical signal to the first pad.

6. The ultrasonic chip according to claim 1, characterized in that, The electrical signal includes a drive signal; The on-chip circuitry includes a control circuit and a signal generation circuit, the signal generation circuit being connected to the control circuit, and the first pad including a drive pad being connected to the signal generation circuit. The off-chip circuitry includes a boost circuit. The control circuit is used to generate a control signal and transmit the control signal to the signal generation circuit. The signal generation circuit is used to generate a drive signal according to the control signal and transmit the drive signal to the drive pad. The drive pad is used to transmit the drive signal to the boost circuit. The boost circuit is used to generate an excitation signal according to the drive signal and transmit the excitation signal to the second pad.

7. The ultrasonic chip according to claim 6, characterized in that, The signal generation circuit includes a full-bridge circuit, which includes a first switching unit and a second switching unit. The driving signal includes a high-side driving signal generated by the first switching unit and a low-side driving signal generated by the second switching unit. The driving pad includes a first driving pad and a second driving pad; The first drive pad is connected to the first switching unit and is used to transmit the high-side drive signal to the boost circuit; The second drive pad is connected to the second switching unit and is used to transmit the low-end drive signal to the boost circuit; The boost circuit is used to generate the excitation signal based on the high-side drive signal and the low-side drive signal.

8. The ultrasonic chip according to claim 7, characterized in that, The first switching unit includes a P-type switch and an N-type switch connected in series; The second switching unit includes a P-type switch and an N-type switch connected in series.

9. The ultrasonic chip according to claim 6, characterized in that, The control circuit includes several P-type switching transistors and several N-type switching transistors.

10. The ultrasonic chip according to claim 1, characterized in that, The electrical signal includes a timing signal; The on-chip circuitry includes timing circuitry, and the first pad includes timing pads connected to the timing circuitry; the off-chip circuitry includes a driver circuit, a signal generation circuit, and a boost circuit, with the signal generation circuit connected to the driver circuit and the boost circuit connected to the signal generation circuit. The timing circuit is used to generate timing signals and transmit the timing signals to the timing pads. The timing pads are used to transmit the timing signals to the driving circuit. The driving circuit is used to generate control signals based on the timing signals and transmit the control signals to the signal generation circuit. The signal generation circuit is used to generate driving signals based on the control signals and transmit the driving signals to the boost circuit. The boost circuit is used to generate excitation signals based on the driving signals and transmit the excitation signals to the second pads.

11. The ultrasonic chip according to claim 10, characterized in that, The timing signal includes a first timing signal and a second timing signal, and the timing pad includes a first timing pad and a second timing pad; The first timing pad is used to transmit the first timing signal to the driving circuit; The second timing pad is used to transmit the second timing signal to the drive circuit; The driving circuit is used to generate the control signal based on the first timing signal and the second timing signal.

12. The ultrasonic chip according to claim 1, characterized in that, The electrical signal includes a control signal; The on-chip circuitry includes a timing circuitry and a driving circuitry, with the driving circuitry connected to the timing circuitry. The first pad includes a control pad, which is connected to the driving circuitry. The off-chip circuitry includes a signal generation circuit and a boost circuit, with the boost circuitry connected to the signal generation circuitry. The timing circuit is used to generate timing signals and transmit the timing signals to the driving circuit. The driving circuit is used to generate control signals according to the timing signals and transmit the control signals to the control pads. The control pads are used to transmit the control signals to the signal generation circuit. The signal generation circuit is used to generate driving signals according to the control signals and transmit the driving signals to the boost circuit. The boost circuit is used to generate excitation signals according to the driving signals and transmit the excitation signals to the second pads.

13. The ultrasonic chip according to claim 12, characterized in that, The driving circuit includes a first driving circuit and a second driving circuit, and the control pad includes a first control pad and a second control pad. The first control pad is connected to the first driving circuit, and the second control pad is connected to the second driving circuit. The first driving circuit is used to generate a first control signal according to the timing signal and to transmit the first control signal to the first control pad, wherein the first control pad is used to transmit the first control signal to the signal generation circuit. The second driving circuit is used to generate a second control signal according to the timing signal and to transmit the second control signal to the second control pad, wherein the second control pad is used to transmit the second control signal to the signal generation circuit; The signal generation circuit is used to generate the drive signal based on the first control signal and the second control signal.

14. The ultrasonic chip according to claim 1, characterized in that, The off-chip circuit is a chip; Alternatively, the off-chip circuitry can be a discrete component circuit. Alternatively, the off-chip circuitry may include interconnected chips and discrete component circuits.

15. An ultrasonic module, characterized in that, The off-chip circuitry includes the ultrasonic chip and ultrasonic transmitting circuitry as described in any one of claims 1-14.

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