PWM (Pulse Width Modulation) module design circuit for reducing dead time and working method thereof

Abstract

The invention provides a PWM module design circuit for reducing dead time and a working method thereof, and belongs to the technical field of analog integrated circuits. Through cooperative work of the first lifting path and the second lifting path, the voltage of the VSUM node is quickly lifted at the voltage rising edge of the SW node. Therefore, the PWM comparator can make a response more quickly, output signals are overturned, and dead time which must be set for preventing straight-through of an upper power tube and a lower power tube is greatly shortened. The reduction of the dead time means that the effective conduction time of the power tube is increased, so that the switching loss is reduced, and the conversion efficiency of the whole power supply system is improved. And by delaying to start a time sequence control strategy of the M6, the dual-path automatic management is creatively realized. In the key initial stage of SW rising, M6 is not started; when the SW is stable, the M6 is turned on, the VSUM voltage is boosted to the state that the SW voltage is smaller than the breakover voltage of the body diode, the second boosted path is automatically cut off, and continuous electric leakage or invalid power consumption through the body diode in a steady state is avoided.

Description

Technical Field

[0001] This invention belongs to the field of analog integrated circuit technology, specifically relating to a PWM module design circuit and its working method for reducing dead time. Background Technology

[0002] In fields such as electronic power conversion and motor drives, PWM (Pulse Width Modulation) modules are core components for achieving precise control, and their performance directly determines the system's efficiency, response speed, and stability. During the operation of a PWM module, a dead time is typically set to prevent short circuits caused by simultaneous conduction of the upper and lower power transistors. Dead time refers to the interval during the switching process between the upper and lower transistors, ensuring that the lower transistor only turns on after the upper transistor is completely turned off, or vice versa.

[0003] However, the existence of dead time brings a series of problems: excessively long dead time can lead to output waveform distortion and reduced conversion efficiency, especially in high-frequency applications where its negative impact on system performance is more significant. Therefore, minimizing dead time while ensuring circuit safety has become a key technical challenge in PWM module design.

[0004] In the specific working mechanism of the PWM module, V SUM The synchronization characteristics of the signal and the SW signal are the core factors affecting dead time design. SUM The output of the error amplifier is converted by the circuit, and SW is the current sampling result. Both serve as input signals to the PWM comparator, and their relative levels directly determine the comparator's output state. If VSUM and SW cannot rise and fall synchronously, the PWM comparator may erroneously flip, causing circuit malfunctions. Therefore, it is crucial to ensure that V... SUM Synchronizing the rise and fall with the SW is a fundamental requirement for maintaining the normal operation of the PWM module.

[0005] Defects and shortcomings of existing technology: In the existing technology, in order to satisfy V SUM The functional requirement of synchronous lifting and lowering with SW mainly adopts the following V SUM It has a production method, but it has significant drawbacks: Existing technologies utilize higher V IN (Input voltage), when the enable signal ENB arrives (i.e., the upper transistor is turned on), V will be... SUM Rapidly boost to the target voltage. This method, although it can utilize V... IN High voltage characteristics achieve V SUM The rapid rise, but with fundamental flaws: Due to circuit structure limitations, the voltage at node SW is naturally lower than V. IN When using V IN Drive V SUM When rising, V SUM The voltage will be due to V IN The voltage difference between the PWM comparator and the voltage switch (SW) causes overshoot. This overshoot can lead to abnormal input signals in the PWM comparator, potentially causing the comparator to flip prematurely and disrupting the normal operating logic of the circuit.

[0006] To mitigate these risks, the designers had to extend the dead time and increase the interval between switching between the upper and lower transistors to shield V. IN The impact of overshoot on comparators. However, the extension of dead time directly leads to a series of performance degradations, such as decreased circuit efficiency, increased output ripple, and slower dynamic response speed, making it difficult to meet the design requirements of high-precision and high-efficiency electronic systems. Summary of the Invention

[0007] The purpose of this invention is to overcome the above-mentioned shortcomings and provide a PWM module design circuit and its working method for reducing dead time.

[0008] To achieve the above objectives, the present invention adopts the following technical solution: In a first aspect, the present invention provides a PWM module design circuit for reducing dead time, comprising an enable module and a rise module, wherein the enable module is connected to the rise module, and: The enabling module includes an enabling signal ENB; The lifting module includes a first lifting path and a second lifting path. The first lifting path includes a two-stage inverter connected in sequence. The output terminal of the two-stage inverter is connected to a capacitor C, and the output terminal of capacitor C is connected to the non-inverting input terminal V of a PWM comparator. SUM The second boost path includes NMOS transistors M3 and M4. The sources and bodies of NMOS transistors M3 and M4 are connected to the switching node SW, and their drains are connected to the non-inverting input V of the PWM comparator. SUM At the node, the gate of NMOS transistor M3 is connected to the source of NMOS transistor M6, and the gate of NMOS transistor M4 is connected to the enable signal ENB.

[0009] The enable signal ENB logic 1 voltage is BST, the gate of NMOS transistor M1 is connected to BST, and the drain is connected to the input voltage terminal V. IN The source is connected to both the drain of NMOS transistor M6 and the drain of voltage limiting transistor M2. The gate of voltage limiting transistor M2 is connected to the internal power supply terminal INTVCC, and the source is electrically connected to the external low-voltage module interface to connect to other circuits. The gate of NMOS transistor M6 is connected to the output terminal of the enable signal ENB after passing through a first-stage inverter.

[0010] The source circuit of the voltage limiting transistor M2 is connected to a pull-down circuit module, which includes an NMOS transistor M5. The gate of the NMOS transistor M5 is connected to the control voltage terminal V. C The source is connected to the upper end of resistor R, the drain is connected to an external power supply, and the lower end of resistor R is grounded.

[0011] The NMOS transistors M1, M2, and M6 are high-voltage transistors with thickened drain terminals.

[0012] In the circuit, the power supply terminal VDD of the inverter and the PWM comparator are both connected to the BST voltage terminal, and the ground terminal VSS is connected to the switching node SW.

[0013] The NMOS transistors M3 and M4 are low-voltage transistors with integrated high-voltage ring structures.

[0014] The non-inverting input of the PWM comparator is connected to V SUM The node has its inverting input connected to the switch node SW, and its output is a PWM signal after being buffered by a buffer.

[0015] Secondly, the present invention provides a method for designing a PWM module circuit to reduce dead time, as detailed below: When the upper transistor is turned on, the BST voltage is about 3.4V higher than the SW voltage, and the NMOS transistor M1 starts to work. After NMOS transistor M1 is turned on, the pull-down circuit module provides pull-down current, which causes a voltage drop at the source of NMOS transistor M1. The turn-on signal of the upper transistor will be delayed, causing the ENB signal to flip slightly behind the change of SW voltage. During the delay time, the voltage change at the switching node SW is used to raise the non-inverting input V of the PWM comparator through the coordinated action of the first and second boosting paths. SUM The voltage at the node.

[0016] The non-inverting input V of the PWM comparator is raised through the first and second lifting paths in a coordinated manner. SUM The specific method for determining the node voltage is as follows: When the voltage at node SW rises rapidly from a low level, the capacitor C in the first rise path causes V to... SUM The node generates a momentary voltage rise; simultaneously, through the body diode of the second rise path, voltage is transferred from the SW node to V. SUM Charge is injected into the node to compensate for the insufficient charging capacity caused by the original voltage difference between the upper and lower plates of capacitor C.

[0017] Once SW stabilizes, NMOS transistor M6 is turned on, and the gate potential of NMOS transistor M3 and the drain potential of NMOS transistor M4 are pulled up, thereby turning off the second boost path.

[0018] Compared with the prior art, the present invention has the following beneficial effects: This invention provides a PWM module design circuit and its operating method for reducing dead time. Through the coordinated operation of a first rise path and a second rise path, V is rapidly raised at the rising edge of the SW node voltage. SUM Node voltage. This allows the PWM comparator to respond faster, with the output signal flipping, significantly shortening the dead time that must be set to prevent shoot-through of the upper and lower power transistors. The reduced dead time means an increase in the effective conduction time of the power transistors, thereby reducing switching losses and improving the overall power system conversion efficiency. Through a timing control strategy that delays the activation of M6, automatic management of the dual paths is creatively achieved. In the critical initial stage of SW rise, M6 is not activated, and both paths operate simultaneously to provide the maximum boost current; once SW stabilizes, M6 activates, and V... SUM Once the voltage rises to a level where the voltage at SW is less than the forward voltage of the body diode, the second rise path is automatically cut off, preventing continuous leakage or ineffective power consumption through the body diode in steady state. This intelligent path management ensures both rapid transient response and manageable power consumption and reliability in steady state.

[0019] Furthermore, this synergistic mechanism of capacitive coupling transient rise and body diode charge replenishment ensures V SUM The node can quickly and smoothly follow the high voltage slew rate changes of the SW node, avoiding the influence of V. SUM The PWM signal distortion caused by slow response ensures the stability and accuracy of loop control.

[0020] Furthermore, this circuit utilizes the inherent body diode of the MOSFET to form a boost path, eliminating the need for additional external components or complex level shifting circuits, resulting in a simple structure that is easy to integrate. Simultaneously, the use of low-voltage transistors with a high-voltage ring structure as M3 and M4, and the design of key MOSFETs as high-voltage transistors with thickened drain terminals, significantly improves the circuit's withstand voltage and long-term reliability under high-voltage switching environments, reducing design risks.

[0021] Furthermore, due to the complete elimination of V SUM The risk of comparator malfunction caused by overshoot is eliminated, eliminating the need for extending the dead time to mitigate this risk and significantly shortening the switching interval between the upper and lower transistors. This directly improves circuit performance: reducing output waveform distortion and increasing power conversion efficiency. Especially in high-frequency applications, it effectively reduces energy loss caused by excessively long dead times, meeting the design requirements of high-precision, high-efficiency electronic systems. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a circuit structure diagram of the present invention; The following are the labeling symbols in the diagram: 1. First inverter; 2. Second inverter; 3. Third inverter; 4. PWM comparator; 5. Buffer. Detailed Implementation

[0024] To further understand the content of this invention, the invention will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments are merely illustrative and not limiting of the invention.

[0025] The accompanying drawings illustrate various structural schematic diagrams according to embodiments disclosed in this invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0026] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0027] Example 1 like Figure 1 As shown, a PWM module design circuit for reducing dead time has the following structure: A PWM module design circuit for reducing dead time is disclosed. This circuit mainly includes an enable module, a rise module, and a pull-down circuit module. The enable module responds to a high-level active enable signal ENB, providing a controlled high-voltage power supply to subsequent circuits. Specifically, logic 1 of the enable signal ENB is the bootstrap voltage BST, and logic 0 of the enable signal ENB is SW. The NMOS transistor M1 is a high-voltage switch, with its gate connected to the BST voltage and its drain connected to the input voltage V. IN The source is connected to both the drain of NMOS transistor M6 and the drain of voltage limiting transistor M2. When ENB is active, after being inverted by the first inverter 1, its output signal controls the gate of NMOS transistor M6. After NMOS transistor M6 is turned on, its drain potential is transferred to V. SUM At the same time, NMOS transistor M1 is turned on because its gate BST is positively biased relative to its source, thus turning V...IN The voltage is transferred to the drain of the voltage limiting transistor M2. M2 is also a high-voltage NMOS transistor, with its gate connected to the internal power supply INTVCC. The function of M2 is to reduce the high voltage V from M1. IN Clamped to a safe voltage level to prevent damage to subsequent low-voltage circuitry due to overvoltage.

[0028] The lift-up module is key to realizing the core function of this invention, and it includes a first lift-up path and a second lift-up path. The first lift-up path (coupling capacitor path) includes a two-stage inverter connected in sequence. The output of the two-stage inverter is connected to a capacitor C, and the output of capacitor C is connected to the non-inverting input V of a PWM comparator. SUM Node. One end of capacitor C receives control signals through the second inverter 2 and the third inverter 3, while the other end is directly connected to the non-inverting input of the PWM comparator, i.e., V. SUM Node. This path utilizes the property that capacitor voltage cannot change abruptly. When the voltage at node SW changes rapidly, this change is directly transmitted to V through the coupling effect of capacitor C. SUM The first node enables instantaneous voltage boosting. The second boosting path (body diode path) consists of NMOS transistors M3 and M4. NMOS transistors M3 and M4 are low-voltage transistors employing an integrated high-voltage ring structure. Their sources and bodies are connected to the switching node SW. The gate of NMOS transistor M3 is connected to the source of NMOS transistor M6, and the gate of NMOS transistor M4 is connected to ENB. Their drains are connected to V. SUM In this embodiment, the body diodes of NMOS transistors M3 and M4 are fully utilized. During a specific operating phase, when the SW voltage rises but the gate voltages of M3 and M4 have not yet been pulled up, their body diodes are forward biased, allowing the SW node to supply power to V. SUM Node charging provides a low-impedance path.

[0029] The pull-down circuit module consists of an NMOS transistor M5 and a resistor R. The gate of the NMOS transistor M5 is controlled by the control voltage VC, its source is connected to the upper end of the resistor R, the lower end of the resistor R is grounded, and its drain is connected to an external power supply. This module reliably pulls down the voltage node of the source of the voltage limiting transistor M2 to ground, thereby generating a voltage drop at the drain of the NMOS transistor M6.

[0030] Furthermore, NMOS transistors M1, M2, and M6 are high-voltage transistors with thickened drain terminals.

[0031] Furthermore, in the circuit, the power supply terminal VDD of both the inverter and PWM comparator 4 is connected to the BST voltage terminal, and the ground terminal VSS is connected to the switching node SW. This connection achieves V... SUM Dual-path synchronous lifting, M6 timing delay control, and high and low voltage circuit compatible power supply.

[0032] Furthermore, NMOS transistor M1 is a continuously conducting high-voltage transistor, and its function in the circuit is as a resistor; NMOS transistor M2 is a voltage limiting transistor, protecting the low-voltage circuit connected after it.

[0033] Furthermore, SW represents the current sampling result in the PWM module, V SUM The signals generated by the error amplifier output and converted by the circuit are the input signals of PWM comparator 4; the non-inverting input of PWM comparator 4 is connected to V. SUM The node has its inverting input connected to the switch node SW, and its output is a low-voltage PWM signal after being buffered by buffer 5.

[0034] Example 2 A PWM module design circuit for reducing dead time, and its operation method is as follows: In this circuit, there are two types of V SUM The generation methods are as follows. The first method utilizes a higher V. IN When the enable signal arrives, i.e., when the upper transistor is turned on, V will be... SUM Increase it to a certain value. However, this approach carries risks. Utilize V IN It is certainly possible to quickly convert V SUM The voltage is pulled up to the required level, but due to the circuit structure, SW is naturally lower than V. IN If it's lower, then this design will lead to V SUM When overshoot occurs, the PWM comparator will not prematurely flip to ensure normal circuit function. This requires designers to design a longer dead time for the circuit, which in turn leads to a decrease in circuit performance.

[0035] Therefore, the present invention adopts the following alternative V SUM The specific methods by which are generated are as follows: Initialization and Enable Phase: When BST is low, the entire circuit does not operate. When BST is high and the upper transistor (not shown in the diagram, usually connected between VIN and SW) is turned on, the BST voltage is higher than V. IN With the SW voltage around 3.4V, NMOS transistor M1 starts working. The pull-down circuit module provides pull-down current, causing a voltage drop at the source of NMOS transistor M1. The turn-on signal of the upper transistor is delayed, causing the ENB signal to lag behind the change in the SW voltage, and M6 is not turned on. After a delay, the ENB signal flips and M6 turns on. During this delay, V is turned on through the first and second rise paths. SUM The voltage is rapidly increased to near the SW voltage. After M6 is turned on, the drain voltage of M6 is transferred to V. SUM .

[0036] Collaborative rise phase: As the upper transistor is turned on, the voltage at node SW rises rapidly from a low level. At this time, since M6 is not yet turned on, the gate of M3 and the drain of M4 are at a low level, and their body diodes are forward biased due to the increase in SW voltage.

[0037] The second lifting path (body diode) takes the lead: the current at node SW is rapidly transferred to V through the body diodes of M3 and M4. SUM Node charging, this is to raise V SUM The first force of voltage.

[0038] The first rise path (capacitive coupling) has a synchronous effect: almost simultaneously, the voltage jump at node SW is coupled to V through the coupling capacitor C. SUM The node generates a momentary voltage surge, which is the second force.

[0039] The coordinated operation of these two paths ensures V SUM The node can follow the voltage rise of the SW node at an extremely high speed, making it easier for the drain of M6 to transfer voltage to V. SUM At this point, as the SW voltage decreases, the PWM signal flips. This significantly shortens the delay from the rise of SW to the flip of the PWM signal, effectively reducing the dead time.

[0040] Path Off and Steady-State Phase: After a delay following the BST flip-through, the gate signal of NMOS transistor M6 goes high, turning on M6. The conduction of M6 rapidly pulls the gate potential of M3 and the drain potential of M4 up to near the SW potential, thus turning off the body diodes of M3 and M4. At this point, the second boost path is automatically cut off, and the circuit enters steady-state operation. At this time, V... SUM The node voltage is determined by the drain of M6, which is also part of the other feedback network. The capacitor C in the first boost path has also finished charging and no longer functions. This design avoids continuous conduction losses through the body diode in steady state.

[0041] Preferably, NMOS transistors M1, M2, and M6 are high-voltage transistors with specially reinforced drain terminals to withstand the high slew rate of the SW node. The power supply terminals VDD of all inverters and PWM comparators in the circuit are connected to BST, and the ground terminals VSS are connected to SW. This allows these low-voltage devices to operate in a relatively stable voltage domain referenced to SW, ensuring signal accuracy.

[0042] In conclusion, in V SUM Rise, any stage before M6 begins (V) SUM Neither voltage can exceed SW, and the voltage difference can always be maintained at a minimum of approximately 0.7V. This ensures that the PWM comparator 4 will not erroneously flip at this time. SUMWhen the power supply rises until M6 is activated, the potential overshoot risk during this phase is eliminated, thus eliminating the need for dead time shielding and reducing the design dead time. This implementation method efficiently solves the problem of excessively long dead time in switching power supplies through a clever timing control and dual-path cooperative lift mechanism, demonstrating high practical value.

[0043] Finally, it should be noted that the above embodiments only describe the basic principles, main features, and advantages of the present invention. For those skilled in the art, it is obvious that the present invention is not limited to the details of the above exemplary embodiments, and that the present invention can be implemented in other specific forms without departing from the spirit or basic characteristics of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects. The scope of the present invention is defined by the appended claims rather than the foregoing description, and therefore all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0044] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can be appropriately combined to form other embodiments that can be understood by those skilled in the art. The above content is only for illustrating the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. Any modifications made based on the technical concept proposed in this invention shall fall within the scope of protection of the claims of this invention.

Claims

1. A PWM module design circuit for reducing dead time, characterized in that, It includes an enable module and a lift module, wherein the enable module is connected to the lift module, and: The enabling module includes an enabling signal ENB; The lifting module includes a first lifting path and a second lifting path. The first lifting path includes a two-stage inverter connected in sequence. The output terminal of the two-stage inverter is connected to a capacitor C, and the output terminal of capacitor C is connected to the non-inverting input terminal V of a PWM comparator. SUM The second boost path includes NMOS transistors M3 and M4. The sources and bodies of NMOS transistors M3 and M4 are connected to the switching node SW, and their drains are connected to the non-inverting input V of the PWM comparator. SUM At the node, the gate of NMOS transistor M3 is connected to the source of NMOS transistor M6, and the gate of NMOS transistor M4 is connected to the enable signal ENB.

2. The PWM module design circuit for reducing dead time as shown in claim 1, characterized in that, The enable signal ENB logic 1 voltage is BST, the gate of NMOS transistor M1 is connected to BST, and the drain is connected to the input voltage terminal V. IN The source is connected to both the drain of NMOS transistor M6 and the drain of voltage limiting transistor M2. The gate of voltage limiting transistor M2 is connected to the internal power supply terminal INTVCC, and the source is electrically connected to the external low-voltage module interface to connect to other circuits. The gate of NMOS transistor M6 is connected to the output terminal of the enable signal ENB after passing through a first-stage inverter.

3. The PWM module design circuit for reducing dead time as shown in claim 2, characterized in that, The source circuit of the voltage limiting transistor M2 is connected to a pull-down circuit module, which includes an NMOS transistor M5. The gate of the NMOS transistor M5 is connected to the control voltage terminal V. C The source is connected to the upper end of resistor R, the drain is connected to an external power supply, and the lower end of resistor R is grounded.

4. A PWM module design circuit for reducing dead time as shown in claim 2, characterized in that, The NMOS transistors M1, M2, and M6 are high-voltage transistors with thickened drain terminals.

5. A PWM module design circuit for reducing dead time according to claim 2, characterized in that, In the circuit, the power supply terminal VDD of the inverter and the PWM comparator are both connected to the BST voltage terminal, and the ground terminal VSS is connected to the switching node SW.

6. A PWM module design circuit for reducing dead time according to claim 1, characterized in that, The NMOS transistors M3 and M4 are low-voltage transistors with integrated high-voltage ring structures.

7. A PWM module design circuit for reducing dead time according to claim 1, characterized in that, The non-inverting input of the PWM comparator (4) is connected to V SUM The node, the inverting input terminal is connected to the switch node SW, and the output terminal is buffered by the buffer (5) to output the PWM signal.

8. A method for designing a PWM module circuit to reduce dead time, characterized in that, The PWM module design circuit for reducing dead time according to any one of claims 1 to 7 is characterized by the following: When the upper transistor is turned on, the BST voltage is higher than V. IN With the voltage SW, NMOS transistor M1 starts working; After NMOS transistor M1 is turned on, the pull-down circuit module provides pull-down current, which causes a voltage drop at the source of NMOS transistor M1. The turn-on signal of the upper transistor will be delayed, causing the ENB signal to flip behind the change of SW voltage, and M6 is not turned on. During the delay time, the voltage change at the switching node SW is used to raise the non-inverting input V of the PWM comparator through the coordinated action of the first and second boosting paths. SUM The voltage at the node.

9. The operating method of a PWM module design circuit for reducing dead time according to claim 8, characterized in that, The non-inverting input V of the PWM comparator is raised through the first and second lifting paths in a coordinated manner. SUM The specific method for determining the node voltage is as follows: When the voltage at node SW rises rapidly from a low level, the capacitor C in the first rise path causes V to... SUM The node generates a momentary voltage rise; simultaneously, through the body diode of the second rise path, voltage is transferred from the SW node to V. SUM Charge is injected into the node to compensate for the insufficient charging capacity caused by the original voltage difference between the upper and lower plates of capacitor C.

10. The operating method of a PWM module design circuit for reducing dead time according to claim 9, characterized in that, Once SW stabilizes, NMOS transistor M6 is turned on, and the gate potential of NMOS transistor M3 and the drain potential of NMOS transistor M4 are pulled up, thereby turning off the second boost path.

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