Low-power-consumption DC-DC system based on V2COT architecture

Abstract

The invention relates to a low-power-consumption DC-DC system based on a V2COT architecture, and belongs to the technical field of switching power supplies. The low-power-consumption DC-DC system based on the V2COT architecture comprises an operational amplifier Av serving as a first stage of the V2COT architecture, a comparator Fm1 serving as a second stage of the V2COT architecture and a low-power-consumption mode comparator Fm2, after a light load state is detected, the system is switched from a normal mode to a low-power-consumption mode, after the system enters the low-power-consumption mode, the first-stage operational amplifier Av does not consume current, and the second-stage operational amplifier Av does not consume current. In the second stage, a comparator Fm1 is switched to a low-power-consumption mode comparator Fm2, the current of the comparators is reduced, a voltage refreshing timing circuit is further utilized, a refreshing mode is entered after the low-power-consumption mode is entered, the reference module output voltage and the operational amplifier output voltage are refreshed, the stable output voltage is provided, meanwhile, the current of the reference module can be thoroughly cut off, and the output voltage of the operational amplifier is increased. Therefore, the power consumption of the DC-DC system during light load and no load is effectively reduced.

Description

Technical Field

[0001] This invention relates to the field of switching power supply technology, and particularly to the field of low-power switching power supply technology, specifically a low-power DC-DC system based on V2COT architecture. Background Technology

[0002] In existing technologies, buck DC-DC converters using a COT architecture offer better transient response, while the V2COT (Voltage to Constant On-Time) architecture can improve DC voltage regulation accuracy. Upon entering a light-load / no-load state, most DC-DC converters employ various methods to reduce power consumption and improve efficiency, such as using timers to calculate fixed-time reconstruction of the LDO output voltage. However, the output of some modules is indispensable under light-load conditions. Therefore, most DC-DC systems must ensure the bias current of the error amplifier and reference module under light-load conditions, which increases power consumption. Simultaneously, the timer requires bias current, and its topping point is significantly affected by the input voltage and the parameters of various components, resulting in a larger final refresh time deviation.

[0003] Therefore, how to reduce power consumption under light load conditions has become an urgent problem to be solved in this field. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a low-power DC-DC system based on the V2COT architecture that can completely shut off the reference module current, reduce the comparator current, and provide a stable output voltage under light load conditions.

[0005] To achieve the above objectives, the low-power DC-DC system based on the V2COT architecture of the present invention has the following configuration: This low-power DC-DC system based on the V2COT architecture includes: Operational amplifier Av, as the first stage of the V2COT architecture, has its input connected to the feedback voltage FB and the reference voltage V. REF4 Its output provides V EC The signal, a constant current source, is transmitted through switch S. EA Connect the enable pin of the op-amp Av; The reference module BG provides the reference voltage V via switch S3. REF4 Reference voltage V REF4 Connect one end of capacitor C0, and ground the other end of capacitor C0; Comparator Fm1 and low-power mode comparator Fm2, as the second stage of the V2COT architecture, have their feedback voltage FB connected to one input terminal of comparator Fm1 and low-power mode comparator Fm2 respectively via switches S5 and S7; the V ECThe signal first passes through switch S4, then through switches S6 and S8 respectively, and is connected to the other input terminals of comparator Fm1 and low-power mode comparator Fm2. EC The signal is also connected to one end of capacitor C1 via switch S4, and the other end of capacitor C1 is grounded; The comparator Fm1 outputs a PWM_OUT1 signal, which controls the conduction of the upper power transistor in the power stage of the DC-DC system. The PWM_OUT1 signal is grounded through switch S9. The power stage also includes a lower power transistor, an inductor, an output capacitor, and voltage divider resistors, with the feedback voltage FB provided between the voltage divider resistors. The output of the low-power mode comparator Fm2 is a PWM_OUT2 signal, which is connected to the low-power mode determination logic unit PS LOGIC. This PWM_OUT2 signal is transmitted through switch S. 10 Grounded; the input of the low-power mode judgment logic unit PS LOGIC is also connected to a light load detection signal; the light load detection generates the light load detection signal after determining that the load of the switching power supply is lower than a preset value, and the low-power mode judgment logic unit PS LOGIC generates a low-power mode enable signal, the PS signal output goes high, and the system enters the low-power mode from the normal mode; when the low-power mode judgment logic unit PS LOGIC receives the PWM_OUT2 signal, the PS signal output goes low, and the system exits the low-power mode; In normal mode, controlled by the PS signal, switches S7 and S8 are open, the low-power mode comparator Fm2 is not working, switch S9 is also open, and switch S... EA S3, S4, S5, S6 and S 10 Conduction; After entering low-power mode, under the control of the PS signal, switch S3 is disconnected, and the reference voltage V... REF4 The energy is stored in capacitor C0; then switches S5 and S6 are opened, comparator Fm1 is not working; switches S7 and S8 are turned on to enable the low-power mode comparator Fm2, switching the second-stage comparator; then switch S4 is opened, and the V... EC The signal is stored in capacitor C1 and continues to serve as the input to comparator Fm1, after which switch S is opened. EA The first-stage op-amp Av does not consume current; then, switch S9 turns on, pulling the PWM_OUT1 signal low, and switch S... 10 Disconnecting the output of the low-power mode comparator Fm2 enables it. At this time, the low-power mode comparator Fm2 continues to monitor the feedback voltage FB. When the low-power mode comparator Fm2 determines that the feedback voltage FB is lower than V... ECWhen the signal is low, the PWM_OUT2 signal is output, and when the PS signal goes low, the low-power mode is exited.

[0006] In this low-power DC-DC system based on the V2COT architecture, the constant current source is connected to switch S. BG Connecting the aforementioned reference module BG, in the aforementioned normal mode, the switch S BG The switch S is turned on; after entering low-power mode, the switch S... BG When disconnected, the reference module BG does not consume current.

[0007] This low-power DC-DC system based on the V2COT architecture also includes a voltage refresh timing circuit, which comprises several voltage divider resistors R1, R2, R3…R connected in series between the reference output VREF1 of the reference module BG and ground. n It also includes the voltage refresh comparator COMP and the refresh logic unit RESET LOGIC. The voltage divider resistors R1, R2, R3...R n A voltage divider output terminal is provided between the two terminals, and one of the voltage divider output terminals provides a reference voltage V. REF4 Voltage divider resistor R n-2 With voltage divider resistor R n-1 The voltage divider output terminal between the two terminals supplies voltage V to one input terminal of the voltage refresh comparator COMP via switch S1. REF3 The voltage V REF3 Sampling capacitor C3 is connected to ground; resistor R n-1 With voltage divider resistor R n The voltage divider output terminal between the two terminals supplies voltage V to the other input terminal of the voltage refresh comparator COMP via switch S2. REF2 The voltage V REF2 A sampling capacitor C2 is connected to ground; the capacitance value of the sampling capacitor C3 is greater than the capacitance value of the sampling capacitor C2. The output of the voltage refresh comparator COMP is connected to the refresh logic unit RESET LOGIC, and the output of the refresh logic unit RESET LOGIC provides the output RESET signal of the voltage refresh timing circuit. After entering the low-power mode, the refresh logic unit RESET LOGIC outputs a RESET signal, entering refresh mode. At this time, switch S... BG When activated, the reference module BG establishes various reference potentials, and the switch S... EA The circuit is activated, establishing the first-stage operational amplifier's potential Av. After a period of time, once all potentials are established, switch S3 opens, providing the reference voltage V. REF4 When switch S4 at the output terminal of op-amp Av is turned on, the output V is turned on.EC The low-power mode comparator Fm2 adds a current channel to accelerate the detection speed; after a delay, once the output stabilizes, it exits the refresh mode and enters the low-power mode.

[0008] In this low-power DC-DC system based on the V2COT architecture, the PWM_OUT1 signal is connected to the input of the constant on-time module ON TIMER. The output of the constant on-time module ON TIMER outputs a fixed pulse width signal TON to control the conduction of the upper power transistor, which is used to determine the moment when the upper power transistor is turned off.

[0009] The low-power DC-DC system based on the V2COT architecture of this invention includes an operational amplifier Av as the first stage of the V2COT architecture, a comparator Fm1 as the second stage of the V2COT architecture, and a low-power mode comparator Fm2. After detecting a light load state, the system switches from normal mode to low-power mode. After entering the low-power mode, the first-stage operational amplifier Av does not consume current, and the second stage switches from comparator Fm1 to low-power mode comparator Fm2, reducing the comparator current. Furthermore, by utilizing a voltage refresh timing circuit, after entering the low-power mode, it enters refresh mode to refresh the output voltage of the reference module and the output voltage of the operational amplifier to provide a stable output voltage. At the same time, it can completely shut off the current of the reference module, thereby effectively reducing the power consumption of the DC-DC system under light load and no-load conditions. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of the circuit structure of the low-power DC-DC system based on the V2COT architecture of the present invention; Figure 2 This is a schematic diagram of the voltage refresh timing circuit structure in the low-power DC-DC system based on the V2COT architecture of the present invention. Figure 3 This is a specific switching timing diagram of the control method corresponding to the low-power DC-DC system based on the V2COT architecture of the present invention. Detailed Implementation

[0011] To better understand the technical content of this invention, the following embodiments are provided for detailed explanation.

[0012] Please see Figure 1 The diagram shown is a schematic of the circuit structure of the low-power DC-DC system based on the V2COT architecture of the present invention.

[0013] In one implementation, the low-power DC-DC system based on the V2COT architecture includes: an operational amplifier Av, a reference module BG, a comparator Fm1, and a low-power mode comparator Fm2.

[0014] Operational amplifier Av serves as the first stage of the V2COT architecture, with its input connected to the feedback voltage FB and the reference voltage V. REF4 Its output provides V EC The signal, a constant current source, is transmitted through switch S. EA Connect the enable pin of op-amp Av; op-amp Av is used to amplify the feedback voltage FB and the reference voltage V. REF4 The difference; The reference module BG provides the reference voltage V via switch S3. REF4 Reference voltage V REF4 Connect one end of capacitor C0, and ground the other end of capacitor C0; Comparator Fm1 and low-power mode comparator Fm2 serve as the second stage of the V2COT architecture. The feedback voltage FB is connected to one input terminal of comparator Fm1 and low-power mode comparator Fm2 respectively via switches S5 and S7; the V EC The signal first passes through switch S4, then through switches S6 and S8 respectively, and is connected to the other input terminals of comparator Fm1 and low-power mode comparator Fm2. EC The signal is also connected to one end of capacitor C1 via switch S4, and the other end of capacitor C1 is grounded; capacitor C1 is a pF-level capacitor, which can improve the accuracy of DC voltage regulation; The comparator Fm1 outputs a PWM_OUT1 signal, which controls the conduction of the upper power transistor in the power stage of the DC-DC system. The PWM_OUT1 signal is grounded through switch S9. The power stage also includes a lower power transistor, an inductor, an output capacitor, and voltage divider resistors, with the feedback voltage FB provided between the voltage divider resistors. The output of the low-power mode comparator Fm2 is a PWM_OUT2 signal, which is connected to the low-power mode determination logic unit PS LOGIC. This PWM_OUT2 signal is transmitted through switch S. 10 Grounded; the input of the low-power mode judgment logic unit PS LOGIC is also connected to a light load detection signal; the light load detection generates the light load detection signal after determining that the load of the switching power supply is lower than a preset value, and the low-power mode judgment logic unit PS LOGIC generates a low-power mode enable signal, the PS signal output goes high, and the system enters the low-power mode from the normal mode; when the low-power mode judgment logic unit PS LOGIC receives the PWM_OUT2 signal, the PS signal output goes low, and the system exits the low-power mode; In normal mode, it is controlled by the aforementioned PS signal, such as Figure 3 As shown, with switches S7 and S8 open, the low-power mode comparator Fm2 is not working, and switch S9 is also open. EAS3, S4, S5, S6 and S 10 Conduction; After entering low-power mode, it is controlled by the aforementioned PS signal, such as Figure 3 As shown, switch S3 is disconnected, and the reference voltage V REF4 The energy is stored in capacitor C0; then switches S5 and S6 are opened, comparator Fm1 is not working; switches S7 and S8 are turned on to enable the low-power mode comparator Fm2, switching the second-stage comparator; then switch S4 is opened, and the V... EC The signal is stored in capacitor C1 and continues to serve as the input to comparator Fm1, after which switch S is opened. EA The first-stage op-amp Av does not consume current; then, switch S9 turns on, pulling the PWM_OUT1 signal low, and switch S... 10 Disconnecting the output of the low-power mode comparator Fm2 enables it. At this time, the low-power mode comparator Fm2 continues to monitor the feedback voltage FB. When the low-power mode comparator Fm2 determines that the feedback voltage FB is lower than V... EC When the signal is low, the PWM_OUT2 signal is output, and when the PS signal goes low, the low-power mode is exited.

[0015] In a preferred embodiment, the constant current source is controlled by switch S. BG Connecting the aforementioned reference module BG, in the aforementioned normal mode, the switch S BG The switch S is turned on; after entering low-power mode, the switch S... BG When disconnected, the reference module BG does not consume current.

[0016] In a further preferred embodiment, the low-power DC-DC system based on the V2COT architecture also includes a voltage refresh timing circuit. For example... Figure 2 As shown, the voltage refresh timing circuit includes several voltage divider resistors R1, R2, R3...R connected in series between the reference output VREF1 of the reference module BG and ground. n It also includes the voltage refresh comparator COMP and the refresh logic unit RESET LOGIC; The voltage divider resistors R1, R2, R3...R n A voltage divider output terminal is provided between the two terminals, and one of the voltage divider output terminals provides a reference voltage V. REF4 Voltage divider resistor R n-2 With voltage divider resistor R n-1 The voltage divider output terminal between the two terminals supplies voltage V to one input terminal of the voltage refresh comparator COMP via switch S1. REF3 The voltage V REF3 Sampling capacitor C3 is connected to ground; resistor R n-1 With voltage divider resistor R nThe voltage divider output terminal between the two terminals supplies voltage V to the other input terminal of the voltage refresh comparator COMP via switch S2. REF2 The voltage V REF2 A sampling capacitor C2 is connected to ground; the capacitance value of the sampling capacitor C3 is greater than the capacitance value of the sampling capacitor C2. The output of the voltage refresh comparator COMP is connected to the refresh logic unit RESET LOGIC, and the output of the refresh logic unit RESET LOGIC provides the output RESET signal of the voltage refresh timing circuit. After entering the low-power mode, the refresh logic unit RESET LOGIC outputs a RESET signal, entering refresh mode. At this time, switch S... BG When activated, the reference module BG establishes various reference potentials, and the switch S... EA The circuit is activated, establishing the first-stage operational amplifier's potential Av. After a period of time, once all potentials are established, switch S3 opens, providing the reference voltage V. REF4 When switch S4 at the output terminal of op-amp Av is turned on, the output V is turned on. EC The low-power mode comparator Fm2 adds a current channel to accelerate the detection speed; after a delay, once the output stabilizes, it exits the refresh mode and enters the low-power mode.

[0017] In a more preferred embodiment, the PWM_OUT1 signal is connected to the input terminal of the constant on-time module ON TIMER, and the output terminal of the constant on-time module ON TIMER outputs a fixed pulse width signal TON to control the on-time of the upper power transistor, which is used to determine the moment when the upper power transistor is turned off.

[0018] In the practical application of this invention, during normal operation, switches S7, S8, and S9 are open, the low-power mode comparator Fm2 does not work, the other switches are open, and the other modules are all working.

[0019] After entering low-power mode under light load detection, the output PS signal goes high. At this time, switch S3 is disconnected, and V... REF4 The voltage is stored in capacitor C0, and switch S is opened. BG This prevents the reference module from consuming current; then, switches S5 and S6 are opened to disable comparator Fm1, and switches S7 and S8 are opened to enable low-power mode comparator Fm2; after switching the second-stage comparator, S4 is opened, V EC The energy stored in capacitor C1 continues to serve as the input to the low-power mode comparator Fm2, and then switch S... EA When disconnected, the first-stage op-amp Av consumes no current; then, switch S9 turns on, pulling the PWM_OUT1 signal low, invalidating the comparator Fm1 output, and switch S... 10Disconnecting the output of the low-power mode comparator Fm2 makes it valid. At this point, the low-power mode comparator Fm2 continues to monitor the feedback voltage FB.

[0020] In low-power mode, comparator Fm2 determines that the feedback voltage FB is lower than V. EC After the signal, the PWM_OUT2 signal is output to exit low-power mode, and the PS signal goes low. This completely shuts off the reference current and the main op-amp Av current in low-power mode. At this point, only the low-power mode comparator Fm2 is working, reducing overall power consumption. However, for the V2COT architecture, this might result in the reference voltage and V... EC Voltage stability issues may lead to problems such as capacitor leakage causing incorrect output results after a long period of time.

[0021] To address this issue, in practical applications, the DC-DC system of this invention may further include a reference voltage / operational amplifier refresh circuit and voltage refresh timing logic.

[0022] like Figure 1 As shown, after entering low-power mode, the timing logic outputs a RESET signal, entering refresh mode. At this time, switch S... BG Turn on, establish reference potentials, switch S EA The system is activated, establishing the first-stage operational amplifier's Av potential. Fm2 receives an additional current, accelerating the detection speed. After a period of time, once all potentials are established, the sampling switch S3 of the reference module BG opens, supplying current to V. REF4 With power supplied, switch S4 at the Av output terminal is open, providing accurate V output. EC The signal is then processed. After a delay and once the output stabilizes, the system exits refresh mode and enters low-power mode. In refresh mode, the current consumed includes the reference module BG, the first-stage operational amplifier Av, and the second-stage comparator Fm2.

[0023] like Figure 2 As shown, traditional timers rely on bias current for timing, and manufacturing variations in numerous components can lead to significant deviations in the final timing output. The timing structure employed in this invention utilizes the sampling voltage network of a reference module, generating a timing signal through inconsistencies in capacitor values. Upon entering low-power mode, switches S1 and S2 are both open, and the voltage V... REF3 and voltage V REF2 They are stored in capacitors C2 and C3, respectively. The voltage V... REF3 The capacitance value of capacitor C3 is larger than that of capacitor C2. In low-power mode, it presents a voltage V. REF3 Relative to voltage V REF2 The rate of decrease is faster when the voltage V REF3 Below voltage V REF2When the refresh comparator COMP outputs a high value, a RESET signal is output through RESET LOGIC. The advantage of this timing method is that it determines the timing time using only a capacitor, and it has a mirror relationship with the leakage current of the feedback voltage FB, which can better correspond to the power loss of both. Moreover, it does not require an additional bias current for timing, thus reducing power consumption.

[0024] It should be noted that the refresh signal RESET may only go high after entering low power mode. In low power mode, the comparator Fm2 outputs the PWM_OUT2 signal, which does not determine the turn-on of the upper power transistor in the power stage. Its function is only to exit low power mode. The turn-on of the upper power transistor is determined by the PWM_OUT1 signal output by the comparator Fm1.

[0025] The low-power DC-DC system based on the V2COT architecture of this invention includes an operational amplifier Av as the first stage of the V2COT architecture, a comparator Fm1 as the second stage of the V2COT architecture, and a low-power mode comparator Fm2. After detecting a light load state, the system switches from normal mode to low-power mode. After entering the low-power mode, the first-stage operational amplifier Av does not consume current, and the second stage switches from comparator Fm1 to low-power mode comparator Fm2, reducing the comparator current. Furthermore, the voltage refresh timing circuit is used to enter refresh mode after entering the low-power mode to refresh the output voltage of the reference module and the output voltage of the operational amplifier to provide a stable output voltage, thereby effectively reducing the power consumption of the DC-DC system under light load and no-load conditions.

[0026] In this specification, the invention has been described with reference to specific embodiments thereof. However, it will be apparent that various modifications and variations can be made without departing from the spirit and scope of the invention. Therefore, the specification and drawings should be considered illustrative rather than restrictive.

Claims

1. A low-power DC-DC system based on V2COT architecture, characterized in that, include: Operational amplifier Av, as the first stage of the V2COT architecture, has its input connected to the feedback voltage FB and the reference voltage V. REF4 Its output provides V EC The signal, a constant current source, is transmitted through switch S. EA Connect the enable pin of the op-amp Av; The reference module BG provides the reference voltage V via switch S3. REF4 Reference voltage V REF4 Connect one end of capacitor C0, and ground the other end of capacitor C0; Comparator Fm1 and low-power mode comparator Fm2, as the second stage of the V2COT architecture, have their feedback voltage FB connected to one input terminal of comparator Fm1 and low-power mode comparator Fm2 respectively via switches S5 and S7; the V EC The signal first passes through switch S4, then through switches S6 and S8 respectively, and is connected to the other input terminals of comparator Fm1 and low-power mode comparator Fm2. EC The signal is also connected to one end of capacitor C1 via switch S4, and the other end of capacitor C1 is grounded; The comparator Fm1 outputs a PWM_OUT1 signal, which controls the conduction of the upper power transistor in the power stage of the DC-DC system. The PWM_OUT1 signal is grounded through switch S9. The power stage also includes a lower power transistor, an inductor, an output capacitor, and voltage divider resistors, with the feedback voltage FB provided between the voltage divider resistors. The output of the low-power mode comparator Fm2 is a PWM_OUT2 signal, which is connected to the low-power mode determination logic unit PSLOGIC. This PWM_OUT2 signal is transmitted through switch S. 10 Grounded; the input of the low-power mode judgment logic unit PS LOGIC is also connected to a light load detection signal; the light load detection generates the light load detection signal after determining that the load of the switching power supply is lower than a preset value, and the low-power mode judgment logic unit PS LOGIC generates a low-power mode enable signal, the PS signal output goes high, and the system enters the low-power mode from the normal mode; when the low-power mode judgment logic unit PS LOGIC receives the PWM_OUT2 signal, the PS signal output goes low, and the system exits the low-power mode; In normal mode, controlled by the PS signal, switches S7 and S8 are open, the low-power mode comparator Fm2 is not working, switch S9 is also open, and switch S... EA S3, S4, S5, S6 and S 10 Conduction; After entering low-power mode, under the control of the PS signal, switch S3 is disconnected, and the reference voltage V... REF4 The energy is stored in capacitor C0; then switches S5 and S6 are opened, comparator Fm1 is not working; switches S7 and S8 are turned on to enable the low-power mode comparator Fm2, switching the second-stage comparator; then switch S4 is opened, and the V... EC The signal is stored in capacitor C1 and continues to serve as the input to comparator Fm1, after which switch S is opened. EA The first-stage op-amp Av does not consume current; then, switch S9 turns on, pulling the PWM_OUT1 signal low, and switch S... 10 Disconnecting the output of the low-power mode comparator Fm2 enables it. At this time, the low-power mode comparator Fm2 continues to monitor the feedback voltage FB. When the low-power mode comparator Fm2 determines that the feedback voltage FB is lower than V... EC When the signal is low, the PWM_OUT2 signal is output, and when the PS signal goes low, the low-power mode is exited.

2. The low-power DC-DC system based on V2COT architecture according to claim 1, characterized in that, The constant current source is connected to switch S BG Connecting the aforementioned reference module BG, in the aforementioned normal mode, the switch S BG The switch S is turned on; after entering low-power mode, the switch S... BG When disconnected, the reference module BG does not consume current.

3. The low-power DC-DC system based on V2COT architecture according to claim 2, characterized in that, It also includes a voltage refresh timing circuit. The voltage refresh timing circuit includes several voltage divider resistors R1, R2, R3...R connected in series between the reference output VREF1 of the reference module BG and ground. n It also includes the voltage refresh comparator COMP and the refresh logic unit RESETLOGIC. The voltage divider resistors R1, R2, R3...R n A voltage divider output terminal is provided between the two terminals, and one of the voltage divider output terminals provides a reference voltage V. REF4 Voltage divider resistor R n-2 With voltage divider resistor R n-1 The voltage divider output terminal between the two terminals supplies voltage V to one input terminal of the voltage refresh comparator COMP via switch S1. REF3 The voltage V REF3 Sampling capacitor C3 is connected to ground; resistor R n-1 With voltage divider resistor R n The voltage divider output terminal between the two terminals supplies voltage V to the other input terminal of the voltage refresh comparator COMP via switch S2. REF2 The voltage V REF2 A sampling capacitor C2 is connected to ground; the capacitance value of the sampling capacitor C3 is greater than the capacitance value of the sampling capacitor C2. The output of the voltage refresh comparator COMP is connected to the refresh logic unit RESET LOGIC, and the output of the refresh logic unit RESET LOGIC provides the output RESET signal of the voltage refresh timing circuit. After entering the low-power mode, the refresh logic unit RESET LOGIC outputs a RESET signal, entering refresh mode. At this time, switch S... BG When activated, the reference module BG establishes various reference potentials, and the switch S... EA The circuit is activated, establishing the first-stage operational amplifier's potential Av. After a period of time, once all potentials are established, switch S3 opens, providing the reference voltage V. REF4 When switch S4 at the output terminal of op-amp Av is turned on, the output V is turned on. EC The low-power mode comparator Fm2 adds a current channel to accelerate the detection speed; after a delay, once the output stabilizes, it exits the refresh mode and enters the low-power mode.

4. The low-power DC-DC system based on V2COT architecture according to claim 3, characterized in that, The PWM_OUT1 signal is connected to the input terminal of the constant on-time module ONTIMER. The output terminal of the constant on-time module ONTIMER outputs a fixed pulse width signal TON to control the on-time of the upper power transistor, which is used to determine the moment when the upper power transistor is turned off.

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