Low-dropout linear voltage stabilizing circuit, low-dropout linear voltage stabilizer, power supply device, and electronic device

Abstract

The application belongs to the technical field of electronic circuits and provides a low-dropout linear voltage stabilizing circuit, a low-dropout linear voltage stabilizer, a power supply device and an electronic device. The low-dropout linear voltage stabilizing circuit comprises a biasing module, an input module, an intermediate stage module, an output module, a first compensation module and a second compensation module. The intermediate stage module is connected with the input module, the output module, the first compensation module, the second compensation module and the biasing module. The output module is connected with the input module, the first compensation module and a load. The input module is connected with the biasing module. The first compensation module generates a first zero point that is positively correlated with the load current and is irrelevant to the output voltage. The first zero point increases with the increase of the load current and decreases with the decrease of the load current, and is not affected by the output voltage. Thus, the tracking compensation of the load current is realized, and the purpose of keeping the tracking compensation effect unchanged with the output voltage is achieved.

Description

Technical Field

[0001] This application belongs to the field of electronic circuit technology, and particularly relates to a low dropout linear regulator circuit, a low dropout linear regulator, a power supply device, and an electronic device. Background Technology

[0002] In many systems with strict requirements on power supply ripple, one or more LDO (Low-Dropout Regulator) units are typically configured to provide a regulated power supply with very low ripple and relatively clean operation. The stability of the LDO regulated power supply is crucial, and there are many compensation methods for this. One such method is load current tracking compensation technology. The core idea of ​​this technology is to dynamically adjust the position of the compensation zero point based on the magnitude of the LDO's output load current, allowing it to track and compensate for the LDO's output poles, thereby achieving stable system operation.

[0003] However, implementing load current tracking compensation technology in NMOS (N-channel Metal-Oxide-Semiconductor Field-Effect Transistor) LDOs is quite difficult. This is because for an NMOS LDO, the load condition is often reflected by the gate voltage of the power transistor. However, the gate voltage depends not only on the load current but also on the output voltage. A higher load current results in a higher gate voltage, and similarly, a higher output voltage leads to a higher gate voltage. Traditional solutions often only track the load current, neglecting the system stability degradation caused by output voltage changes. This can lead to an unstable or critically stable LDO system, severely impacting the performance of subsequent circuits. Therefore, this problem urgently needs improvement. Summary of the Invention

[0004] This application provides a low-dropout linear regulator circuit, a low-dropout linear regulator, a power supply device, and an electronic device, which can solve the problem that traditional solutions often only track the load current but ignore the system stability degradation caused by output voltage changes.

[0005] In a first aspect, embodiments of this application provide a low-dropout linear regulator circuit, including a bias module, an input module, an intermediate stage module, an output module, a first compensation module, and a second compensation module. The intermediate stage module is connected to the input module, the output module, the first compensation module, the second compensation module, and the bias module, respectively. The output module is connected to the input module, the first compensation module, and the load, respectively. The input module is connected to the bias module.

[0006] The bias module provides a first bias current and a second bias current; the input module outputs a first voltage signal based on a reference voltage, a feedback voltage, and the first bias current, generating a first pole at the common terminal of the input module and the intermediate stage module; the intermediate stage module outputs a second voltage signal based on the second bias current and the first voltage signal; the output module outputs the feedback voltage and the output voltage based on the second voltage signal, generating a second pole at the common terminal of the intermediate stage module and the output module, and a third pole at the common terminal of the output module and the load; the first compensation module generates a first zero that is positively correlated with the load current and independent of the output voltage to compensate for the third pole; the second compensation module generates a second zero to compensate for the first pole.

[0007] In one possible implementation of the first aspect, the first compensation module includes a first resistor, a second resistor, a first current source, a first capacitor, and a first transistor. The first terminal of the first resistor is connected to the output module and the load, respectively. The second terminal of the first resistor is connected to the first terminal of the second resistor and the gate of the first transistor, respectively. The second terminal of the second resistor is connected to the first terminal of the first current source, and the second terminal of the first current source is grounded. The drain of the first transistor is connected to the first terminal of the first capacitor, and the second terminal of the first capacitor is connected to the second compensation module, the input module, and the intermediate stage module, respectively. The source of the first transistor is connected to the second compensation module, the intermediate stage module, the bias module, and the output module, respectively.

[0008] In one possible implementation of the first aspect, the second compensation module includes a third resistor and a second capacitor. The first end of the third resistor is connected to the input module, the first compensation module, and the intermediate stage module, respectively. The second end of the third resistor is connected to the first end of the second capacitor, and the second end of the second capacitor is connected to the first compensation module, the intermediate stage module, the bias module, and the output module, respectively.

[0009] In one possible implementation of the first aspect, the bias module includes a second transistor, a third transistor, a fourth transistor, and a second current source. The gate of the second transistor receives a bias voltage and is connected to the drain of the second transistor, a first terminal of the second current source, and the gate of the third transistor, respectively. The gate of the fourth transistor receives a bias voltage. The second terminal of the second current source is grounded. The sources of the second transistor, the third transistor, and the fourth transistor receive a power supply voltage. The drain of the third transistor is connected to the input module. The drain of the fourth transistor is connected to the intermediate stage module, the first compensation module, the second compensation module, and the output module, respectively.

[0010] In one possible implementation of the first aspect, the input module includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. The gate of the fifth transistor receives a feedback voltage. The source of the fifth transistor is connected to the source of the sixth transistor and the bias module. The drain of the fifth transistor is connected to the drain of the seventh transistor, the gate of the seventh transistor, and the gate of the eighth transistor. The sources of the seventh transistor and the eighth transistor are grounded. The gate of the sixth transistor is used to receive a reference voltage. The drain of the sixth transistor is connected to the first compensation module, the second compensation module, the intermediate stage module, and the drain of the eighth transistor.

[0011] In one possible implementation of the first aspect, the intermediate stage module includes a ninth transistor, the gate of which is connected to the input module, the first compensation module, and the second compensation module, respectively; the source of which is grounded; and the drain of which is connected to the first compensation module, the second compensation module, the output module, and the bias module, respectively.

[0012] In one possible implementation of the first aspect, the output module includes a tenth transistor, a fourth resistor, a fifth resistor, and a third capacitor. The drain of the tenth transistor receives a power supply voltage. The gate of the tenth transistor is connected to the bias module, the intermediate stage module, the first compensation module, and the second compensation module, respectively. The source of the tenth transistor is connected to the first terminal of the fifth resistor, the first terminal of the third capacitor, the first compensation module, and the load, respectively. The second terminal of the fifth resistor is connected to the first terminal of the fourth resistor and the input module, respectively. The second terminal of the fourth resistor and the second terminal of the third capacitor are grounded.

[0013] Secondly, embodiments of this application provide a low-dropout linear regulator, including the low-dropout linear regulator circuit described in any one of the first aspects.

[0014] Thirdly, embodiments of this application provide a power supply device including the low-dropout linear regulator described in any one of the second aspects.

[0015] Fourthly, embodiments of this application provide an electronic device including the power supply device described in any one of the third aspects.

[0016] The beneficial effects of the embodiments in this application compared with the prior art are:

[0017] This application provides a low dropout linear regulator circuit, including a bias module, an input module, an intermediate stage module, an output module, a first compensation module, and a second compensation module. The intermediate stage module is connected to the input module, the output module, the first compensation module, the second compensation module, and the bias module, respectively. The output module is connected to the input module, the first compensation module, and the load, respectively. The input module is connected to the bias module.

[0018] The bias module provides a first bias current and a second bias current. The input module outputs a first voltage signal based on the reference voltage, feedback voltage, and first bias current, generating a first pole at the common terminal of the input module and the intermediate stage module. The intermediate stage module outputs a second voltage signal based on the second bias current and the first voltage signal. The output module outputs a feedback voltage and an output voltage based on the second voltage signal, generating a second pole at the common terminal of the intermediate stage module and the output module, and a third pole at the common terminal of the output module and the load. The first compensation module generates a first zero that is positively correlated with the load current and independent of the output voltage to compensate for the third pole. The second compensation module generates a second zero to compensate for the first pole.

[0019] This application generates a first zero point that is positively correlated with the load current and independent of the output voltage through a first compensation module. That is, the first zero point rises as the load current increases and falls as the load current decreases, and is unaffected by the output voltage. This achieves tracking compensation of the load current and ensures that the tracking compensation effect does not change with the output voltage. Therefore, the low-dropout linear regulator circuit provided in this application solves the problem that traditional solutions often only track the load current but ignore the system stability degradation caused by changes in output voltage.

[0020] It is understood that the beneficial effects of the second to fourth aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a circuit connection diagram of a low-dropout linear regulator circuit based on traditional load current tracking compensation technology;

[0023] Figure 2 This is a schematic diagram of a low dropout linear regulator circuit provided in an embodiment of this application;

[0024] Figure 3 This is a circuit connection diagram of a low dropout linear regulator circuit provided in an embodiment of this application.

[0025] In the diagram: 10. Low dropout linear regulator circuit; 101. Bias module; 102. Input module; 103. Intermediate stage module; 104. Output module; 105. First compensation module; 106. Second compensation module; 20. Load. Detailed Implementation

[0026] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0027] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0028] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0029] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0030] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0031] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0032] Figure 1 The circuit connection diagram of a low-dropout linear regulator (LDO) circuit based on traditional load current tracking compensation technology is shown. This is a three-stage LDO circuit with three poles, therefore requiring two zero-point compensations to achieve stable operation. The sixth resistor R6 and the sixth capacitor C4 form a fixed zero point. Another dynamic zero point that can track the load current is generated by a compensation circuit consisting of the seventh resistor R7, the fifth capacitor C5, and the NM8 transistor. , where R on_n8 This represents the channel impedance of the NM8 transistor. When the load current of the LDO circuit increases, its output pole will become higher, and the gate voltage of the NM9 transistor will increase (i.e., the voltage at node A1 will increase). Since the source voltage of the NM8 transistor (i.e., the voltage at node A2) changes very little (approximately the threshold voltage of the NM7 transistor), the voltage difference between the gate and source of the NM8 transistor is... V gs_n8 It will increase, thus increasing the channel impedance R of the NM8 transistor. on_n8As the voltage decreases, the dynamic zero Z12 increases, thus perfectly tracking the output pole as it increases. Similarly, if the load current of the LDO circuit decreases, the dynamic zero Z12 will track the output pole as it decreases, achieving zero-pole compensation and stabilizing the system. However, this approach has a fatal flaw: because the voltage at node A1... , VOUT It is the output voltage of the LDO circuit. V gs_n9 It is the voltage difference between the gate and source of the NM9 transistor. Therefore, the voltage at node A1 and the load current are not in a one-to-one correspondence (while...). V gs_n9 It has a positive correlation with the load current, and both change in the same trend, that is, a lower output voltage with a large load current. VOUT With a higher output voltage and a small load current VOUT Possibly corresponding to the same voltage V A1 In this case, this method will cause load tracing to fail, ultimately leading to system instability.

[0033] To address the aforementioned problems, this application proposes a low-dropout linear regulator circuit, including a bias module, an input module, an intermediate stage module, an output module, a first compensation module, and a second compensation module. The intermediate stage module is connected to the input module, output module, first compensation module, second compensation module, and bias module, respectively. The output module is connected to the input module, first compensation module, and load, respectively. The input module is connected to the bias module. This application generates a first zero point (used to compensate the output pole of the low-dropout linear regulator circuit) that is positively correlated with the load current and independent of the output voltage through the first compensation module—that is, the first zero point rises as the load current increases and falls as the load current decreases, unaffected by the output voltage; thus achieving tracking compensation of the load current and ensuring that the tracking compensation effect does not change with the output voltage. Therefore, the low-dropout linear regulator circuit provided by this application solves the problem that traditional solutions often only track the load current but ignore the system stability degradation caused by changes in output voltage.

[0034] To illustrate the technical solution described in this application, specific embodiments are provided below.

[0035] Figure 2 A schematic diagram of the low-dropout linear regulator circuit provided in this application is shown. Figure 2As shown, the low dropout linear regulator circuit 10 includes a bias module 101, an input module 102, an intermediate stage module 103, an output module 104, a first compensation module 105, and a second compensation module 106. The intermediate stage module 103 is connected to the input module 102, the output module 104, the first compensation module 105, the second compensation module 106, and the bias module 101, respectively. The output module 104 is connected to the input module 102, the first compensation module 105, and the load 20, respectively. The input module 102 is connected to the bias module 101.

[0036] Specifically, bias module 101 is used to provide a first bias current and a second bias current. Input module 102 is used to input current based on a reference voltage. VREF Feedback voltage VFB The first bias current and the first voltage signal are used to generate a first pole at the common terminal of the input module 102 and the intermediate stage module 103. The intermediate stage module 103 is used to output a second voltage signal based on the second bias current and the first voltage signal. The output module 104 is used to output a feedback voltage based on the second voltage signal. VFB and output voltage VOUT A second pole is generated at the common terminal of the intermediate stage module 103 and the output module 104, and a third pole (i.e., the output pole) is generated at the common terminal of the output module 104 and the load 20. The first compensation module 105 is used to generate a value that is positively correlated with the load current and the output voltage. VOUT An irrelevant first zero point is used to compensate for the third pole. A second compensation module 106 is used to generate a second zero point to compensate for the first pole. In this embodiment, the reference voltage... VREF Provided by a reference source or an external chip 。 It should be noted that the load current is related to the load 20. The heavier the load 20, the greater the load current; the lighter the load 20, the smaller the load current.

[0037] This application generates a value that is positively correlated with the load current and the output voltage through the first compensation module 105. VOUT The first zero point is independent – ​​that is, the first zero point rises with increasing load current and falls with decreasing load current, and is unaffected by output voltage. VOUT This mitigates the impact of load current tracking and compensation, ensuring that the tracking compensation effect remains independent of the output voltage. VOUT The purpose of the change. Therefore, the low-dropout linear regulator circuit 10 provided in this application embodiment solves the problem that traditional solutions often only track the load current but ignore the output voltage. VOUT The problem of system instability caused by changes.

[0038] In one embodiment of this application, such as Figure 3As shown, the bias module 101 includes a second transistor M2, a third transistor M3, a fourth transistor M4, and a second current source Ib2. The gate of the second transistor M2 receives the bias voltage. VBP It is connected to the drain of the second transistor M2, the first terminal of the second current source Ib2, and the gate of the third transistor M3, respectively. The gate of the fourth transistor M4 receives the bias voltage. VBP The second terminal of the second current source Ib2 is grounded, and the sources of the second transistor M2, the third transistor M3, and the fourth transistor M4 receive the power supply voltage. VDD The drain of the third transistor M3 is connected to the input module 102, and the drain of the fourth transistor M4 is connected to the intermediate stage module 103, the first compensation module 105, the second compensation module 106, and the output module 104, respectively. In this embodiment, the second transistor M2, the third transistor M3, and the fourth transistor M4 are all PMOS transistors.

[0039] Specifically, the bias module 101 provides a first bias current and a second bias current. The current supplied by the second current source Ib2 is mirrored (the second transistor M2, the third transistor M3, and the fourth transistor M4 each form a current mirror structure), generating the first bias current in the branch containing the third transistor M3 and the second bias current in the branch containing the fourth transistor M4. The first bias current provides a stable operating current for the input module 102, and the second bias current provides a stable operating current for the intermediate stage module 103.

[0040] In one embodiment of this application, such as Figure 3 As shown, the input module 102 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8. The gate of the fifth transistor M5 receives the feedback voltage. VFB The source of the fifth transistor M5 is connected to the source of the sixth transistor M6 and the drain of the bias module 101 (i.e., the drain of the third transistor M3). The drain of the fifth transistor M5 is connected to the drain of the seventh transistor M7, the gate of the seventh transistor M7, and the gate of the eighth transistor M8. The sources of the seventh transistor M7 and the eighth transistor M8 are grounded. The gate of the sixth transistor M6 is used to receive the reference voltage. VREF The drain of the sixth transistor M6 is connected to the drains of the first compensation module 105, the second compensation module 106, the intermediate stage module 103, and the eighth transistor M8, respectively. In this embodiment, the fifth transistor M5 and the sixth transistor M6 are both PMOS transistors; the seventh transistor M7 and the eighth transistor M8 are both NMOS transistors.

[0041] Specifically, the input transistor pair (i.e., the fifth transistor M5 and the sixth transistor M6) will, under the action of the first bias current, feed back the voltage. VFBWith reference voltage VREF Voltage difference Δ between VFB This is converted into a corresponding small-signal current; when this small-signal current flows through the load impedance of the branch where the eighth transistor M8 is located, a small-signal voltage is generated across the impedance, which is the first voltage signal. It is important to note that the first voltage signal is related to Δ... VFB There is a certain multiple relationship between them.

[0042] In one embodiment of this application, such as Figure 3 As shown, the intermediate stage module 103 includes a ninth transistor M9. The gate of the ninth transistor M9 is connected to the input module 102 (i.e., the drain of the sixth transistor M6), the first compensation module 105, and the second compensation module 106, respectively. The source of the ninth transistor M9 is grounded, and the drain of the ninth transistor M9 is connected to the first compensation module 105, the second compensation module 106, the output module 104, and the bias module 101 (i.e., the drain of the fourth transistor M4), respectively. In this embodiment, the ninth transistor M9 is an NMOS transistor.

[0043] Specifically, under the action of the second bias current, the ninth transistor M9 outputs a second voltage signal to the output module 104 according to the first voltage signal. It should be noted that there is a certain multiple relationship between the second voltage signal and the first voltage signal.

[0044] In one embodiment of this application, such as Figure 3 As shown, the output module 104 includes a tenth transistor M10, a fourth resistor R4, a fifth resistor R5, and a third capacitor C3. The drain of the tenth transistor M10 receives the power supply voltage. VDD The gate of the tenth transistor M10 is connected to the bias module 101 (i.e., the drain of the fourth transistor M4), the intermediate stage module 103 (i.e., the drain of the ninth transistor M9), the first compensation module 105, and the second compensation module 106. The source of the tenth transistor M10 is connected to the first terminal of the fifth resistor R5, the first terminal of the third capacitor C3, the first compensation module 105, and the load 20. The second terminal of the fifth resistor R5 is connected to the first terminal of the fourth resistor R4 and the input module 102 (i.e., the gate of the fifth transistor M5). The second terminals of the fourth resistor R4 and the second terminal of the third capacitor C3 are grounded. In this embodiment, the tenth transistor M10 is an NMOS transistor.

[0045] Specifically, the tenth transistor M10 obtains the final output voltage based on the second voltage signal. VOUT Output voltage VOUT The feedback voltage is obtained after voltage division by the voltage divider network composed of the fifth resistor R5 and the fourth resistor R4. VFB, Feedback voltage VFB Feedback is sent to input module 102, along with the reference voltage. VREFDifferential comparison is performed to form closed-loop negative feedback to stabilize the output voltage. VOUT .

[0046] In one embodiment of this application, such as Figure 3 As shown, the first compensation module 105 includes a first resistor R1, a second resistor R2, a first current source Ib1, a first capacitor C1, and a first transistor M1. The first terminal of the first resistor R1 is connected to the output module 104 (i.e., the source of the tenth transistor M10) and the load 20. The second terminal of the first resistor R1 is connected to the first terminal of the second resistor R2 and the gate of the first transistor M1. The second terminal of the second resistor R2 is connected to the first terminal of the first current source Ib1, and the second terminal of the first current source Ib1 is grounded. The first transistor... The drain of transistor M1 is connected to the first terminal of the first capacitor C1. The second terminal of the first capacitor C1 is connected to the second compensation module 106, the input module 102 (i.e., the drain of the sixth transistor M6), and the intermediate stage module 103 (i.e., the gate of the ninth transistor M9), respectively. The source of the first transistor M1 is connected to the second compensation module 106, the intermediate stage module 103 (i.e., the drain of the ninth transistor M9), the bias module 101 (i.e., the drain of the fourth transistor M4), and the output module 104 (i.e., the gate of the tenth transistor M10), respectively. In this embodiment, the first transistor M1 is a PMOS transistor.

[0047] The second compensation module 106 includes a third resistor R3 and a second capacitor C2. The first end of the third resistor R3 is connected to the input module 102 (i.e., the drain of the sixth transistor M6), the first compensation module 105 (i.e., the second end of the first capacitor C1), and the intermediate stage module 103 (i.e., the gate of the ninth transistor M9), respectively. The second end of the third resistor R3 is connected to the first end of the second capacitor C2. The second end of the second capacitor C2 is connected to the first compensation module 105 (i.e., the source of the first transistor M1), the intermediate stage module 103 (i.e., the drain of the ninth transistor M9), the bias module 101 (i.e., the drain of the fourth transistor M4), and the output module 104 (i.e., the gate of the tenth transistor M10), respectively.

[0048] Specifically, the low-dropout linear regulator circuit 10 provided in this application has three poles: the first pole is located at node B1, the second pole is located at node B2, and the third pole (i.e., the output pole) is located at node B3. P The expression for 3 is approximately: , where R out R is the equivalent output impedance of the low-dropout linear regulator circuit 10. As the load current increases, R... out The smaller the value of R, the smaller the load current. out The larger the value, the more likely it is to be stable. Traditional theory dictates that at least two zeros are required for a circuit to remain stable.

[0049] Figure 3 The function of the third resistor R3 and the second capacitor C2 is to form a fixed second zero point. This is used to compensate for the first pole. It tracks the first zero point of the load current. , where R on_M1 Let M1 be the channel impedance of the first transistor. The voltage expression at node B4 is: According to this expression, we can know that: V B4 Automatically tracks output voltage VOUT Regardless of output voltage VOUT No matter how things change, it can always be guaranteed. V B4 Compared to output voltage VOUT Small Ib 1. R1. The voltage expression at node B2 is: V gs_M10 Let be the voltage difference between the gate and source of the tenth transistor M10. Therefore, the voltage difference between the gate and source of the first transistor M1 is . ,

[0050] From the expression, we can see that V gs_M1 With output voltage VOUT Irrelevant, and Ib 1. R1 can be a fixed value through proper design, that is V gs_M1 Will follow V gs_M10 Changes in the same direction.

[0051] According to the formula for current ,in μ Surface mobility of semiconductor devices c Gate oxide capacitance per unit area of ​​a semiconductor device. V represents the aspect ratio of the tenth transistor M10. th_M10 This is the threshold voltage of the tenth transistor M10. I o Given the load current, we can derive the value when the load current is... I o When V increases gs_M10 It will also increase.

[0052] In conclusion, it can be concluded that V gs_M1 It will follow the load current I o It changes with the load current. I o When it gets bigger, V gs_M1 It will follow the load current I oThe drain current of the first transistor M1 increases together with the drain current of the transistor. ,in The aspect ratio of the first transistor M1 is... V th_M1 The threshold voltage of the first transistor M1; the channel impedance of the first transistor M1. , γ It is a process constant; therefore, it can be derived that when the load current... I o When the value increases, the channel impedance R of the first transistor M1... on_M1 As the value decreases, according to the expression for the first zero point Z1, the first zero point Z1 will increase, meaning the first zero point Z1 will follow the load current. I o (Or the output poles) rise together, similarly when the output load current I o When the current decreases, the first zero point Z1 also decreases, thus achieving both control over the load current and... I o The tracking compensation function also achieves tracking compensation that is independent of output voltage. VOUT The purpose of change.

[0053] In summary, the low dropout linear regulator circuit 10 provided in this application generates a voltage regulation circuit that corresponds to the load current through the first compensation module 105. I o It is positively correlated with the output voltage. VOUT The first zero point Z1 is irrelevant - that is, the first zero point Z1 will change with the load current. I o As the load current increases, the load current also increases. I o It decreases as it decreases, and is unaffected by the output voltage. VOUT The effect; thus realizing the control of load current. I o The tracking compensation was achieved, and the tracking compensation effect was not affected by the output voltage. VOUT The purpose of the change. Therefore, the low-dropout linear regulator circuit 10 provided in this application embodiment solves the problem that traditional solutions often only track the load current. I o However, the output voltage was overlooked. VOUT The problem of system instability caused by changes.

[0054] This application also provides a low-dropout linear regulator, including the low-dropout linear regulator circuit described above. Since the low-dropout linear regulator provided in this application adopts all the technical solutions of all the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be elaborated upon here.

[0055] This application also provides a power supply device, including the low-dropout linear regulator described above. Since the power supply device provided in this application adopts all the technical solutions of all the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be elaborated upon here.

[0056] This application also provides an electronic device, including the power supply device described above. Since the electronic device provided in this application adopts all the technical solutions of all the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be elaborated further here.

[0057] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0058] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A low-dropout linear voltage regulator circuit, characterized in that, It includes a bias module, an input module, an intermediate stage module, an output module, a first compensation module, and a second compensation module. The intermediate stage module is connected to the input module, the output module, the first compensation module, the second compensation module, and the bias module, respectively. The output module is connected to the input module, the first compensation module, and the load, respectively. The input module is connected to the bias module. The bias module is used to provide a first bias current and a second bias current; The input module is used to output a first voltage signal based on the reference voltage, feedback voltage, and the first bias current, and to generate a first pole at the common terminal of the input module and the intermediate stage module; the intermediate stage module is used to output a second voltage signal based on the second bias current and the first voltage signal; the output module is used to output the feedback voltage and the output voltage based on the second voltage signal, and to generate a second pole at the common terminal of the intermediate stage module and the output module, and a third pole at the common terminal of the output module and the load; the first compensation module is used to generate a first zero that is positively correlated with the load current and independent of the output voltage, in order to compensate for the third pole; the second compensation module is used to generate a second zero to compensate for the first pole; The first compensation module includes a first resistor, a second resistor, a first current source, a first capacitor, and a first transistor. The first end of the first resistor is connected to the output module and the load, respectively. The second end of the first resistor is connected to the first end of the second resistor and the gate of the first transistor, respectively. The second end of the second resistor is connected to the first end of the first current source, and the second end of the first current source is grounded. The drain of the first transistor is connected to the first end of the first capacitor, and the second end of the first capacitor is connected to the second compensation module, the input module, and the intermediate stage module, respectively. The source of the first transistor is connected to the second compensation module, the intermediate stage module, the bias module, and the output module, respectively.

2. The low-dropout linear voltage regulator circuit according to claim 1, characterized in that, The second compensation module includes a third resistor and a second capacitor. The first end of the third resistor is connected to the input module, the first compensation module, and the intermediate stage module, respectively. The second end of the third resistor is connected to the first end of the second capacitor, and the second end of the second capacitor is connected to the first compensation module, the intermediate stage module, the bias module, and the output module, respectively.

3. The low-dropout linear voltage regulator circuit according to claim 1, characterized in that, The bias module includes a second transistor, a third transistor, a fourth transistor, and a second current source. The gate of the second transistor receives a bias voltage and is connected to the drain of the second transistor, the first terminal of the second current source, and the gate of the third transistor, respectively. The gate of the fourth transistor receives a bias voltage. The second terminal of the second current source is grounded. The sources of the second transistor, the third transistor, and the fourth transistor receive a power supply voltage. The drain of the third transistor is connected to the input module. The drain of the fourth transistor is connected to the intermediate stage module, the first compensation module, the second compensation module, and the output module, respectively.

4. The low-dropout linear voltage regulator circuit according to claim 1, characterized in that, The input module includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. The gate of the fifth transistor receives a feedback voltage. The source of the fifth transistor is connected to the source of the sixth transistor and the bias module. The drain of the fifth transistor is connected to the drain of the seventh transistor, the gate of the seventh transistor, and the gate of the eighth transistor. The sources of the seventh transistor and the eighth transistor are grounded. The gate of the sixth transistor receives a reference voltage. The drain of the sixth transistor is connected to the first compensation module, the second compensation module, the intermediate stage module, and the drain of the eighth transistor.

5. The low-dropout linear voltage regulator circuit according to claim 1, characterized in that, The intermediate stage module includes a ninth transistor, the gate of which is connected to the input module, the first compensation module, and the second compensation module, respectively. The source of the ninth transistor is grounded, and the drain of the ninth transistor is connected to the first compensation module, the second compensation module, the output module, and the bias module, respectively.

6. The low-dropout linear voltage regulator circuit according to claim 1, characterized in that, The output module includes a tenth transistor, a fourth resistor, a fifth resistor, and a third capacitor. The drain of the tenth transistor receives the power supply voltage. The gate of the tenth transistor is connected to the bias module, the intermediate stage module, the first compensation module, and the second compensation module. The source of the tenth transistor is connected to the first terminal of the fifth resistor, the first terminal of the third capacitor, the first compensation module, and the load. The second terminal of the fifth resistor is connected to the first terminal of the fourth resistor and the input module. The second terminals of the fourth resistor and the third capacitor are grounded.

7. A low-dropout linear voltage regulator, characterized in that, Includes the low dropout linear regulator circuit as described in any one of claims 1-6.

8. A power supply device, characterized in that, Includes the low-dropout linear regulator as described in claim 7.

9. An electronic device, characterized in that, Includes the power supply device as described in claim 8.

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