Dual-frequency adaptive single-ended input rectifier and chip

Abstract

The invention discloses a dual-frequency self-adaptive single-ended input rectifier and a chip. The rectifier comprises an impedance matching circuit, and a starting circuit and a rectifying circuit which are coupled with the impedance matching circuit, the impedance matching circuit comprises a matching network and a self-adaptive double-frequency control module, the matching network comprises a first matching branch and a second matching branch; the starting circuit comprises a clock extraction module and a voltage monitoring module. The matching network is used for inputting an external voltage signal and outputting an alternating current voltage signal with the same frequency as the external voltage signal through impedance matching; and the self-adaptive dual-frequency control module is used for generating a frequency selection signal based on a clock signal containing frequency information of the AC voltage signal so as to control the first matching branch or the second matching branch to be switched on and realize a dual-frequency self-adaptive tuning function. According to the scheme, the adaptability of the rectifier to input signals with different frequencies can be improved, and meanwhile the starting speed and the power conversion efficiency of the rectifier can be improved.

Description

Technical Field

[0001] This application relates to the field of electronic circuits, specifically to a dual-frequency adaptive single-ended input rectifier and chip. Background Technology

[0002] With the rapid development of medical electronics technology, the demand for IMDs (Implantable Medical Devices) in modern medicine is increasing rapidly. Among various wireless power transmission schemes for powering IMDs, ultrasound power transmission, with its advantages such as a small tissue attenuation coefficient (approximately 0.5-1 dB / cm / MHz) and low electromagnetic radiation risk, not only allows for smaller implant sizes and greater penetration depths but is also less susceptible to tissue heat and electromagnetic interference. Therefore, ultrasound wireless power transmission has become the primary choice for wireless power supply of IMDs. To improve the efficiency of ultrasound-driven wireless power transmission systems, beamforming technology can be used at the external transmitter to generate a focused beam to power the implant. For the implant receiver, miniaturization and chip size reduction are crucial for achieving miniaturization. Furthermore, improving the power conversion efficiency and voltage conversion rate of the receiver rectifier, thereby minimizing tissue heat and improving voltage utilization, is also one of the current research focuses of ultrasound wireless power transmission.

[0003] Traditional full-wave bridge rectifiers and CMOS voltage multipliers are no longer suitable for high-efficiency wireless power transmission systems due to their large on-state voltage drop and low conversion efficiency. Currently, the rectifier circuits at the implant receiver end in ultrasound wireless power transmission for IMD applications mainly suffer from the following problems:

[0004] 1. Traditional full-wave bridge rectifiers and CMOS multipliers are no longer suitable for high-energy-efficiency wireless power transmission systems due to their large on-state voltage drop and low conversion efficiency.

[0005] 2. Most existing active rectifiers adopt a differential input cross-coupled full-wave structure, which cannot match the single-ended output characteristics of a dual-frequency PMUT (Piezoelectric Micromachined Ultrasonic Transducer).

[0006] 3. The impedance matching network used in existing single-ended input active rectifiers can only match input signals of one frequency, which cannot meet the requirements of dual-frequency PMUTs for dual-band operation.

[0007] 4. Existing single-ended input active rectifiers cannot simultaneously meet the requirements of fast start-up and high power conversion efficiency. Summary of the Invention

[0008] This application provides a dual-frequency adaptive single-ended input rectifier and chip to solve the problem that existing single-ended input active rectifiers cannot meet the dual-frequency band operation requirements of dual-frequency ultrasonic transducers, while improving the rectifier's startup speed and power conversion efficiency.

[0009] On one hand, embodiments of this application provide a dual-frequency adaptive single-ended input rectifier, including: an impedance matching circuit, and a startup circuit and a rectifier circuit coupled to the impedance matching circuit; the impedance matching circuit includes: a matching network and an adaptive dual-frequency control module; the matching network includes a first matching branch and a second matching branch; the startup circuit includes a clock extraction module and a voltage monitoring module;

[0010] The matching network is used to input an external voltage signal and output an AC voltage signal with the same frequency as the external voltage signal through impedance matching.

[0011] The adaptive dual-frequency control module is powered by the rectified output voltage of the rectifier circuit and is used to generate a frequency selection signal based on a clock signal containing frequency information of the AC voltage signal, so as to control the first matching branch or the second matching branch to be turned on, thereby realizing the dual-frequency adaptive tuning function.

[0012] The clock extraction module is used to generate the clock signal based on the AC voltage signal, providing an initial energy path for the rectifier circuit.

[0013] The voltage monitoring module is used to monitor the rectified output voltage according to the clock signal, and output a start-up completion flag signal to the rectifier circuit after the rectified output voltage reaches a set value, so as to trigger the rectifier circuit to start working.

[0014] The rectifier circuit is used to perform AC-DC conversion according to the clock signal and the start-up completion flag signal, converting the AC voltage signal into a DC voltage signal and outputting the rectified output voltage.

[0015] Optionally, the first matching branch includes a matching capacitor, a first inductor, and a first switch connected in series; the second matching branch includes the matching capacitor, a second inductor, and a second switch connected in series; the adaptive dual-frequency control module inputs the clock signal and outputs a first frequency selection signal and a second frequency selection signal; the first frequency selection signal is used to control the first switch to close or open; the second frequency selection signal is used to control the second switch to close or open.

[0016] Optionally, the adaptive dual-frequency control module includes: a first delay unit, a frequency divider, a second delay unit, a first D flip-flop, and an inverting unit;

[0017] The first delay unit is used to input the clock signal and output a first delay signal corresponding to the clock signal;

[0018] The frequency divider is used to divide the clock signal to obtain a frequency-divided signal;

[0019] The second delay unit is used to input the frequency division signal and output a second delay signal corresponding to the frequency division signal;

[0020] The clock input of the first D flip-flop is the second delay signal, and the D trigger input of the first D flip-flop is the first delay signal; the Q output of the first D flip-flop outputs the first frequency selection signal.

[0021] The inverting unit is used to input the first frequency selection signal, invert the first frequency selection signal, obtain and output the second frequency selection signal.

[0022] Optionally, the clock extraction module includes: a charging unit and an inverter;

[0023] The charging unit includes a first PMOS transistor and a first capacitor connected in a diode configuration; the source of the first PMOS transistor is connected to the output terminal of the impedance matching circuit, and the AC voltage signal is input; the first capacitor is connected between the gate of the first PMOS transistor and ground, providing a power supply voltage for the inverter;

[0024] The inverter is used to input the AC voltage signal and output the clock signal.

[0025] Optionally, the voltage monitoring module includes: a reference voltage unit, a sampling voltage generation unit, and a control signal generation unit;

[0026] The reference voltage unit is used to generate a reference voltage;

[0027] The sampling voltage generation unit is used to generate a sampling voltage based on the reference voltage;

[0028] The control signal generation unit is used to generate the start-up completion flag signal based on the sampled voltage and the clock signal.

[0029] Optionally, the sampling voltage generation unit includes: a second PMOS transistor and a first resistor;

[0030] One end of the first resistor is connected to the drain of the second PMOS transistor, and the other end of the first resistor is grounded;

[0031] The reference voltage is input to the gate of the second PMOS transistor, and the source of the second PMOS transistor is connected to the output terminal of the rectifier circuit.

[0032] Optionally, the control signal generation unit includes a second D flip-flop; the clock signal is input to the clock terminal of the second D flip-flop, the D trigger terminal of the second D flip-flop is connected to the drain of the second PMOS transistor; the Q output terminal of the second D flip-flop outputs the start-up completion flag signal.

[0033] Optionally, the rectifier circuit includes: a comparator, a 2-to-1 multiplexer selection module, a buffer, and a rectifier diode;

[0034] The positive input terminal of the comparator is connected to the output terminal of the rectifier circuit, and the negative input terminal of the comparator receives the AC voltage signal.

[0035] The clock signal is input to the first input terminal of the 2-to-1 multiplexer selection module, and the second input terminal of the 2-to-1 multiplexer selection module is connected to the output terminal of the comparator; the start-up completion flag signal is input to the control terminal of the 2-to-1 multiplexer selection module.

[0036] The input terminal of the buffer is connected to the output terminal of the 2-to-1 multiplexer selection module to output a rectification control signal;

[0037] The rectifier tube is used to output the rectified output voltage according to the rectification control signal.

[0038] Optionally, the rectifier is a PMOS transistor, the gate of which is connected to the output terminal of the buffer; the drain of which is connected to the negative input terminal of the comparator; and the source of which serves as the output terminal of the rectifier circuit, outputting the rectified output voltage.

[0039] On the other hand, this application embodiment also provides a chip, the chip including: an adaptive dual-frequency control module, a startup circuit and a rectifier circuit;

[0040] The adaptive dual-frequency control module is powered by the rectified output voltage of the rectifier circuit and is used to generate a frequency selection signal based on a clock signal containing input signal frequency information.

[0041] The clock extraction module is used to generate the clock signal and provide an initial energy path for the rectifier circuit.

[0042] The voltage monitoring module is used to monitor the rectified output voltage according to the clock signal, and output a start-up completion flag signal to the rectifier circuit after the rectified output voltage reaches a set value, so as to trigger the rectifier circuit to start working.

[0043] The rectifier circuit is used to perform AC-DC conversion according to the clock signal and the start-up completion flag signal, and output the rectified output voltage.

[0044] The dual-frequency adaptive single-ended input rectifier provided in this application embodiment employs a dual-frequency adaptive impedance matching network and features dual-frequency adaptive tuning functionality, improving product applicability. It not only meets the dual-frequency band operation requirements of dual-frequency ultrasonic transducers but also matches its single-ended input structure with the single-ended output characteristics of the dual-frequency PMUT. Furthermore, the dual-frequency adaptive single-ended input rectifier provided in this application embodiment uses a control signal multiplexing architecture instead of the traditional multiple control module scheme, effectively reducing circuit complexity, saving chip area, reducing power consumption, and improving the rectifier's startup speed and power conversion efficiency. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0046] Figure 1 This is a schematic diagram of a dual-frequency adaptive single-ended input rectifier provided in an embodiment of this application;

[0047] Figure 2 This is a schematic diagram of an impedance matching circuit in one embodiment of this application;

[0048] Figure 3 This is a schematic diagram of one structure of the adaptive dual-frequency control module in an embodiment of this application;

[0049] Figure 4 yes Figure 3 The diagram shows the timing relationship of key signals in the adaptive dual-frequency control module.

[0050] Figure 5 This is a schematic diagram of a startup circuit in one embodiment of this application;

[0051] Figure 6 This is a schematic diagram of a rectifier circuit and an external load in an embodiment of this application;

[0052] Figure 7 This is a schematic diagram of a specific structure of the dual-frequency adaptive single-ended input rectifier provided in the embodiments of this application. Detailed Implementation

[0053] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0054] The implantation depth of an IMD (Intracytoplasmic Device) is one of the key factors determining its wireless power supply frequency. In other words, for IMDs with different implantation depths, the wireless power supply frequency based on ultrasound (such as PMUT) differs. Existing single-ended input active rectifiers use impedance matching networks that can only match one frequency of input signal, failing to meet the dual-band operation requirements of dual-frequency ultrasonic transducers. Furthermore, existing single-ended input active rectifiers cannot simultaneously meet the requirements of fast start-up and high power conversion efficiency. Therefore, this application proposes a dual-frequency adaptive single-ended input rectifier. By extracting the frequency of the ultrasonic transducer output signal (i.e., the external voltage signal input to the rectifier), a clock signal containing frequency information is obtained. Based on this clock signal, a frequency selection signal is generated, which then controls the matching circuit to select different impedance matching branches, achieving dual-frequency adaptive tuning functionality.

[0055] like Figure 1 The diagram shown is a structural schematic of a dual-frequency adaptive single-ended input rectifier provided in an embodiment of this application.

[0056] The dual-frequency adaptive single-ended input rectifier 100 includes: an impedance matching circuit 10, and a startup circuit 20 and a rectifier circuit 30 coupled to the impedance matching circuit 10. The impedance matching circuit 10 includes: a matching network 101 and an adaptive dual-frequency control module 102; the matching network 101 includes a first matching branch and a second matching branch; the startup circuit 20 includes a clock extraction module 201 and a voltage monitoring module 202. Wherein:

[0057] Matching network 101 is used to input external voltage signal V P The output is matched with the external voltage signal V through impedance matching. P AC voltage signal V of the same frequency AC ;

[0058] The adaptive dual-frequency control module 102 receives the rectified output voltage V from the rectifier circuit 30. REC Power supply, used based on an AC voltage signal V AC The clock signal CLK, which contains the frequency information, generates a frequency selection signal to control the conduction of the first matching branch or the second matching branch, thereby realizing the dual-frequency adaptive tuning function.

[0059] The clock extraction module 201 is used to extract clock signals based on AC voltage signal V. ACGenerate clock signal CLK;

[0060] Voltage monitoring module 202 is used to monitor the rectified output voltage V according to the frequency control signal CLK. REC At the rectified output voltage V REC After reaching the set value, output the start-up completion flag signal V. STU The signal is sent to the rectifier circuit 30 to trigger the rectifier circuit 30 to start working;

[0061] The rectifier circuit 30 is used to rectify the clock signal CLK and the start-up completion flag signal V. STU Complete the AC / DC conversion, converting the AC voltage signal V AC Converted to DC voltage signal, output rectified output voltage V REC .

[0062] like Figure 2 The diagram shown is a structural schematic of an impedance matching circuit in an embodiment of this application.

[0063] Simultaneously combined Figure 1 and Figure 2 In this embodiment, the matching network 101 includes two matching branches, namely a first matching branch and a second matching branch. The first matching branch includes a matching capacitor C2, a first inductor L1, and a first switch K1 connected in series; the second matching branch includes a matching capacitor C2, a second inductor L2, and a second switch K2 connected in series.

[0064] The first inductor L1 is greater than L2, and its specific value can be determined as follows: obtain the equivalent circuit model of the dual-frequency PMUT and its equivalent impedance, obtain the equivalent input impedance of the dual-frequency adaptive single-ended input rectifier, and obtain the values ​​of the matching capacitor C2, the first inductor L1 and the second inductor L2 with the help of software and other automated tools.

[0065] The adaptive dual-frequency control module 102 takes a clock signal CLK as input and outputs a first frequency selection signal F1_S and a second frequency selection signal F2_S. The first frequency selection signal F1_S is used to control the first switch K1 to close or open; the second frequency selection signal F2_S is used to control the second switch K2 to close or open.

[0066] like Figure 3 The diagram shown is a structural schematic of an adaptive dual-frequency control module in an embodiment of this application.

[0067] The adaptive dual-frequency control module 102 includes: a first delay unit 121, a frequency divider 122, a second delay unit 123, a first D flip-flop 124, and an inverting unit 125. Wherein:

[0068] The first delay unit 121 is used to input the clock signal CLK and output the first delay signal CLK' corresponding to the clock signal CLK.

[0069] Frequency divider 122 is used to divide the clock signal CLK to obtain the divided frequency signal CLK_OUT; the division factor can be, for example, 1 / 8 to improve the stability of the control loop.

[0070] The second delay unit 122 is used to input the frequency division signal CLK_OUT and output a second delay signal CLK_OUT' corresponding to the frequency division signal CLK_OUT. The delay time of the second delay unit 122 can be, for example, the midpoint of half the period of the two input frequency signals. Taking the input frequencies of 3MHz and 9.4MHz as an example, the delay time can be selected as 70ns.

[0071] The clock input of the first D flip-flop 124 is the second delay signal CLK_OUT', and the D trigger input of the first D flip-flop 124 is the first delay signal CLK'; the Q output of the first D flip-flop 124 outputs the first frequency selection signal F1_S.

[0072] The inverting unit 125 is used to input the first frequency selection signal F1_S, invert the first frequency selection signal F1_S, and obtain and output the second frequency selection signal F2_S.

[0073] It should be noted that the first delay unit 121 can be implemented using two stages of inverters, and its delay time is generally about tens of ps, which is negligible. The delay time of the second delay unit 122 is determined by the frequency of the input signal of the rectifier 100. For example, it can be the midpoint between half of the frequencies of the two input signals. Taking 3MHz / 9.4MHz as an example, the delay time of the second delay unit 122 can be in the range of 53.2~106.4ns.

[0074] The first D flip-flop 124 can acquire the first delayed signal CLK' at the rising edge of each second delayed signal CLK_OUT'. Since the distance between the rising edge of the second delayed signal CLK_OUT' and the rising edge of the nearest CLK' is the delay time of the second delay unit 122, when the input signal frequency is low, the delay time is less than half of the signal period. At this time, the CLK' signal has not yet shown a falling edge, so the output F1_S is high and F2_S is low; when the input signal frequency is high, the delay time is greater than half of the signal period. At this time, the CLK' signal has already shown a falling edge, so the output F1_S is low and F2_S is high.

[0075] Figure 4 The timing relationship of the above signals is shown. See below for further details. Figure 3 and Figure 4This explains the principle of frequency output frequency selection signal based on external voltage signal.

[0076] With external voltage signal V P Taking a frequency of 3MHz as an example, the clock signal extracted by the clock extraction module 201 is denoted as the first clock signal CLK1, and half of its period is defined as T. CLK1 The first clock signal CLK1 is delayed by the first delay unit 121 to obtain the delayed signal CLK1'. The first clock signal CLK1 is then divided by the frequency divider 122 to obtain the divided signal CLK_OUT1. The divided signal CLK_OUT1 is then delayed by the second delay unit 123 to obtain the delayed signal CLK_OUT1'. The delay time of the second delay unit 123 is defined as T. Delay The first D flip-flop 124 samples CLK1' on the rising edge of each CLK_OUT1', because... Therefore, the acquired signal is a high level, with F1_S pulled high and F2_S pulled low.

[0077] Similarly, when the external voltage signal V P When the frequency is 9.4MHz, the clock signal extracted by the clock extraction module 201 is defined as the second clock signal CLK2, and half of its period is defined as T. CLK2 The second clock signal CLK2 is delayed by the first delay unit 121 to obtain the delayed signal CLK2'. The second clock signal CLK2 is divided by the frequency divider 122 to obtain the divided signal CLK_OUT2, and the divided signal CLK_OUT2 is delayed by the second delay unit 123 to obtain the delayed signal CLK_OUT2'. The first D flip-flop 124 samples CLK2' on the rising edge of each CLK_OUT2'. Therefore, the acquired signal is low level, F1_S is pulled low, and F2_S is pulled high.

[0078] The adaptive dual-frequency control module 102 controls the switching of the two matching branches in the matching network through a closed-loop control mechanism. This switching enables adaptive frequency tuning, thereby effectively improving the power conversion efficiency of the receiver.

[0079] Reference Figure 5 , Figure 5 This is a schematic diagram of one structure of the startup circuit in an embodiment of this application.

[0080] The startup circuit 20 includes a clock extraction module 201 and a voltage monitoring module 202. Wherein:

[0081] The clock extraction module 201 includes a charging unit and an inverter 211.

[0082] The charging unit includes a first PMOS transistor M connected in a diode configuration. P1And the first capacitor C1; the first PMOS transistor M P1 The source is connected to the output of the impedance matching circuit, and the input AC voltage signal V is... AC The first capacitor C1 is connected to the first PMOS transistor M. P1 Between the gate and ground, a supply voltage V is provided for inverter 211. C1 .

[0083] Inverter 211 is used to input AC voltage signal V AC Output clock signal CLK.

[0084] The voltage monitoring module 202 includes: a reference voltage unit 221, a sampling voltage generation unit, and a control signal generation unit.

[0085] Reference voltage unit 221 is used to generate reference voltage V REF .

[0086] The sampling voltage generation unit is used to generate a voltage based on a reference voltage V. REF Generate a sampling voltage. Figure 5 In the illustrated embodiment, the sampling voltage generation unit includes: a second PMOS transistor M PS and the first resistor R S First resistor R S One end is connected to the second PMOS transistor M PS The drain, the first resistor R S The other end is grounded; the second PMOS transistor M PS Gate input reference voltage V REF The second PMOS transistor M PS source connection Figure 1 The output terminal of the intermediate rectifier circuit 30.

[0087] The control signal generation unit is used to generate a start-up completion flag signal V based on the sampled voltage and clock signal CLK. STU .exist Figure 5 In the illustrated embodiment, the control signal generation unit includes a second D flip-flop 222. The clock input of the second D flip-flop 222 is a clock signal CLK. The D trigger terminal of the second D flip-flop 222 is connected to the second PMOS transistor M. PS The drain connection is as follows; the Q output of the second D flip-flop 222 outputs a start-up completion flag signal V. STU to Figure 1 The rectifier circuit 30 in the middle.

[0088] exist Figure 5 In the illustrated embodiment, the sampling voltage generation unit includes: a second PMOS transistor M PS and the first resistor R S First resistor RS One end is connected to the second PMOS transistor M PS The drain, the first resistor R S The other end is grounded; the second PMOS transistor M PS Gate input reference voltage V REF The second PMOS transistor M PS source connection Figure 1 The output terminal of the intermediate rectifier circuit 30. When Time (V) TH For M PS Threshold voltage, V REF (reference voltage), second PMOS transistor M PS Cut-off, first resistor R S No current flows through R, therefore S When the voltage on the sampled voltage is 0, the clock signal CLK detects this sampled voltage signal and generates a start-complete flag signal V. STU At this time, the start-up completion flag signal V STU The level is low (0). When At that time, the second PMOS transistor M PS On, the first resistor R S Current begins to flow through it, and as V... REC As the current increases, the first resistance R... S The voltage on the sampled voltage also varies with V REC As the sampling voltage increases, when the sampling voltage does not reach the threshold voltage of the second D flip-flop 222, the clock signal CLK detects that the sampling voltage is still low, and the start-up completion flag signal V... STU The value remains 0. When the sampling voltage reaches the threshold voltage of the second D flip-flop 222, the clock signal CLK detects that the sampling voltage is high, and the start-up completion flag signal V is activated. STU High level 1, trigger Figure 1 The rectifier circuit 30 in the middle is working. This is achieved by appropriately setting the reference voltage V. REF The second PMOS transistor M PS The aspect ratio and resistance R S The value of V can be used to effectively estimate the threshold voltage V when the sampling voltage reaches the second D flip-flop 222. REC The value of V is thus realized when V REC When the value rises to a set value, the purpose of triggering the rectifier circuit 30 is to achieve this.

[0089] Reference Figure 6 , Figure 6 This is a schematic diagram of a rectifier circuit and an external load in an embodiment of this application.

[0090] In this embodiment, the rectifier circuit 30 includes: a comparator 301, a 2-to-1 multiplexer selection module 302, a buffer 303, and a rectifier diode M. P .in:

[0091] The non-inverting input of comparator 301 is connected to the output of rectifier circuit 30, and the negative input of comparator 301 receives the AC voltage signal V. AC ;

[0092] The first input terminal of the 2-to-1 multiplexer selection module 302 receives the clock signal CLK, and the second input terminal of the 2-to-1 multiplexer selection module 302 is connected to the output terminal of the comparator 301; the control terminal of the 2-to-1 multiplexer selection module 302 receives the clock signal CLK. Figure 5 The start-up completion flag signal V output from the Q terminal of the second D flip-flop 222. STU ;

[0093] The input terminal of buffer 303 is connected to the output terminal of 2-to-1 multiplexer selection module 302, and outputs a rectifier control signal V. CMP ;

[0094] Rectifier tube M P2 Used according to the rectifier control signal V CMP Output rectified output voltage V REC For load circuits such as Figure 6 The load resistor R in LOAD and the filter capacitor C connected in parallel with it LOAD Power supply. Rectifier diode M P2 A PMOS transistor can be used, with its gate connected to the output of buffer 303; its drain connected to the negative input of comparator 301; and its source serving as the output of rectifier circuit 30, outputting the rectified output voltage V. REC .

[0095] The following is combined with Figure 7 The working process of the dual-frequency adaptive single-ended input rectifier provided in the embodiments of this application will be described in detail.

[0096] Reference Figure 7 V P The external input signal for the dual-frequency adaptive single-ended input rectifier 100 can be, for example, the AC voltage signal output from a transducer (such as a PMUT). In the initial stage of circuit operation, the adaptive dual-frequency control module 102 receives the rectified output voltage V... REC Power supply, and at this time the rectified output voltage V REC =0, impedance matching circuit 10 is in a non-operating state. Because of the mismatch between the transducer output impedance and the rectifier 100 input impedance, the output voltage V of impedance matching circuit 10 is reduced. AC Amplitude below V P Amplitude.

[0097] The output voltage V of the impedance matching circuit 10 AC The first PMOS transistor M is connected via a diode. P1 The first capacitor C1 is charged. The voltage V across the first capacitor C1 is... C1 The supply voltage for inverter 211, when V C1 When the turn-on voltage of inverter 211 is reached, inverter 211 receives the input signal V from the start-up circuit 20. AC The clock signal CLK carrying the frequency information of the input signal is obtained. This clock signal CLK will simultaneously act on three modules: the adaptive dual-frequency control module 102 in the impedance matching circuit 10, the voltage monitoring module 202 in the startup circuit 20, and the 2-to-1 multiplexer selection module 302 in the rectifier circuit 30.

[0098] The output voltage V of the impedance matching circuit 10 AC When the amplitude is low, the rectified output voltage V REC Lower, second PMOS transistor M PS As of now, M PS The drain is at a low level, and the start-up completion flag signal V output by the second D flip-flop 222 is... STU A low level indicates that the indicator circuit has entered the startup process.

[0099] In the rectifier circuit 30, the control signal V of the 2-to-1 multiplexer selection module 302 STU When the signal is low, the clock signal CLK at its first input terminal is selected. This clock signal CLK is then passed through buffer 303 to output the rectified control signal V. CMP Control rectifier tube M P2 The on / off state.

[0100] When the output voltage V of impedance matching circuit 10 AC When the value is greater than 0, the clock signal CLK is low, and the rectifier transistor M... P2 Open, V AC To the load capacitor C LOAD Charging; when V AC When the value is less than 0, the clock signal CLK is high, and the rectifier transistor M... P2 Shut down to suppress reverse current from output to input. During startup, due to V AC For load capacitor C LOAD The charging process causes the rectified output voltage V to... REC Gradually rising.

[0101] When the rectified output voltage V RECWhen the voltage rises to the turn-on voltage of the dual-frequency adaptive control module 102, the dual-frequency adaptive control module 102 generates frequency selection signals F1_S and F2_S based on the clock signal CLK. When the input signal frequency V... P At lower frequencies (e.g., 3MHz), F1_S=1, F2_S=0; when the input signal frequency V... P At higher frequencies (e.g., 9.4MHz), F1_S=0 and F2_S=1. The frequency selection signals F1_S and F2_S control the switching of the two matching branches respectively, realizing dual-frequency adaptive tuning. After the impedance matching network is activated, V... AC The amplitude can be increased to approximately equal to or even greater than V. P The amplitude.

[0102] Rectified output voltage V REC Continue to climb, when (V) THP For the second PMOS transistor M PS When the threshold voltage is reached, the second PMOS transistor M PS Turn on, first resistor R S The current gradually increases, and the first resistor R S The voltage gradually increases, and the second D flip-flop 222 detects R on each rising edge of CLK. S The voltage on R S When the voltage reaches a certain value, the start-up completion flag signal V is activated. STU It is high. At this time, the comparator 301 in the rectifier circuit 30 can already be based on V. AC and V REC The output comparison signal is correct. The 2-to-1 multiplexer selection module 302 in the rectifier circuit 30 outputs the correct comparison signal V upon startup completion. STU Under the control of the gate comparator 301, the output signal directly controls the rectifier diode M. P2 The gate of the circuit is switched from startup mode to active rectification mode.

[0103] In active rectification mode, when When the comparator 301 outputs low, the rectifier diode M... P2 On, V AC To the load capacitor C LOAD Fast charging; when When the comparator 301 outputs high, the rectifier diode M... P2 Cutoff, effectively suppressing the flow from V REC To V AC The reverse conduction current. It is evident that, in active rectification mode, rectifier 30 can achieve high power conversion efficiency and voltage conversion rate.

[0104] The dual-frequency adaptive single-ended input rectifier provided in this application adopts a control signal multiplexing architecture. When the input voltage amplitude is low, the clock signal CLK can directly control the rectifier diode M. P2 The conduction / cutoff of the rectifier achieves the rectified output voltage V. REC The rapid rise of the voltage and the rapid start-up of the active rectifier 30; simultaneously, the clock signal CLK can also control the switching of the matching branch in the impedance matching circuit 10, start the impedance matching circuit 10, and increase the amplitude of the input signal; in addition, when the rectified output voltage V REC When the value climbs to a certain level, a start-up completion flag signal V is generated. STU The start-up completion flag signal V STU Controls the switching from startup mode to active rectification mode. In the startup circuit, V AC Through the first PMOS transistor M P1 Charging the first capacitor C1, V C1 Provide a forward power supply voltage to inverter 211. Inverter 211 draws a voltage from V... AC The clock signal CLK is obtained from the input. The clock signal CLK serves as a control signal, acting on three control channels as follows:

[0105] (1) In the startup circuit 20, the clock signal CLK passes through the detection resistor R. S The voltage on the start-up completion flag signal V is generated. STU This completes the switching between startup mode and rectification mode;

[0106] (2) In the rectifier circuit 30, when the start-up completion flag signal V STU When the signal is low, the circuit is in startup mode, and the clock signal CLK directly controls the rectifier diode M. P2 The on / off state affects the load capacitor C. LOAD Charging is performed to establish a DC output voltage V. REC .

[0107] (3) In the adaptive dual-frequency control module 102, the clock signal CLK generates the frequency division signal CLK_OUT through the frequency divider. After a certain delay, the input frequency is detected by detecting the falling edge of the delay signal CLK' of the clock signal CLK, and the control signals for switching the matching branches in the dual-frequency adaptive impedance matching network, namely F1_S and F2_S, are generated.

[0108] The dual-frequency adaptive single-ended input rectifier provided in this application not only meets the dual-frequency band operation requirements of the dual-frequency ultrasonic transducer, but also its single-ended input structure matches the single-ended output characteristics of the dual-frequency ultrasonic transducer. Furthermore, in this dual-frequency adaptive single-ended input rectifier, the impedance matching circuit, startup circuit, and rectifier circuit are simultaneously controlled by the same clock signal CLK. Compared to the traditional scheme with multiple control modules, this control signal multiplexing architecture can effectively reduce circuit complexity, save chip area, reduce power consumption, and improve the rectifier's startup speed and power conversion efficiency.

[0109] Accordingly, this application also provides a chip including the above-mentioned adaptive dual-frequency control module 102, startup circuit 20 and rectifier circuit 30. This chip has the advantages of small area and low power consumption, and has dual-frequency adaptive tuning function. It is suitable for ultrasonic wireless power transmission systems of dual-frequency ultrasonic transducers (such as PMUT) to improve the power receiving efficiency of ultrasonic transducers.

[0110] In the description of the embodiments of this application, unless otherwise expressly specified and limited, ordinal numbers, such as "first" and "second," are used only to distinguish and describe related objects, and should not be construed as indicating or implying the relative importance or order between related objects. Furthermore, ordinal numbers do not represent the number of related objects.

[0111] In the description of the embodiments in this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. Other quantifiers are similar.

[0112] The terms "or" and "and / or" used in this application are used to describe the relationship between related objects, indicating a non-exclusive inclusion. For example, "A and / or B" can include: "A alone", "B alone", or "A with B". Additionally, the character " / " in this document indicates that the preceding and following related objects are in an "or" relationship.

[0113] In the several embodiments provided in this application, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for example, the division of modules is merely a logical functional division, and there may be other division methods in actual implementation, which this application does not limit.

[0114] In the embodiments of this application, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0115] Furthermore, the functional modules in the various embodiments of this application can be integrated into one processing unit, or they can be separate physical units, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in the form of hardware and software functional units.

[0116] Integrated units implemented as hardware and software functional units can be implemented by a processor calling software; for example, the system includes a processor connected to memory, which stores instructions. The processor calls the instructions stored in memory to implement any of the above methods or to implement the functions of each module of the system. The processor is, for example, a general-purpose processor, such as a CPU or microprocessor, and the memory is either internal or external to the system. The software described above can be stored in a computer-readable storage medium.

[0117] Although embodiments of this application have been shown and described above, it is to be understood that the above embodiments are exemplary and should not be construed as limiting this application. Any person skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments without departing from the spirit and scope of this application.

Claims

1. A dual-frequency adaptive single-ended input rectifier, characterized in that, include: Impedance matching circuit, and startup circuit and rectifier circuit coupled to said impedance matching circuit; The impedance matching circuit includes a matching network and an adaptive dual-frequency control module; the matching network includes a first matching branch and a second matching branch; the startup circuit includes a clock extraction module and a voltage monitoring module. The matching network is used to input an external voltage signal and output an AC voltage signal with the same frequency as the external voltage signal through impedance matching. The adaptive dual-frequency control module is powered by the rectified output voltage of the rectifier circuit and is used to generate a frequency selection signal based on a clock signal containing frequency information of the AC voltage signal, so as to control the first matching branch or the second matching branch to be turned on, thereby realizing the dual-frequency adaptive tuning function. The clock extraction module is used to generate the clock signal based on the AC voltage signal, providing an initial energy path for the rectifier circuit. The voltage monitoring module is used to monitor the rectified output voltage according to the clock signal, and output a start-up completion flag signal to the rectifier circuit after the rectified output voltage reaches a set value, so as to trigger the rectifier circuit to start working. The rectifier circuit is used to perform AC-DC conversion according to the clock signal and the start-up completion flag signal, converting the AC voltage signal into a DC voltage signal and outputting the rectified output voltage.

2. The dual-frequency adaptive single-ended input rectifier according to claim 1, characterized in that, The first matching branch includes a matching capacitor, a first inductor, and a first switch connected in series. The second matching branch includes the matching capacitor, the second inductor, and the second switch connected in series. The adaptive dual-frequency control module takes the clock signal as input and outputs a first frequency selection signal and a second frequency selection signal; the first frequency selection signal is used to control the first switch to close or open; the second frequency selection signal is used to control the second switch to close or open.

3. The dual-frequency adaptive single-ended input rectifier according to claim 2, characterized in that, The adaptive dual-frequency control module includes: a first delay unit, a frequency divider, a second delay unit, a first D flip-flop, and an inverting unit; The first delay unit is used to input the clock signal and output a first delay signal corresponding to the clock signal; The frequency divider is used to divide the clock signal to obtain a frequency-divided signal; The second delay unit is used to input the frequency division signal and output a second delay signal corresponding to the frequency division signal; The clock input of the first D flip-flop is the second delay signal, and the D trigger input of the first D flip-flop is the first delay signal; the Q output of the first D flip-flop outputs the first frequency selection signal. The inverting unit is used to input the first frequency selection signal, invert the first frequency selection signal, obtain and output the second frequency selection signal.

4. The dual-frequency adaptive single-ended input rectifier according to claim 1, characterized in that, The clock extraction module includes: a charging unit and an inverter; The charging unit includes a first PMOS transistor and a first capacitor connected in a diode configuration; the source of the first PMOS transistor is connected to the output terminal of the impedance matching circuit, and the AC voltage signal is input; the first capacitor is connected between the gate of the first PMOS transistor and ground, providing a power supply voltage for the inverter; The inverter is used to input the AC voltage signal and output the clock signal.

5. The dual-frequency adaptive single-ended input rectifier according to claim 1, characterized in that, The voltage monitoring module includes: a reference voltage unit, a sampling voltage generation unit, and a control signal generation unit; The reference voltage unit is used to generate a reference voltage; The sampling voltage generation unit is used to generate a sampling voltage based on the reference voltage; The control signal generation unit is used to generate the start-up completion flag signal based on the sampled voltage and the clock signal.

6. The dual-frequency adaptive single-ended input rectifier according to claim 5, characterized in that, The sampling voltage generation unit includes: a second PMOS transistor and a first resistor; One end of the first resistor is connected to the drain of the second PMOS transistor, and the other end of the first resistor is grounded; The reference voltage is input to the gate of the second PMOS transistor, and the source of the second PMOS transistor is connected to the output terminal of the rectifier circuit.

7. The dual-frequency adaptive single-ended input rectifier according to claim 6, characterized in that, The control signal generation unit includes a second D flip-flop; The clock signal is input to the clock terminal of the second D flip-flop, and the D trigger terminal of the second D flip-flop is connected to the drain of the second PMOS transistor; the Q output terminal of the second D flip-flop outputs the start-up completion flag signal.

8. The dual-frequency adaptive single-ended input rectifier according to claim 1, characterized in that, The rectifier circuit includes: a comparator, a 2-to-1 multiplexer selection module, a buffer, and a rectifier diode; The positive input terminal of the comparator is connected to the output terminal of the rectifier circuit, and the negative input terminal of the comparator receives the AC voltage signal. The clock signal is input to the first input terminal of the 2-to-1 multiplexer selection module, and the second input terminal of the 2-to-1 multiplexer selection module is connected to the output terminal of the comparator; the start-up completion flag signal is input to the control terminal of the 2-to-1 multiplexer selection module. The input terminal of the buffer is connected to the output terminal of the 2-to-1 multiplexer selection module to output a rectification control signal; The rectifier tube is used to output the rectified output voltage according to the rectification control signal.

9. The dual-frequency adaptive single-ended input rectifier according to claim 8, characterized in that, The rectifier is a PMOS transistor, the gate of which is connected to the output terminal of the buffer; the drain of which is connected to the negative input terminal of the comparator; and the source of which serves as the output terminal of the rectifier circuit, outputting the rectified output voltage.

10. A chip, characterized in that, The chip includes: an adaptive dual-frequency control module, a startup circuit, and a rectifier circuit; The adaptive dual-frequency control module is powered by the rectified output voltage of the rectifier circuit and is used to generate a frequency selection signal based on a clock signal containing input signal frequency information. The clock extraction module is used to generate the clock signal and provide an initial energy path for the rectifier circuit. The voltage monitoring module is used to monitor the rectified output voltage according to the clock signal, and output a start-up completion flag signal to the rectifier circuit after the rectified output voltage reaches a set value, so as to trigger the rectifier circuit to start working. The rectifier circuit is used to perform AC-DC conversion according to the clock signal and the start-up completion flag signal, and output the rectified output voltage.

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