Linear bias circuit and power amplifier

Abstract

The invention provides a linear biasing circuit and a power amplifier, and the linear biasing circuit comprises a first resistor, a first triode, a second triode, a first capacitor, a first field effect transistor, a third triode, a second resistor and a second field effect transistor. The linear bias circuit can provide corresponding bias voltage for the power amplifier when radio-frequency signals in different power ranges are connected to the power amplifier, so that the linearity of the power amplifier cannot be deteriorated, and redundant direct-current power loss can be avoided under the condition of low power; therefore, the power amplifier can achieve the optimal efficiency and linearity in any power amplification range.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a linear bias circuit and a power amplifier. Background Technology

[0002] To achieve higher transmission rates and spectral efficiency, wireless communication systems typically employ complex modulation techniques with non-constant envelopes, such as Quadrature Phase Shift Keying (QPSK), Quadrature Amplitude Modulation (QAM), and Orthogonal Frequency Division Multiplexing (OFDM). These modulated signals usually have a high peak-to-average power ratio (PAPR).

[0003] Generally, the efficiency of a power amplifier increases with power, while its linearity deteriorates as the amplifier approaches saturation. Therefore, effective linearization techniques must be employed to improve the linearity of the power amplifier, so that it can maintain high linearity while ensuring high efficiency.

[0004] like Figure 1 As shown, the power amplifier in the related technology includes a capacitor (C2), a transistor (HBT2), and an active linear bias circuit. The active linear bias circuit includes transistors (HBT1, D1, D2), a capacitor (C1), and resistors (R1, R2), where transistors (D1, D2) are connected in diode form. When the power of the RF signal input to the power amplifier increases, some RF signal leaks into the active linear bias circuit. After rectification by transistor (HBT1), the DC voltage drop across the base-emitter junction decreases, while the base-emitter junction voltage of transistor (HBT2) increases due to the decrease in the base-emitter junction voltage of transistor (HBT1). This compensates for the base-emitter junction voltage of transistor (HBT2), thereby stabilizing the quiescent operating point of the power amplifier.

[0005] Although the active linear bias circuit described above can stabilize the quiescent operating point of the power amplifier to a certain extent, complex modulation signals have a large peak-to-average power ratio. For the power amplifier using the active linear bias circuit described above, it will reach its peak value when it is close to saturation, which will lead to the deterioration of the linearity of the power amplifier.

[0006] As can be seen from the above analysis in the power amplifiers of the related technologies, since the amount of RF power entering the active linear bias circuit is related to the values ​​of capacitor (C1) and resistor (R1, R2), the linearization effect of the active linear bias circuit is determined by its impedance. That is, the impedance of the active linear bias circuit is the reason for the deterioration of the linearity of the power amplifier.

[0007] Therefore, a new linear bias circuit and power amplifier are needed to solve the above problems. Summary of the Invention

[0008] To address the shortcomings of the aforementioned related technologies, this invention proposes a linear bias circuit and a power amplifier to solve the problem that when an active linear bias circuit provides a bias voltage to a power amplifier, the linearity of the power amplifier deteriorates when the amplifier approaches saturation.

[0009] To solve the above-mentioned technical problems, in a first aspect, the present invention provides a linear bias circuit, which includes a first resistor, a first transistor, a second transistor, a first capacitor, a first field-effect transistor, a third transistor, a second resistor, and a second field-effect transistor. The first end of the first resistor is used to connect to the first operating voltage; The collector and base of the first transistor are connected together and connected to the second terminal of the first resistor; The collector of the second transistor and the base of the second transistor are connected together and connected to the emitter of the first transistor. The emitter of the second transistor is grounded. The first terminal of the first capacitor is connected to the collector of the first transistor; The drain of the first field-effect transistor is connected to the second terminal of the first capacitor, the gate of the first field-effect transistor is used to connect to the second operating voltage, and the source of the first field-effect transistor is grounded. The collector of the third transistor is used to connect to the first operating voltage, and the base of the third transistor is connected to the first terminal of the first capacitor. The first terminal of the second resistor is connected to the emitter of the third transistor; The drain of the second field-effect transistor is connected to the emitter of the third transistor, the gate of the second field-effect transistor is used to connect to the third operating voltage, and the source of the second field-effect transistor and the second end of the second resistor are connected and together serve as the output terminal of the linear bias circuit.

[0010] Preferably, the linear bias circuit further includes a second capacitor; the emitter of the third transistor is connected to the drain of the second field-effect transistor via the second capacitor in series.

[0011] In a second aspect, the present invention provides a power amplifier, which includes an input matching circuit, a linear bias circuit as described above, and a power amplification circuit. The input terminal of the input matching circuit is used to receive radio frequency signals; The input terminal of the power amplifier circuit is connected to the output terminal of the input matching circuit and the output terminal of the linear bias circuit, respectively. The output terminal of the power amplifier circuit is used to output radio frequency signals.

[0012] Preferably, the input matching circuit includes a third capacitor; the first terminal of the third capacitor serves as the input terminal of the input matching circuit, and the second terminal of the third capacitor serves as the output terminal of the input matching circuit.

[0013] Preferably, the power amplifier circuit includes a fourth transistor; the base of the fourth transistor serves as the input terminal of the power amplifier circuit, the collector of the fourth transistor serves as the output terminal of the power amplifier circuit, and the emitter of the fourth transistor is grounded.

[0014] Compared with related technologies, the linear bias circuit in this invention adds a first field-effect transistor for connecting to the second operating voltage and a second field-effect transistor for connecting to the third operating voltage. This allows the impedance of the linear bias circuit to be adjusted by controlling the voltage values ​​of the second and third operating voltages. Thus, when the linear bias circuit provides a bias voltage to the power amplifier, it can provide the corresponding bias voltage when the power amplifier is connected to RF signals of different power ranges, so that the linearity of the power amplifier will not deteriorate. It can also avoid excessive DC power loss under low power conditions, thereby enabling the power amplifier to achieve optimal efficiency and linearity in any power amplifier range. Attached Figure Description

[0015] The present invention will now be described in detail with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and more readily understood through the detailed description following the accompanying drawings. In the drawings: Figure 1 Circuit diagram of a power amplifier provided for related technologies; Figure 2 A circuit diagram of a power amplifier provided for an embodiment of the present invention. Detailed Implementation

[0016] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein in the specification of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the terms "comprising" and "having," and any variations thereof, in the specification, claims, and foregoing drawings of this application, are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or foregoing drawings of this application are used to distinguish different objects, not to describe a particular order.

[0017] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] Example 1 Combination Figure 2 As shown, an embodiment of the present invention provides a linear bias circuit 30, which includes a first resistor R1, a first transistor D1, a second transistor D2, a first capacitor C1, a first field-effect transistor FET1, a third transistor HBT3, a second resistor R2, and a second field-effect transistor FET2.

[0020] The first end of the first resistor R1 is used to connect the first operating voltage Vb1.

[0021] The collector and base of the first transistor D1 are connected together and connected to the second terminal of the first resistor R1.

[0022] The collector of transistor D2 is connected to the base of transistor D2 and together they are connected to the emitter of transistor D1. The emitter of transistor D2 is grounded. Transistors D1 and D2 are connected in the form of diodes through their respective connection methods described above.

[0023] The first terminal of the first capacitor C1 is connected to the collector of the first transistor D1.

[0024] The drain of the first field-effect transistor FET1 is connected to the second terminal of the first capacitor C1, the gate of the first field-effect transistor FET1 is used to connect to the second operating voltage Vg2, and the source of the first field-effect transistor FET1 is grounded.

[0025] The collector of the third transistor HBT3 is connected to the first operating voltage Vb1, and the base of the third transistor HBT3 is connected to the first terminal of the first capacitor C1.

[0026] The first end of the second resistor R2 is connected to the emitter of the third transistor HBT3.

[0027] The drain of the second field-effect transistor FET2 is connected to the emitter of the third transistor HBT3. The gate of the second field-effect transistor FET2 is used to connect to the third operating voltage Vg3. The source of the second field-effect transistor FET2 and the second end of the second resistor R2 are connected and together serve as the output of the linear bias circuit 30.

[0028] In the linear bias circuit 30 of this embodiment, when the operating voltage Vg2 / Vg3 increases, the impedance of the field-effect transistors FET1 / FET2 decreases, and the impedance of the linear bias circuit 30 also decreases accordingly; conversely, when the operating voltage Vg2 / Vg3 decreases, the impedance of the field-effect transistors FET1 / FET2 increases, and the impedance of the linear bias circuit 30 also increases accordingly.

[0029] The linear bias circuit 30 also includes a second capacitor C2; the emitter of the third transistor HBT3 is connected to the drain of the second field-effect transistor FET2 via the second capacitor C2 in series. By adding the second capacitor C2, an additional path with variable impedance can be provided for the radio frequency signal while retaining the function of the DC rectifier resistor, thereby avoiding the suppression effect of the second resistor R2 on the linearization effect of the linear bias circuit 30 and maximizing the linearity of the power amplifier 100 using the linear bias circuit 30 in this embodiment.

[0030] Compared with related technologies, due to entry Figure 1In the active linear bias circuits of related technologies, the RF power is related to the values ​​of capacitor (C1) and resistors (R1, R2). Therefore, the linearization effect of the active linear bias circuit is determined by its impedance. That is, the impedance of the active linear bias circuit in related technologies is the cause of the deterioration of the linearity of the power amplifier. In this embodiment, the linear bias circuit 30 adds a first field-effect transistor FET1 for connecting to the second operating voltage Vg2 and a second field-effect transistor FET2 for connecting to the third operating voltage Vg3. Thus, the impedance of the linear bias circuit 30 can be adjusted by controlling the voltage values ​​of the second operating voltage Vg2 and the third operating voltage Vg3. In this way, when the linear bias circuit 30 provides a bias voltage to the power amplifier 100, it can provide the corresponding bias voltage when the power amplifier 100 is connected to RF signals of different power ranges, so that the linearity of the power amplifier 100 will not deteriorate, and it can also avoid excessive DC power loss under low power conditions. In this way, the power amplifier 100 can achieve optimal efficiency and linearity in any power amplifier range. In addition, from the perspective of impedance matching, the linear bias circuit 30 in this embodiment can dynamically adjust the impedance position within different power ranges to improve the freedom of power amplifier design.

[0031] Example 2 Combination Figure 2 As shown, this embodiment of the invention provides a power amplifier 100, which includes an input matching circuit 10, a power amplification circuit 20, and the linear bias circuit 30 described in the first embodiment above.

[0032] The input terminal of the input matching circuit 10 is used to connect the radio frequency signal RFin.

[0033] The input matching circuit 10 includes a third capacitor C3; the first end of the third capacitor C3 serves as the input terminal of the input matching circuit 10, and the second end of the third capacitor C3 serves as the output terminal of the input matching circuit 10.

[0034] The input terminal of the power amplifier circuit 20 is connected to the output terminal of the input matching circuit 10 and the output terminal of the linear bias circuit 30, respectively. The output terminal of the power amplifier circuit 20 is used to output the radio frequency signal RFout.

[0035] The power amplifier circuit 20 includes a fourth transistor HBT4; the base of the fourth transistor HBT4 serves as the input terminal of the power amplifier circuit 20, the collector of the fourth transistor HBT4 serves as the output terminal of the power amplifier circuit 20, and the emitter of the fourth transistor HBT4 is grounded.

[0036] Since the power amplifier 100 in this embodiment uses the linear bias circuit 30 in the first embodiment above, it can also achieve the same technical effect as the linear bias circuit 30 in the first embodiment above, which will not be described in detail here.

[0037] It should be noted that the various embodiments described above with reference to the accompanying drawings are merely illustrative of the present invention and not intended to limit its scope. Those skilled in the art should understand that any modifications or equivalent substitutions made to the present invention without departing from its spirit and scope should be included within the scope of the present invention. Furthermore, unless the context otherwise requires, words appearing in the singular include those in the plural, and vice versa. Additionally, unless specifically stated otherwise, all or part of any embodiment may be used in conjunction with all or part of any other embodiment.

Claims

1. A linear bias circuit, characterized in that, The linear bias circuit includes a first resistor, a first transistor, a second transistor, a first capacitor, a first field-effect transistor, a third transistor, a second resistor, and a second field-effect transistor. The first end of the first resistor is used to connect to the first operating voltage; The collector and base of the first transistor are connected together and connected to the second terminal of the first resistor; The collector of the second transistor and the base of the second transistor are connected together and connected to the emitter of the first transistor. The emitter of the second transistor is grounded. The first terminal of the first capacitor is connected to the collector of the first transistor; The drain of the first field-effect transistor is connected to the second terminal of the first capacitor, the gate of the first field-effect transistor is used to connect to the second operating voltage, and the source of the first field-effect transistor is grounded. The collector of the third transistor is used to connect to the first operating voltage, and the base of the third transistor is connected to the first terminal of the first capacitor. The first terminal of the second resistor is connected to the emitter of the third transistor; The drain of the second field-effect transistor is connected to the emitter of the third transistor, the gate of the second field-effect transistor is used to connect to the third operating voltage, and the source of the second field-effect transistor and the second end of the second resistor are connected and together serve as the output terminal of the linear bias circuit.

2. The linear bias circuit as described in claim 1, characterized in that, The linear bias circuit also includes a second capacitor; the emitter of the third transistor is connected to the drain of the second field-effect transistor via the second capacitor in series.

3. A power amplifier, characterized in that, The power amplifier includes an input matching circuit, a linear bias circuit as described in claim 1 or 2, and a power amplification circuit; The input terminal of the input matching circuit is used to receive radio frequency signals; The input terminal of the power amplifier circuit is connected to the output terminal of the input matching circuit and the output terminal of the linear bias circuit, respectively. The output terminal of the power amplifier circuit is used to output radio frequency signals.

4. The power amplifier as described in claim 3, characterized in that, The input matching circuit includes a third capacitor; the first terminal of the third capacitor serves as the input terminal of the input matching circuit, and the second terminal of the third capacitor serves as the output terminal of the input matching circuit.

5. The power amplifier as described in claim 3, characterized in that, The power amplifier circuit includes a fourth transistor; the base of the fourth transistor serves as the input terminal of the power amplifier circuit, the collector of the fourth transistor serves as the output terminal of the power amplifier circuit, and the emitter of the fourth transistor is grounded.

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