Broadband bidirectional amplifier chip, device and method based on gallium arsenide technology

Abstract

The invention provides a broadband bidirectional amplifier chip, equipment and a method based on a gallium arsenide process, and belongs to the technical field of integrated circuits. The chip adopts a monolithic integrated structure and comprises a first low-noise amplifier and a second low-noise amplifier which are symmetrically arranged, a first switch switching network and a second switch switching network which are respectively arranged at the input end and the output end of the chip, and a logic control circuit. The logic control circuit is powered by a positive single power supply, and converts an external control signal into a TTL level to control a switching network, thereby realizing selection and bidirectional amplification of a signal receiving and transmitting path. The low-noise amplifier adopts an improved cascode structure, and high gain, low noise and good gain flatness are realized in a frequency band of 0.5-6GHz through collaborative design of a resistor-capacitor-inductor feedback network, a peaking inductor and a grid-to-ground capacitor. The problems that a traditional discrete scheme is large in size and poor in consistency and a traditional gallium arsenide circuit needs negative-voltage power supply are solved, and the gallium arsenide circuit has the advantages of being high in integration level, low in power consumption, simple in power supply and the like.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a broadband bidirectional amplifier chip, device and method based on gallium arsenide process. Background Technology

[0002] In modern wireless communication systems, such as mobile phones and BeiDou navigation systems, there is an increasing demand for miniaturized, highly integrated, and low-cost chips. Traditional RF systems typically use discrete chips to build transceiver modules, assembling bidirectional amplifiers on printed circuit boards using independent switches, low-noise amplifiers, and other components. This approach suffers from problems such as large size, difficulty in ensuring inter-chip consistency, high system complexity, and high cost.

[0003] To achieve miniaturization, existing technologies have proposed MMIC (Multi-Instrument Microcontroller) solutions that integrate multiple functions onto a single chip. However, the design of broadband bidirectional amplifiers still faces several challenges: First, while traditional distributed amplifiers can achieve operating bandwidths across octaves, their structure typically requires 6-8 transistor dies, resulting in large chip area, high power consumption, and poor noise performance at low frequencies. Second, in terms of control circuitry, traditional gallium arsenide (GaAs) process switching circuits usually require a negative power supply voltage (e.g., -5V) for control, which increases the complexity of the external power supply circuitry and system cost. Summary of the Invention

[0004] The main objective of this application is to propose a broadband bidirectional amplifier chip, device, and method based on gallium arsenide (GaAs) technology, in order to solve the problems of large system size, high power consumption, complex power supply, and poor noise performance in the prior art.

[0005] To achieve the above objectives, one aspect of this application proposes a wideband bidirectional amplifier chip based on gallium arsenide (GaAs) technology, comprising: A chip body; The first switch switching network and the second switch switching network are respectively set at the signal input terminal and the signal output terminal of the chip body; A first low-noise amplifier and a second low-noise amplifier are integrated on the chip body and connected between the first switching network and the second switching network to form a symmetrical transmit and receive amplification path; and A logic control circuit is integrated on the chip body and electrically connected to the first switch switching network and the second switch switching network; The logic control circuit is powered by a single positive power supply and is used to receive external control signals, convert them into corresponding TTL levels to control the on / off states of the first and second switching networks, thereby selectively turning on the signal path where the first or second low-noise amplifier is located, and realizing bidirectional signal amplification.

[0006] In some embodiments, the logic control circuit includes a level shifting network consisting of multiple resistors, diodes, and capacitors, with a supply voltage VDD of +5V, receiving a control signal Vin of 0 / +5V as a clock signal, and outputting a +5V / 0V TTL level.

[0007] In some embodiments, both the first low-noise amplifier and the second low-noise amplifier employ a common-source, common-gate structure and include a temperature compensation circuit integrated on the chip body for synchronously adjusting the gate voltage of the amplifier according to the ambient temperature to stabilize gain and noise performance.

[0008] In some embodiments, the common-source, common-gate structure includes a common-source transistor and a common-gate transistor; A resistor-capacitor-inductor feedback network is connected between the gate and drain of the common source transistor and between the gate and drain of the common gate transistor. The gate of the common-gate transistor is connected to a ground capacitor; Peaking inductors are connected in series with the drains of the common-source transistor and the common-gate transistor, respectively.

[0009] In some embodiments, the parameters of the resistor-capacitor-inductor feedback network, the ground capacitor, and the peaking inductor are configured such that the bidirectional amplifier chip achieves optimized gain flatness and low noise figure in the frequency range of 0.5 GHz to 6 GHz.

[0010] In some embodiments, the common-source, common-gate structure consists of only two transistor dies.

[0011] In some embodiments, the first switch switching network and the second switch switching network are single-pole double-throw switches.

[0012] To achieve the above objectives, another aspect of the present application provides an electronic device including a radio frequency front-end module, wherein the radio frequency front-end module integrates a broadband bidirectional amplifier chip as described above.

[0013] To achieve the above objectives, another aspect of this application proposes a bidirectional signal amplification control method based on the aforementioned chip, comprising the following steps: Apply a positive single-supply voltage to the logic control circuit; Input a control signal into the logic control circuit; The control signal is converted into a first TTL level and a second TTL level by the logic control circuit, and then output to the first switching network and the second switching network respectively. Based on the first TTL level and the second TTL level, the first switching network and the second switching network are controlled to switch synchronously, so that the radio frequency input signal is output after passing through the first switching network, the first low noise amplifier, and the second switching network in sequence, or after passing through the second switching network, the second low noise amplifier, and the first switching network in sequence.

[0014] In some embodiments, the positive single power supply voltage is +5V, the control signal is a 0 / +5V clock signal, and the converted TTL level is +5V / 0V.

[0015] The embodiments of this application include at least the following beneficial effects: 1) High integration and miniaturization: The transmit / receive switching switch, two low-noise amplifier channels and control circuit are all integrated on a single chip, which greatly reduces the system size and improves channel consistency.

[0016] 2) Simplified power supply: Through innovative logic control circuit design, the traditional -5V negative voltage power supply is abandoned. Only a +5V single power supply is needed to complete the switching control, which simplifies the peripheral circuit and reduces the system cost.

[0017] 3) Excellent broadband performance: By adopting an improved cascode structure, combined with a resistor-capacitor-inductor feedback network, peaking inductor and gate-to-ground capacitor, high gain, good gain flatness and low noise figure are achieved in an ultra-wide bandwidth of 0.5-6GHz.

[0018] 4) Low power consumption: Each low-noise amplifier channel consists of only two transistor dies, which significantly reduces power consumption compared to traditional distributed amplifiers (6-8 dies).

[0019] 5) High reliability: Built-in temperature compensation circuit effectively suppresses amplifier performance drift with temperature and improves chip stability in various environments. Attached Figure Description

[0020] Figure 1 This is an overall structural diagram of the broadband bidirectional amplifier chip in the embodiments of this application; Figure 2 This is a schematic diagram of the overall broadband bidirectional amplifier in the embodiments of this application; Figure 3 This is a circuit diagram of the logic control circuit in an embodiment of this application; Figure 4 This is a diagram of the improved cascode core amplifier circuit in the embodiments of this application; Figure 5 It is a traditional level conversion circuit; where (a) is the circuit schematic and (b) is the input and output timing diagram. Figure 6 This is a small-signal equivalent circuit diagram based on Miller's theorem in the embodiments of this application; Figure 7 The results of the S21 simulation in the embodiments of this application are shown in (a) and (b) are the simulation curves of S21 when C3 changes, respectively. Figure 8 This is a schematic diagram illustrating the effects of LD1 and LD2 on the first-stage amplifier in an embodiment of this application; where (a) shows the effect of changes in LD1 on S21; (b) shows the effect of changes in LD1 on S11; (c) shows the effect of changes in LD1 on stability; (d) shows the effect of changes in LD2 on S21; (e) shows the effect of changes in LD2 on S11; and (f) shows the effect of changes in LD2 on stability. Figure 9 This is a schematic diagram of a traditional distributed architecture. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application; they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.

[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0023] Before providing a detailed description of the embodiments of this application, some of the nouns and terms involved in the embodiments of this application will be explained first. The nouns and terms involved in the embodiments of this application are subject to the following interpretations.

[0024] 1) MMIC is an abbreviation for Monolithic Microwave Integrated Circuit, which is a single-chip microwave integrated circuit. It is made by using a series of semiconductor processes on a semi-insulating semiconductor substrate to manufacture passive and active components, and then connecting them to form a functional circuit for use in the microwave (or even millimeter wave) frequency band.

[0025] 2) TTL level signals specify that +5V is equivalent to logic "1", and 0V is equivalent to logic "0" (when using binary to represent data). This data communication and level specification method is called the TTL (Transistor-to-Transistor Logic Level) signal system. This is the standard technology for communication between various parts within a computer processor-controlled device.

[0026] The miniaturization requirements for RF terminals such as mobile phones using BeiDou navigation are increasing. Traditional RF systems use bidirectional amplifiers that are separate transceiver modules built from discrete chips, resulting in large sizes and difficulties in ensuring inter-chip consistency. The bidirectional amplifier disclosed in this application integrates two transmit / receive switching (SW) circuits, two low-noise amplifier (LNA) circuits for both transmit and receive channels, and a logic level control circuit onto a single gallium arsenide MMIC chip. The transmit and receive channels are identical and symmetrical, and the LNA circuit has an internal temperature compensation module, ensuring stability in various environments. The bidirectional amplifier chip of this application features high integration and small size, significantly reducing the cost of RF systems.

[0027] This application's bidirectional amplifier operates in the 0.5-5 GHz range, requiring the introduction of a wideband low-noise amplifier for that frequency band. While traditional distributed structures can achieve operating bandwidth across octaves, they suffer from large chip area, high power consumption, and high noise at low frequencies. To address this issue, this bidirectional amplifier MMIC will employ... Figure 2 The diagram shows a two-stage low-noise amplifier with either a first or second LNA. It employs a common-source, common-gate amplification structure, fully utilizing two negative feedback loops to extend bandwidth and balance gain. Simultaneously, a ground capacitance is added to the gate of the common-gate transistor to improve high-frequency gain, and peaking inductors are added to the drains of both the common-source and common-gate transistors to improve broadband gain characteristics and reduce noise. Furthermore, optimized matching structures achieve low noise and high linearity over an ultra-wideband range.

[0028] See Figure 1 , Figure 1The overall structure of the bidirectional amplifier chip according to an embodiment of this application is shown. The chip includes a first switching network 101, a second switching network 102, a first low-noise amplifier 103, a second low-noise amplifier 104, and a logic control circuit. A signal can be input from the RXin port, selected by the first switching network 101, amplified by the first LNA 103, and then output from the RXout port via the second switching network 102; alternatively, a signal can be input from the TXin port, selected by the second switching network 102, amplified by the second LNA 104, and then output from the TXout port via the first switching network 101. The logic control circuit receives an external control signal Vin and generates corresponding control voltages Vctrl1 and Vctrl2 to synchronously control the switching of the two switching networks.

[0029] See Figure 2 It displays the detailed circuit schematic of the chip. The two low-noise amplifiers (LNA1 and LNA2) are structurally symmetrical. The core amplification circuit of each LNA uses, for example... Figure 4 The improved common source, common gate structure is shown.

[0030] See Figure 4 The improved cascode structure includes a cas-source transistor M1 and a cas-gate transistor M2. A feedback network consisting of a resistor, capacitor, and inductor is connected between the gate and drain of M1; a feedback network consisting of a resistor, capacitor, and inductor is also connected between the gate and drain of M2. A capacitor to ground is also connected to the gate of M2. Peaking inductors are connected in series with the drains of M1 and M2, respectively. and The coordinated operation of these components, through the introduction of multiple negative feedbacks and peaking effects, effectively expands the operating bandwidth and balances gain and noise performance. Simultaneously, the circuit integrates a temperature compensation module, which senses ambient temperature and adjusts the transistor's gate voltage to compensate for temperature variations in parameters such as transistor transconductance.

[0031] See Figure 3 The logic control circuit consists of a specific level-shifting network composed of resistors R1-R10, diodes D1-D5, and capacitor C1. When the external input control voltage Vin switches between 0V and +5V, this circuit, powered only by a single VDD=+5V power supply, can generate corresponding +5V and 0V TTL control levels at its outputs Vout1 and Vout2, thereby driving subsequent switching circuits. This contrasts sharply with traditional negative voltage power supply level-shifting circuits, greatly simplifying the system power supply design.

[0032] The following detailed description of the modules and working principle of the chip in this embodiment, in conjunction with specific implementation methods, provides a detailed explanation.

[0033] (1) Overall chip structure See Figure 1 The bidirectional amplifier chip provided in this embodiment consists of multiple modules, including two low-noise amplifiers (LNAs), a switching network (SW), and a logic control circuit, as detailed below: 1.1) First switch to switch networks Structure: Composed of switching elements, selectively transmitting signals to either the first or second amplifier. Utilizes single-pole double-throw switching technology.

[0034] Function: Switches the input path of the signal according to the state of the control signal to achieve bidirectional signal amplification.

[0035] 1.2) First Amplifier (First LNA): Structure: It adopts a cascode structure and a feedback structure of capacitor, resistor and inductor, integrating multiple inductors, capacitors and field-effect transistors, and has wide bandwidth, high gain and low noise characteristics.

[0036] Function: Amplify radio frequency signals to ensure signal integrity.

[0037] 1.3) Second Amplifier (Second LNA): Structure: Same as but inverted from the first amplifier, with optimized feedback and circuit structure to ensure good gain and noise performance.

[0038] Function: Amplify radio frequency signals to ensure signal integrity.

[0039] 1.4) Second switch to switch the network: Structure: Functionally the same as the first switch network, responsible for sending the amplified signal to the output.

[0040] Function: Switches the input path of the signal according to the state of the control signal to achieve bidirectional signal amplification.

[0041] 1.5) Logic control circuit: Structure: This circuit consists of multiple resistors (R1-R10), diodes (D1-D5), and capacitors (C1). These components are connected in different ways to form an amplification structure adapted to the input signal.

[0042] Function: It abandons the traditional -5V power supply and adopts +5V power supply, making the system power supply simpler. According to the receiving / transmitting usage mode, the control voltage Vin (0 / +5V) is adjusted, and then converted to (+5 / 0V) through the logic control circuit to control the switching transistor.

[0043] (2) Working principle 2.1) Signal input: The received RF signal enters the first switch through the receive input RXin, is amplified by the first LNA, and then switches to the second switch network to the receive-transmitter RXout; or the transmit input RF signal enters the second switch through TXin, is amplified by the second LNA, and then switches to the first switch network to the transmit-transmitter TXout.

[0044] 2.2) Signal amplification: The switching network determines the signal path based on the control logic: If the first amplifier is selected, the signal is amplified by the first amplifier and then enters the second switching network; If the second amplifier is selected, the signal is amplified by the second amplifier and then enters the first switching network.

[0045] (3) Control Logic The control logic in this embodiment uses a VDD=5V power supply and a clock signal Vin (0 / +5V). After passing through this control network, it is finally switched to the corresponding TTL level (+5 / 0V), controlling the corresponding first and second switching networks to complete the control of the bidirectional transceiver amplifier circuit. This control network can flexibly switch according to system requirements, ensuring smooth signal transmission between different channels.

[0046] In the field of gallium arsenide (GaAs) circuit design, traditional solutions generally use -5V for power supply control. For example... Figure 5 As shown in (a), VEE = -5V. When the external clock signal Vin is 0 / 5V, the voltages of the level conversion signals for Vout1 and Vout2 are -5V and 0V, respectively. Figure 5 As shown in (b), the control of the first switch and the second switch is completed.

[0047] The embodiment adopted Figure 3 The level switching structure shown adopts a VDD=5V design, eliminating the use of VEE negative voltage and making the system power supply simpler.

[0048] (4) Theoretical analysis and simulation verification This embodiment of the wideband low-noise amplifier only requires a cascode consisting of two dies to achieve wideband amplification. It employs a two-stage gate-drain feedback structure with a resistor-capacitor-inductor configuration, effectively achieving 10 octave wideband amplification. The following is combined with… Figure 6 The small-signal equivalent model shown is subjected to theoretical analysis and simulation verification.

[0049] Will Figure 6 The feedback loops Rf and Cf are equivalent to the ground impedances m1Z at both ends of the feedback loop. F m2Z F The feedback loop impedance Z F=R F +1 / (sC f The equivalent impedance to ground for power supply branches L4, L5, and R12 is Z. L This is to facilitate impedance analysis. Cgs is the gate-source parasitic capacitance, Cds is the drain-source parasitic capacitance, rds is the drain-source parasitic resistance, and Z... L is the load impedance. m1 and g m2 It is the transconductance of transistors M1 and M2. It is the voltage gain at both ends of the feedback.

[0050] Among them, Miller factor (1) (2) (3) (4) Feedback loop impedance: (5) (6) make Given the equivalent transconductance of a cascode source, the overall voltage gain can be obtained. The relevant impedances are as follows: (7) in (8) in (9) Substitute the feedback loop impedance equation (8) into equation (11). (10) To further simplify the analysis, we assume... Figure 6 Resistance between source and drain of the transistor , It is infinitely large.

[0051] Then equations (8) to (10) can be further simplified to: (11) (12) (13) achievable The expression: (14) At high frequencies, the effects of low frequencies (such as large capacitance impedance) can be ignored. or the impedance of a small inductor ), and on and Make reasonable simplifications.

[0052] The following is the derivation and simplification process: 1) At high frequencies, the impedance of the capacitor ,therefore , , It can be ignored; 2) In the high-frequency range of the Ku band, C4 and C5 are small capacitors and are generally short-circuited. , ; 3) Inductor impedance As frequency increases, retention , , .

[0053] Ignore at high frequencies , : (15) Furthermore, if and When the values ​​are equal, or at high frequencies, the denominator is changed. Dominance, then (16) At this point, the parallel resonant impedance is: (17) At the resonant frequency Time (18) Furthermore,

[0054] (19) Will , For high-frequency simplification, we have: (20) like and leading: (twenty one) Formula (18) Substitute into equation (22) above. (twenty two) To further simplify the analysis, ignore and High-frequency effects: (twenty three) visible, , , The introduction of can increase the gain Increasing the value expands the bandwidth. To verify the above analysis results, the rest of the circuit was kept constant in the simulation, and different values ​​were used... , , Simulations were performed to observe the effect of the value on the small-signal gain. The simulation results are as follows Figure 7 As shown.

[0055] The results show that increasing C3 does indeed improve the gain, especially at high frequencies. However, this also degrades stability and output echo, so the value of C3 needs to be selected by considering both gain and VSWR. Using the same method, different values ​​of LD1 and LD2 were tested, and the simulation results are as follows. Figure 8 As shown.

[0056] An increase in LD1 and LD2 will lead to The increase is particularly noticeable in the high-frequency range. This aligns with the previous analysis results. In conclusion, adjusting LD1... , The value is used to adjust the gain and improve the broadband gain flatness, thereby expanding the bandwidth. The topology proposed in this patent can effectively expand the bandwidth.

[0057] Furthermore, traditional distributed amplifiers require 6-8 transistors, while the low-noise amplifier proposed in this embodiment uses only 2 transistors, thus significantly reducing power consumption. Traditional distributed amplifiers, such as... Figure 9 As shown. The broadband amplifier proposed in this embodiment only requires two transistors to form a cascode structure to achieve amplification under the same conditions, significantly reducing power consumption.

[0058] (5) Advantages and beneficial effects In summary, compared with the prior art, this application has at least the following advantages and beneficial effects: 1) High integration: Multiple functional modules (two LNAs, two switching networks and control logic circuits) are integrated on the same chip, reducing system size and complexity.

[0059] 2) Bidirectional amplification design: The bidirectional amplifier structure enables bidirectional amplification of signals on the same chip, improving the flexibility and efficiency of signal processing.

[0060] 3) Improved circuit design: By introducing improved cascode and appropriate inductor-resistor-capacitor negative feedback between the gate and drain, the circuit layout was optimized, achieving good gain, reducing noise figure and power consumption in a wide bandwidth of 0.5-6GHz, and improving the overall performance of the amplifier.

[0061] 4) Novel logic control circuit: Powered by VDD=5V, with a clock signal Vin (0 / 5V). This control network switches to the corresponding TTL level (+5 / 0V), controlling the first and second switching networks to complete the control of the bidirectional transceiver amplifier circuit. 5) Noise reduction performance: Through reasonable circuit layout and material selection, this invention significantly reduces the noise figure and improves signal quality. Existing distributed broadband technologies often struggle to achieve the same effect in low-frequency noise.

[0062] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0063] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0064] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0065] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A broadband bidirectional amplifier chip based on gallium arsenide (GaAs) technology, characterized in that, include: A chip body; The first switch switching network and the second switch switching network are respectively set at the signal input terminal and the signal output terminal of the chip body; A first low-noise amplifier and a second low-noise amplifier are integrated on the chip body and connected between the first switching network and the second switching network to form a symmetrical transmit and receive amplification path; and A logic control circuit is integrated on the chip body and electrically connected to the first switch switching network and the second switch switching network; The logic control circuit is powered by a single positive power supply and is used to receive external control signals, convert them into corresponding TTL levels to control the on / off states of the first and second switching networks, thereby selectively turning on the signal path where the first or second low-noise amplifier is located, and realizing bidirectional signal amplification.

2. The broadband bidirectional amplifier chip according to claim 1, characterized in that, The logic control circuit includes a level shifting network consisting of multiple resistors, diodes, and capacitors. Its power supply voltage VDD is +5V, it receives a control signal Vin that is a clock signal of 0 / +5V, and outputs a TTL level of +5V / 0V.

3. The broadband bidirectional amplifier chip according to claim 1, characterized in that, Both the first and second low-noise amplifiers adopt a common-source, common-gate structure and include a temperature compensation circuit integrated on the chip body for synchronously adjusting the gate voltage of the amplifier according to the ambient temperature to stabilize gain and noise performance.

4. The broadband bidirectional amplifier chip according to claim 3, characterized in that, The common-source, common-gate structure includes a common-source transistor and a common-gate transistor; A resistor-capacitor-inductor feedback network is connected between the gate and drain of the common source transistor and between the gate and drain of the common gate transistor. The gate of the common-gate transistor is connected to a ground capacitor; Peaking inductors are connected in series with the drains of the common-source transistor and the common-gate transistor, respectively.

5. The broadband bidirectional amplifier chip according to claim 4, characterized in that, The parameters of the resistor-capacitor-inductor feedback network, the ground capacitor, and the peaking inductor are configured to optimize the gain flatness and low noise figure of the bidirectional amplifier chip in the frequency range of 0.5 GHz to 6 GHz.

6. The broadband bidirectional amplifier chip according to claim 4, characterized in that, The common-source, common-gate structure consists of only two transistor dies.

7. The broadband bidirectional amplifier chip according to claim 1, characterized in that, The first switch switching network and the second switch switching network are single-pole double-throw switches.

8. An electronic device, characterized in that, It includes a radio frequency front-end module, wherein the radio frequency front-end module integrates a broadband bidirectional amplifier chip as described in any one of claims 1 to 7.

9. A bidirectional signal amplification control method based on the chip according to any one of claims 1 to 7, characterized in that, Includes the following steps: Apply a positive single-supply voltage to the logic control circuit; Input a control signal into the logic control circuit; The control signal is converted into a first TTL level and a second TTL level by the logic control circuit, and then output to the first switching network and the second switching network respectively. Based on the first TTL level and the second TTL level, the first switching network and the second switching network are controlled to switch synchronously, so that the radio frequency input signal is output after passing through the first switching network, the first low noise amplifier, and the second switching network in sequence, or after passing through the second switching network, the second low noise amplifier, and the first switching network in sequence.

10. The method according to claim 9, characterized in that, The positive single power supply voltage is +5V, the control signal is a 0 / +5V clock signal, and the converted TTL level is +5V / 0V.

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