Low-voltage AGC circuit for inductance encoder

Abstract

The invention provides a low-voltage AGC (Automatic Gain Control) circuit for an inductance encoder. The device is characterized by comprising a sine channel PreAmp (1), a cosine channel PreAmp (2), a sine channel dB linear amplifier (3), a cosine channel dB linear amplifier (4), a phase difference circuit (5), a vector amplitude synthesis circuit (6), a quantization circuit (7), a digital algorithm circuit (8), a sine channel output buffer (9) and a cosine channel output buffer (10). According to the invention, an innovative full-simulation vector amplitude synthesis circuit is adopted to replace a traditional switched capacitor scheme, so that the technical bottleneck that the signal amplitude cannot be accurately detected in a low-voltage environment is successfully overcome, and the AGC system can stably work and accurately control the output amplitude at the low voltage of less than or equal to 3.3 V. In combination with a wide dynamic range brought by a dB linear amplifier and precise control of a digital intelligent algorithm, the circuit finally provides a complete low-voltage solution with high response speed, ultrahigh amplitude stability and excellent anti-interference capability for an inductance encoder, and is particularly suitable for low-power-consumption scenes such as portable equipment and the Internet of Things.

Description

(I) Technical Field

[0001] This invention relates to a low-voltage AGC circuit for inductive encoders. By employing an innovative fully analog vector amplitude synthesis circuit to replace the traditional switched capacitor solution, this invention successfully overcomes the technical bottleneck of inaccurate signal amplitude detection under low-voltage environments, enabling the AGC system to operate stably and precisely control the output amplitude at voltages ≤3.3V. Combined with the wide dynamic range provided by a dB linear amplifier and the precise control of digital intelligent algorithms, this circuit ultimately provides inductive encoders with a complete low-voltage solution featuring high response speed, ultra-high amplitude stability, and excellent anti-interference capabilities. It is particularly suitable for low-power scenarios such as portable devices and the Internet of Things, as well as for mechatronic systems requiring precise motion measurement and control under stringent conditions such as complex electromagnetic environments, wide temperature ranges, and vibration. (II) Background Technology

[0002] In inductive encoders, the AGC circuit is a crucial signal conditioning module. Through a closed-loop feedback system, it automatically adjusts the system gain to maintain a constant output signal amplitude, effectively overcoming measurement errors caused by air gap variations, temperature drift, and other factors. This significantly improves the accuracy, stability, and reliability of angle or position measurements. The ultimate goal of an inductive encoder is to accurately resolve the rotor's angle or position information. This information is typically encoded in the phase relationship or amplitude ratio of the inductive signal, rather than the absolute amplitude of a single signal. In practical operation, a series of non-ideal factors can affect the amplitude: 1. Mechanical level: The air gap between the rotor and stator cannot remain absolutely constant during rotation. Minor bearing clearances, shaft eccentricity, installation errors, or mechanical wear can all cause dynamic changes in the air gap. According to the law of electromagnetic induction, even a small increase in the air gap can lead to a sharp decrease in magnetic coupling efficiency, resulting in a significant attenuation of the inductive signal amplitude. 2. Environmental level: Temperature changes profoundly affect the system. The DC resistance of the coil changes, the permeability of the magnetic core drifts, and the characteristics of semiconductor components also change. These directly cause gain drift throughout the entire signal chain. 3. Electrical Level: The source signal supplying power to the excitation coil may fluctuate, and the performance of amplifiers in the circuit may age over time. If these fluctuating signals are directly fed to the angle calculation circuit (such as a phase detector or ADC), the resulting angle value will be full of errors, completely failing to meet the accuracy requirements of industrial applications. The AGC circuit uses a precise negative feedback closed-loop system to combat all of the above interferences. It continuously samples the amplitude of the key signal (which may be the peak value, RMS value, or envelope) from the output. The sampled real-time amplitude is compared with an internally highly stable reference voltage. When the signal amplitude is greater than the reference voltage, the AGC circuit generates a control signal, instructing the variable gain amplifier in the preceding stage to reduce its gain, pulling the output signal amplitude down to the standard level. When the signal amplitude is less than the reference voltage, the control signal instructs the variable gain amplifier in the preceding stage to increase its gain, amplifying the output signal amplitude to the standard level. This process is real-time, continuous, and dynamic. No matter how fast and severe the external interference is, this closed-loop system can always respond quickly, compensating for external changes by adjusting its own gain, and ultimately locking the output signal amplitude firmly at the preset reference value.

[0003] Common AGC circuits include the following types: 1. AGC based on a variable gain amplifier. This is implemented analogally, with its core being an amplifier whose gain can be continuously adjusted by voltage (such as a Gilbert unit). By real-time detection of the output signal amplitude and comparison with a reference voltage, the resulting error voltage is filtered and then used to control the amplifier gain, forming a negative feedback closed loop, thereby maintaining output stability over a wide input range. This type of AGC has several drawbacks: ① The relationship between the VGA gain and the control voltage (usually DC voltage) drifts with changes in temperature and power supply voltage. Under the same control voltage, the actual gain of the circuit may differ at different temperatures, causing steady-state errors in the AGC loop, meaning the output signal amplitude cannot be precisely stabilized at the target value. DC offset of the integrator or filter that generates the control voltage also introduces errors. ② To suppress high-frequency jitter and noise, the bandwidth of the loop filter needs to be set narrow, but this slows down the loop's response speed (i.e., settling time). Conversely, increasing the loop bandwidth to improve response speed may cause loop oscillation or generate excessive ripple on the control voltage, resulting in poor output signal quality. ③ The gain-control voltage relationship of the VGA itself may not be perfectly linear (or logarithmically linear), which can lead to inaccurate control characteristics. When the input signal amplitude varies greatly, the VGA may not be able to maintain good linearity (low distortion) under all gain settings, especially at high gain and large input signals, where it is prone to saturation and distortion. ④ The accuracy of the entire AGC loop depends to a large extent on the accuracy of the amplitude detector (such as a peak detector or RMS detector). The temperature stability of the detector itself, its sensitivity to waveform type (e.g., peak detection is very sensitive to pulses, but inaccurate for signals with different noise levels), and its detection efficiency all directly affect the accuracy of the control voltage. If a very short but large burst pulse occurs, due to the limited loop response speed, the pulse may saturate subsequent circuits (such as the ADC) before the AGC has time to reduce the gain. 2. Switched Capacitor / Digital AGC. This type of AGC uses a mixed-signal design, using digitally controlled switched capacitor arrays or digital potentiometers to discretely (stepwise) set the amplifier gain. The output amplitude is detected and compared with a digital threshold. The gain code is then calculated by digital logic to precisely configure the feedback network. Its biggest advantage is that the gain is determined by the ratio of capacitors or resistors, resulting in high accuracy, good temperature stability, and ease of digital interface integration. However, it suffers from gain quantization errors, limiting its speed. Switched capacitors generate kT / C noise during charge transfer, directly limiting the circuit's optimal noise performance, especially at high gain settings. 3. Fully Digital AGC. In fully digital AGC, the signal is digitized by the ADC as early as possible after coarse adjustment at the front end. Subsequently, all gain control and amplitude stabilization are performed in the digital domain.Digital processing units (such as DSPs) calculate signal power and generate a gain control word through a digital control loop (such as a digital integrator). This control word can drive the front-end digitally controllable analog gain stage for coarse adjustment or directly control the digital multiplier for fine scaling of the data stream. It has the advantages of drift-free operation and flexible parameter adjustment, but its performance is highly dependent on the dynamic range of the ADC and introduces processing delay. 4. Logarithmic amplifier-based AGC. This type utilizes amplifiers with accurate logarithmic compression characteristics (such as successive detection logarithmic amplifiers) to process signals with a very large dynamic range. Its output is a voltage proportional to the input signal power (dBm), which is itself a stable compressed signal. This signal can be used directly or used to control the pre-amplifier VGA. It provides extremely fast response speed and is very suitable for processing pulse signals, but it destroys the phase information of the signal, and the linearity of the logarithmic characteristics and temperature compensation design are quite challenging.

[0004] The AGC (Automatic Gain Control) in an inductive encoder chip requires a high-quality output signal with good phase and low delay, and it needs to operate at low voltage. Regarding signal processing: AGC based on a variable gain amplifier has continuous gain changes, making it highly susceptible to temperature drift. Switched-capacitor / digital AGCs have quantization noise and limited speed. Fully digital AGCs rely on an ADC, resulting in delay. AGCs based on logarithmic amplifiers lose phase information and are complex to design. Regarding power supply: Most functions of fully digital AGCs (such as multipliers, adders, integrators, and state machines) are implemented by digital circuits, which perform well at low voltages, and their operating voltage can be further reduced with advancements in technology. The peak detection circuit of switched-capacitor / digital AGCs typically uses a switched-capacitor sum-of-squares circuit, which stacks too many transistors, making it unsuitable for low-voltage operation. AGCs based on variable gain amplifiers, due to the presence of Gilbert cells and excessive transistor stacking, are also not well-suited for low-voltage operation. AGCs based on logarithmic amplifiers involve excessive circuit cascading and complex transistor stacking, also making them unsuitable for low-voltage operation. AGC based on variable gain amplifiers, switched capacitor / digital AGC, fully digital AGC, and logarithmic amplifier-based AGC cannot meet the requirements of inductive encoder AGC. Therefore, it is necessary to combine the characteristics of these four types of AGC, taking advantage of their strengths and compensating for their weaknesses, to ensure operation at low voltage while guaranteeing good signal quality, normal phase, and low delay.

[0005] This invention proposes a low-voltage AGC circuit for inductive encoders. It consists of a sine channel PreAmp (1), a cosine channel PreAmp (2), a sine channel dB linear amplifier (3), a cosine channel dB linear amplifier (4), a phase difference circuit (5), a vector amplitude synthesis circuit (6), a quantization circuit (7), a digital algorithm circuit (8), a sine channel output buffer (9), and a cosine channel output buffer (10). The key architectural feature of this invention is that the VGA section uses a conventional linear amplifier, achieving VGA functionality through a precise resistor feedback network ratio. Gain is changed by digitally adjusting the resistor network ratio, and this change is logarithmically linear, significantly expanding the dynamic range. The peak detection circuit uses a continuous-time vector amplitude synthesis circuit to detect peak-to-peak values, accelerating the conversion speed. The linear amplifier, peak detection circuit, and digital control circuit can all operate under low voltage conditions, ensuring that the inductive encoder chip maintains good output signal quality, good phase, and low delay under low voltage. (III) Summary of the Invention

[0006] The purpose of this invention is to provide a low-voltage AGC circuit for inductive encoders.

[0007] The objective of this invention is achieved as follows:

[0008] (Claim 1) The low-voltage AGC circuit for an inductive encoder consists of a sine channel PreAmp (1), a cosine channel PreAmp (2), a sine channel dB linear amplifier (3), a cosine channel dB linear amplifier (4), a phase difference circuit (5), a vector amplitude synthesis circuit (6), a quantization circuit (7), a digital algorithm circuit (8), a sine channel output buffer (9), and a cosine channel output buffer (10). In the system, the sine channel PreAmp (1) performs a primary amplification on the input sine signal, and then the sine channel dB linear amplifier (3) performs further amplification, outputting to the phase difference circuit (5) and the sine channel output buffer (9) as inputs. Similarly, the cosine channel PreAmp (2) performs a primary amplification on the input cosine signal, and then the cosine channel dB linear amplifier (4) performs further amplification, outputting to the phase difference circuit (5) and the sine channel output buffer (10) as inputs. The outputs of the sine channel dB linear amplifier (3) and the cosine channel dB linear amplifier (4) are four signals with the same frequency and amplitude but a 90° phase difference. These signals are fed into the phase difference circuit (5) as input, and then the phase difference circuit (5) outputs sixteen signals with the same frequency and amplitude but a 22.5° phase difference. These sixteen signals are then processed by the vector amplitude synthesis circuit (6) to extract the DC signal containing peak-to-peak information, which is then fed into the quantization circuit (7) to obtain the error signal by subtracting it from Vset. The error signal is then quantized and output as a digital code. The digital algorithm circuit (8) classifies and processes the quantized error signal and outputs a digital control word to control the gain of the sine channel dB linear amplifier (3) and the cosine channel dB linear amplifier (4) respectively, thus forming a gain closed loop. Finally, the outputs of the dB linear amplifier (3) and the cosine channel dB linear amplifier (4) reach the target amplitude. Then, the sine channel output buffer (9) outputs the final sine signal of the inductor encoder, and the cosine channel output buffer (10) outputs the final cosine signal of the inductor encoder.

[0009] The dB linear amplifier (3, 4) consists of a dB linear programmable gain instrumentation amplifier (11) and a differential amplifier circuit (12), where (13) is the gain resistor RG and (14) is the feedback resistor RF, both of which are precision resistor arrays. Different resistor combinations are switched using CMOS analog switches with low charge injection and low on-resistance. The digital control word from the digital algorithm circuit (8) controls the analog switches of the gain resistor RG (13) and the feedback resistor RF (14), making the value of RG / RF exhibit a logarithmic relationship with the input amplitude. The amplifier circuit remains linear overall. Through a digital lookup table and a resistor switch network, discrete, linear gain levels are mapped to a macroscopically continuous (or quasi-continuous) dB linear control. This makes the loop dynamic characteristics stable and easy to compensate.

[0010] The phase difference circuit (5) consists of a pure resistor network. Based on the principle of the auxiliary angle formula (1-1), it sums the four signals with the same frequency amplitude and a 90° phase difference from the outputs of the sine channel dB linear amplifier (3) and the cosine channel dB linear amplifier (4) to form 16 signals with the same frequency amplitude and a 22.5° phase difference. These signals are then fed into the vector amplitude synthesis circuit (6). Where: a and b are the amplitudes of the two input signals, respectively, and φ is the phase shift, satisfying tanφ=b / a. It is the amplitude of the signal after signal a and signal b are combined.

[0011] The vector amplitude synthesis circuit (6) consists of a square-law current synthesizer (15), current sources (16, 17), a summing load resistor (18), a summing circuit (19), and a 2x differential amplifier circuit (20). The input terminals V1 to V16 of the vector amplitude synthesis circuit (6) are connected to 16 signals with the same frequency amplitude and a phase difference of 22.5° output from the phase difference circuit (5), which are converted into current signals that exhibit a square law relationship with the input voltages V1 to V16. These square-law current signals are added across the summing load resistor (18). After the addition of the 8 sets of two AC signals with a phase difference of 90°, they become DC, forming a DC voltage VP across the resistor. The summing circuit (18) sums the 16 signals, including V1 to V16, to obtain a common-mode voltage VN. The 2x differential amplifier circuit (20) amplifies the difference between the DC voltage VP and the common-mode voltage VN by a factor of 2, and the output is the peak-to-peak value of V1 to V16. The vector amplitude synthesis circuit (6) outputs a DC signal to the quantization circuit (7).

[0012] The quantization circuit (7) subtracts the output signal of the vector amplitude synthesis circuit (6) from the target value Vset to obtain an error signal. Then, the error signal is compared with multiple levels (VCM-160mV, VCM-80mV, VCM-20mV, VCM-10mV, VCM+10mV, VCM+20mV, VCM+80mV, VCM+160mV) to obtain an error quantization signal, where VCM is the reference level. The error quantization signal is then fed to the digital algorithm circuit (8).

[0013] The digital algorithm circuit (8) reads the error quantization signal and classifies it into negative error, positive error, and zero error. Negative error and positive error are further divided into three error levels: high, medium, and low. For the three error levels of negative error (high, medium, and low), control words for fine-tuning gain increase, intermediate gain increase, and coarse-tuning gain increase are set respectively. For the three error levels of positive error (high, medium, and low), control words for fine-tuning gain increase, intermediate gain increase, and coarse-tuning gain increase are set respectively. For zero error, the current gain is maintained. Finally, the digital algorithm (8) outputs control words to control the gain switching of the dB linear amplifiers (3, 4). The control words of the dB linear amplifiers (3) and (4) are independent. Even if the input amplitudes of the AGC circuit input signals VSINP_IN, VSINN_IN and VCOSP_IN, VCOSN_IN are inconsistent, the digital algorithm circuit (8) can still make the amplitudes of the final output signals VSIN and VCOS reach the same target value. (iv) Description of the attached drawings

[0014] Figure 1 This is a schematic diagram of a low-voltage AGC circuit used for inductive encoders. It consists of a sine path PreAmp (1), a cosine path PreAmp (2), a sine channel dB linear amplifier (3), a cosine channel dB linear amplifier (4), a phase difference circuit (5), a vector amplitude synthesis circuit (6), a quantization circuit (7), a digital algorithm circuit (8), a sine channel output buffer (9), and a cosine channel output buffer (10).

[0015] Figure 2 This is a schematic diagram of a dB linear amplifier (3, 4), which consists of a dB linear programmable gain instrumentation amplifier (11) and a differential amplifier (12). Among them, (13) is the gain resistor RG and (14) is the feedback resistor RF, both of which are precision resistor arrays. Different resistor combinations are switched using CMOS analog switches with low charge injection and low on-resistance.

[0016] Figure 3It is a vector amplitude synthesis circuit (6), which consists of a square law current synthesizer (15), a current source (16, 17), a summing load resistor (18), a summing circuit (19), and a 2x differential amplifier circuit (20).

[0017] Figure 4 This is a schematic diagram of the embodiment. The circuit consists of an inductor receiving coil (21), a demodulation filter circuit (22), a sine path PreAmp (1), a cosine path PreAmp (2), a sine channel dB linear amplifier (3), a cosine channel dB linear amplifier (4), a phase difference circuit (5), a vector amplitude synthesis circuit (6), a quantization circuit (7), a digital algorithm circuit (8), a sine channel output buffer (9), and a cosine channel output buffer (10). (V) Detailed Implementation

[0018] Figure 4 An embodiment of the low-voltage AGC circuit of the inductive encoder is given in the case of the inductive encoder receiving coil. The circuit consists of an inductive receiving coil (21), a demodulation / filtering circuit (22), a sine path PreAmp (1), a cosine path PreAmp (2), a sine channel dB linear amplifier (3), a cosine channel dB linear amplifier (4), a phase difference circuit (5), a vector amplitude synthesis circuit (6), a quantization circuit (7), a digital algorithm circuit (8), a sine channel output buffer (9), and a cosine channel output buffer (10).

[0019] The signals induced by the sine and cosine channels of the inductor receiving coil (21) are sent to the demodulation / filtering circuit (22) to output clean sine and cosine signals VSINP_IN, VSINN_IN, VCOSP_IN, and VCOSN_IN. These are then connected to PreAmp (1, 2) and amplified by the dB linear amplifier (3, 4), outputting four signals with the same frequency, amplitude, and 90° phase difference to the phase difference circuit (5) as input. The phase difference circuit (5) then outputs 16 signals with the same frequency and amplitude, and a phase difference of 22.5°. These 16 signals are then processed by the vector amplitude synthesis circuit (6) to detect the peak-to-peak value. The quantization circuit (7) calculates the difference between the peak-to-peak value and the set value Vset to obtain the error signal. The error signal is then quantized to output a digital code. The digital algorithm circuit (8) divides the error signal according to the digital code output by the quantization circuit (7), classifying it into negative error, positive error, and zero error. Negative and positive errors are further divided into three error levels: high, medium, and low. For the three error levels of negative error (high, medium, and low), control words are set for fine-tuning gain increase, medium-tuning gain increase, and coarse-tuning gain increase, respectively. For the three error levels of positive error (high, medium, and low), control words are set for fine-tuning gain increase, medium-tuning gain increase, and coarse-tuning gain increase, respectively. For zero error, the current gain is maintained. The final digital algorithm (8) outputs control words to control the gain switching of the dB linear amplifiers (3, 4). The control words of the dB linear amplifiers (3) and (4) are independent. Even if the input amplitudes of the AGC circuit input signals VSINP_IN, VSINN_IN and VCOSP_IN, VCOSN_IN are inconsistent, the digital algorithm circuit (8) can still make the amplitudes of the final output signals VSIN and VCOS reach the same target value.

Claims

1. A low-voltage AGC circuit for inductive encoders. Its features are: It consists of a sine channel PreAmp (1), a cosine channel PreAmp (2), a sine channel dB linear amplifier (3), a cosine channel dB linear amplifier (4), a phase difference circuit (5), a vector amplitude synthesis circuit (6), a quantization circuit (7), a digital algorithm circuit (8), a sine channel output buffer (9), and a cosine channel output buffer (10). In this system, the sine channel PreAmp (1) performs a primary amplification on the input sine signal, and then the sine channel dB linear amplifier (3) performs further amplification, outputting to the phase difference circuit (5) and the sine channel output buffer (9) as inputs. Similarly, the cosine channel PreAmp (2) performs a primary amplification on the input cosine signal, and then the cosine channel dB linear amplifier (4) performs further amplification, outputting to the phase difference circuit (5) and the sine channel output buffer (10) as inputs. The outputs of the sine channel dB linear amplifier (3) and the cosine channel dB linear amplifier (4) are four signals with the same frequency and amplitude but a 90° phase difference. These signals are fed into the phase difference circuit (5) as input, and then the phase difference circuit (5) outputs sixteen signals with the same frequency and amplitude but a 22.5° phase difference. These sixteen signals are then processed by the vector amplitude synthesis circuit (6) to extract the DC signal containing peak-to-peak information, which is then fed into the quantization circuit (7) to obtain the error signal by subtracting it from Vset. The error signal is then quantized and output as a digital code. The digital algorithm circuit (8) classifies and processes the quantized error signal and outputs a digital control word to control the gain of the sine channel dB linear amplifier (3) and the cosine channel dB linear amplifier (4) respectively, thus forming a gain closed loop. Finally, the outputs of the dB linear amplifier (3) and the cosine channel dB linear amplifier (4) reach the target amplitude. Then, the sine channel output buffer (9) outputs the final sine signal of the inductor encoder, and the cosine channel output buffer (10) outputs the final cosine signal of the inductor encoder.

2. The dB linear amplifier (3, 4) according to claim 1 is composed of a dB linear programmable gain instrumentation amplifier (11) and a differential amplifier circuit (12), wherein (13) is a gain resistor RG and (14) is a feedback resistor RF, both of which are precision resistor arrays. Different resistor combinations are switched using CMOS analog switches with low charge injection and low on-resistance, thereby changing the value of RG / RF, which is to say, changing the gain of the dB linear amplifier (3, 4). The digital control word from the digital algorithm circuit (8) controls the analog switches of the gain resistor RG (13) and the feedback resistor RF (14), so that the value of RG / RF has a logarithmic relationship with the input amplitude. The amplifier circuit is kept linear overall. Through the digital lookup table and the resistor switch network, the discrete, linear gain levels are mapped to a macroscopically continuous (or quasi-continuous) dB linear control. This makes the loop dynamic characteristics stable and easy to compensate.

3. The vector amplitude synthesis circuit (6) according to claim 1 consists of a square-law current synthesizer (15), current sources (16, 17), a summing load resistor (18), a summing circuit (19), and a 2x differential amplifier circuit (20). The 16 signals with the same frequency amplitude and a phase difference of 22.5° output by the phase difference circuit (5) are sent to the input terminals V1 to V16 of the vector amplitude synthesis circuit (6) and converted into current signals that exhibit a square law with the voltages of the input V1 to V16. These square-law current signals are added to the summing load resistor (18). After the 8 sets of two AC current signals with a phase difference of 90° are added together, they become DC current signals, thus forming a DC voltage VP on the resistor. The summing circuit (18) takes a common-mode level VN from the 16 signals V1 to V16. The 2x differential amplifier circuit (20) amplifies the difference between the DC voltage VP and the common-mode level VN by a factor of 2, and the output is the peak-to-peak value of V1 to V16. The vector amplitude synthesis circuit (6) processes multiple input signals with consistent amplitude and frequency and orthogonality in parallel in the current domain. Utilizing the inherent square-law characteristic of MOS transistors, it directly completes vector amplitude detection and synthesis in a single-step operation, eliminating the need for complex analog multipliers or switched-capacitor circuits found in traditional solutions. It possesses low-voltage operating capability, making it highly suitable for modern low-power SoCs, and its fully parallel, current-mode processing mechanism ensures high-speed response. For the closed-loop application of AGC, the good monotonicity of its detection output and the statistical averaging effect brought by the 16 signals fully guarantee the stability and accuracy of the loop, perfectly solving the key challenge of high dynamic range amplitude detection for inductive encoders under low-voltage conditions.

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