Automatic gain control circuit based on dichotomy and method thereof
By using a digital peak detection circuit and a binary logic module based on the binary method, the problems of high complexity and high power consumption of traditional automatic gain control circuits are solved, achieving low power consumption, fast and stable automatic gain control that is adaptable to multi-frequency environments.
Patent Information
- Application Number
- CN202511496351.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-20
- Publication Date
- 2026-02-24
AI Technical Summary
In radio frequency/intermediate frequency receiving systems such as wireless communication, radar, and broadcasting, traditional automatic gain control circuits rely on analog ADCs and digital peak detection methods, resulting in high circuit complexity, high power consumption, and poor frequency adaptability, making it difficult to achieve rapid stabilization in multi-frequency environments.
A digital peak detection circuit and a binary division logic module based on the binary division method are adopted. The gain control word is directly generated by the digital peak detection circuit, and the loop stabilization time is shortened by combining the binary division logic to achieve low-power automatic gain control.
It reduces circuit complexity and power consumption, shortens loop settling time, adapts to multi-frequency environments, and expands the adjustable gain range.
Smart Images
Figure CN121567080A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to an automatic gain control circuit and method based on the binary division method, belonging to the field of integrated circuits. Background Technology
[0002] In radio frequency (RF) / intermediate frequency (IF) receiving systems such as wireless communication, radar, and broadcasting, the dynamic range of the receiver input signal is often as high as 60dB to 100dB due to channel fading, distance variations, obstacle obstruction, and multipath effects. To ensure that the subsequent analog-to-digital converter (ADC) and baseband demodulation unit always operate within the linear and optimal quantization range, an automatic gain control (AGC) loop needs to be inserted into the RF or IF link to adjust the link gain in real time and stabilize the output signal power near the set level.
[0003] Traditional analog AGC typically consists of a closed-loop feedback system comprised of a variable gain amplifier (VGA), an analog detector (peak detector), a comparator, and an RC filter network. The detector converts the output signal amplitude into a DC voltage, which is compared with a reference voltage. After filtering by the RC network, the resulting voltage generates the AGC control voltage VAGC, which inversely adjusts the VGA gain, achieving negative feedback control of "increased output → decreased gain." Digital AGC (also known as numerically controlled AGC or digital AAGC) samples the analog signal using an ADC, performs power estimation, error calculation, and gains control word updates in the digital domain, and then adjusts the link gain in a closed loop using a DAC or a digital variable gain amplifier (DVGA).
[0004] Peak detection circuits essentially obtain a function from a detector that shows a linear relationship between the output signal and the input signal strength. However, this function is not directly applied to the gain control output of the AGC circuit. For analog methods, a comparator is needed to construct a quantization array; for digital methods, an ADC is needed for quantization to obtain the gain control output, which then controls the variable gain amplifier to adjust the gain. These peak detection methods are affected by the sampling capacitor, require a large circuit area, or are only applicable to a single detection frequency.
[0005] In the self-calibration and self-adjustment loops of analog integrated circuits, the core task is to precisely drive a certain electrical parameter (such as the zero-temperature coefficient current of a bandgap reference, the peak efficiency point of a DC-DC converter, or the phase-locked voltage of a PLL) to the target value. Traditional "successive scanning" schemes accumulate data unidirectionally or back and forth from the starting point with a fixed step size Δ, sampling the comparator output once per step until the sign flips. The bisection method replaces "step-by-step accumulation" with "interval partitioning," utilizing the intermediate value theorem to ensure that the search interval is halved in each iteration. In terms of hardware implementation, the bisection method uses shift-addition to calculate the "midpoint," with area and power consumption comparable to the "unidirectional counter" of the successive scanning method, but achieving exponential convergence speed. When the target value is large, the bisection method requires less time for the loop to stabilize compared to the successive scanning scheme. Summary of the Invention
[0006] This invention focuses on the design of low-power digital AGC without ADC in a digital manner, and provides a general automatic gain control circuit and method based on the binary method, which shortens the loop settling time as much as possible without affecting power consumption.
[0007] The technical solution adopted by the control circuit of this invention is as follows:
[0008] An automatic gain control circuit based on the binary division method includes a first peak detection circuit, a second peak detection circuit, a peak judgment logic module, a rising edge detection circuit, and a binary division logic module. The first and second peak detection circuits are respectively connected to the peak judgment logic module, which is connected to the rising edge detection circuit. The second peak detection circuit and the rising edge detection circuit are respectively connected to the binary division logic module. The first and second peak detection circuits are used to compare whether the input signal is within a reference range. The peak judgment logic module is used to generate a judgment signal based on the output levels of the first and second peak detection circuits. The rising edge detection circuit is used to extract the judgment signal and activate the binary division logic module. The binary division logic module is used to generate a gain control word.
[0009] Furthermore, the first peak detection circuit is used to compare the input signal with a first reference reference, and the second peak detection circuit is used to compare the input signal with a second reference reference, wherein the first reference reference is lower than the second reference reference.
[0010] Furthermore, the binary logic module is also connected to the clock signal CLK, and is used to shift and output the signal at the output terminal of the second peak detection circuit under the control of the clock signal CLK.
[0011] This invention also provides a control method for the above-mentioned automatic gain control circuit based on the binary division method, comprising the following steps:
[0012] Connect the input signal Vin and the input reference voltage Vref_l to the input terminal of the first peak detection circuit, and connect the input signal Vin and the input reference voltage Vref_h to the input terminal of the second peak detection circuit, wherein the input reference voltage Vref_l is less than the input reference voltage Vref_lVref_h;
[0013] When the input signal Vin is higher than the input reference voltage Vref_h and higher than the input reference voltage Vref_l, both the first peak detection circuit and the second peak detection circuit are set to 1, and the peak judgment logic module outputs a high level.
[0014] When the input signal Vin is higher than the lower input reference voltage Vref_l and lower than the higher input reference voltage Vref_h, the first peak detection circuit is set to 1, the second peak detection circuit is set to 0, and the peak judgment logic module outputs a low level.
[0015] When the input signal Vin is lower than the input reference voltage Vref_l and lower than the input reference voltage Vref_h, both the first peak detection circuit and the second peak detection circuit are set to 0, and the peak judgment logic module outputs a high level.
[0016] The beneficial effects of this invention are:
[0017] (1) Compared with the traditional analog ADC for signal sampling, the present invention adopts digital peak detection, which can reduce the complexity of circuit implementation and greatly reduce circuit power consumption (current within 100uA); at the same time, under the premise of meeting the setup time and hold time of digital timing logic, it can adapt to multi-frequency peak detection.
[0018] (2) The binary conversion logic is adopted so that the automatic gain control loop can achieve gain regulation in 6 clock cycles, shortening the loop stabilization time of the circuit.
[0019] (3) Under the binary automatic gain control logic, the present invention can extend to an automatic gain control circuit with a wider bit width, thereby further improving the dynamic range of the adjustable gain amplifier circuit. Attached Figure Description
[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0021] Figure 1 This is a block diagram of the automatic gain control circuit of the present invention;
[0022] Figure 2 This is the timing diagram of the 5-bit wide binary logic module used in Embodiment 1 of the present invention;
[0023] Figure 3 This is a schematic diagram of the combination of automatic gain control circuit and programmable gain amplifier circuit in Embodiment 2 of the present invention. Detailed Implementation
[0024] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.
[0025] Since the peak detection signal is constantly changing, existing technologies can only quantize the dynamically changing peak value using an ADC. The automatic gain control circuit of this invention, through a digital peak detection circuit based on binary logic, only needs to detect whether the peak value of the input signal circuit reaches a reference. The generated detection signal, through certain digital logic and timing, can directly provide the gain control word. For traditional peak detection methods, peak detection depends on a single sampling capacitor and has a single peak detection frequency. In contrast, the digital peak detection method of this invention only requires a detection frequency greater than the setup and hold times of the digital timing logic.
[0026] Example 1
[0027] This embodiment provides an automatic gain control circuit based on the binary search method and its operating method. The block diagram of its automatic gain control circuit is shown below. Figure 1 As shown, the automatic gain control circuit includes a first peak detection circuit, a second peak detection circuit, a peak judgment logic module, a rising edge detection circuit, and a binary division logic module. The first and second peak detection circuits are respectively connected to the peak judgment logic module, which is connected to the rising edge detection circuit. The second peak detection circuit and the rising edge detection circuit are respectively connected to the binary division logic module. The first and second peak detection circuits are used to compare whether the input signal is within the reference range. The peak judgment logic module is used to generate a judgment signal based on the output levels of the two detection circuits. The rising edge detection circuit is used to extract the judgment signal and activate the binary division logic module, which is used to generate the gain control word. In this embodiment, the binary division logic module uses a 5-bit width to generate a 5-bit gain control word, but it can be extended to other bit widths, i.e., any bit width is acceptable. In this embodiment, the first peak detection circuit is used to compare the input signal with the low reference reference, and the second peak detection circuit is used to compare the input signal with the high reference reference.
[0028] The input signal Vin and the input reference voltage Vref_l are connected to the input terminal of the first peak detection circuit, and the input signal Vin and the input reference voltage Vref_h are connected to the input terminal of the second peak detection circuit, where Vref_l is less than Vref_h. The output terminals of the first and second peak detection circuits are connected to the input terminal of the peak judgment logic module. When the input signal Vin is higher than both the input reference voltage Vref_h and the input reference voltage Vref_l, both the first and second peak detection circuits are set to 1 (i.e., outputting a high level), and the peak judgment logic module outputs a high level. When the input signal Vin is higher than the lower input reference voltage Vref_l but lower than the higher input reference voltage Vref_h, the first peak detection circuit is set to 1, the second peak detection circuit is set to 0 (i.e., outputting a low level), and the peak judgment logic module outputs a low level. When the input signal Vin is lower than both the input reference voltage Vref_l and the input reference voltage Vref_h, both the first and second peak detection circuits are set to 0, and the peak judgment logic module outputs a high level.
[0029] The output of the peak detection logic module is connected to the input of the rising edge detection circuit to determine whether the input signal Vin needs adjustment, i.e., whether the input signal Vin is lower than or higher than the input reference voltage Vref_l. Once adjustment is required, a rising edge change is detected at the output of the peak detection logic module, and the rising edge detection circuit outputs a high-level signal for one clock cycle.
[0030] When the set signal at the output of the rising edge detection circuit goes high, it will activate a 5-bit wide binary logic module. The inputs of this 5-bit wide binary logic module are connected to the clock signal CLK, the output of the rising edge detection circuit, and the output of the second peak detection circuit, respectively. Under the control of the clock signal CLK, after the binary logic module is activated, the signal at the output of the second peak detection circuit is shifted and output.
[0031] The specific working process of the aforementioned 5-bit wide binary logic module includes:
[0032] Step 1: Upon detecting that the set signal is pulled high, the binary logic module is reset, and the 5-bit wide binary logic module outputs a gain control word of 10000.
[0033] Step 2: Under the control of the clock, after the next clock cycle arrives, the signal at the output of the second peak detection circuit is retrieved and transmitted to the highest bit of the 5-bit wide binary logic module. At this time, the 5-bit wide binary logic module outputs the gain control word D51000, where D5 represents the fifth bit output result of the binary logic module, which may be 0 or 1.
[0034] Step 3: Under the control of the clock, after the next clock cycle arrives, the signal at the output of the second peak detection circuit is retrieved again, and the signal is transmitted to the second highest bit of the 5-bit wide binary logic module. At this time, the 5-bit wide binary logic module outputs the gain control word D5D4100, where D4 represents the fourth bit output result of the binary logic module.
[0035] Step 4: Under the control of the clock, after the next clock cycle arrives, the signal at the output of the second peak detection circuit is retrieved again, and the signal is transmitted to the 5-bit wide binary logic module to output the 3rd bit. At this time, the 5-bit wide binary logic module outputs the gain control word D5D4D310, where D3 represents the third bit output result of the binary logic module.
[0036] Step 5: Under the control of the clock, after the next clock cycle arrives, the signal at the output of the second peak detection circuit is retrieved again, and the signal is transmitted to the second lowest bit of the 5-bit wide binary logic module. At this time, the 5-bit wide binary logic module outputs the gain control word D5D4 D3D21, where D2 represents the second bit output result of the binary logic module.
[0037] Step six: Under the control of the clock, after the next clock cycle arrives, the signal at the output of the second peak detection circuit is retrieved again, and the signal is transmitted to the least significant bit of the 5-bit wide binary logic module. At this time, the 5-bit wide binary logic module outputs the gain control word D5D4 D3D2D1, where D1 represents the first output result of the binary logic module.
[0038] Optionally, after the 5-bit wide binary logic module completes the above-mentioned round of gain adjustment and outputs a stable output signal, the 5-bit wide binary logic module latches the output result D5D4 D3D2D1 until the input signal Vin deviates from the input reference voltage again, that is, when it is lower than the lower input reference voltage Vref_l or higher than the higher input reference voltage Vref_h, a new round of gain adjustment is performed.
[0039] When the set adjustment signal is received as high, the timing diagram of the 5-bit binary logic module is as follows: Figure 2 As shown. The final circuit requires 6 complete clock cycles to complete one input-to-output conversion. If one clock cycle is 2µs, then 6 clock cycles, or 12µs, are needed to complete one conversion. Afterward, it will wait for the next deviation of the input signal.
[0040] Example 2
[0041] This embodiment provides a method for implementing an automatic gain control circuit based on the binary division method. A schematic diagram of the combination of the automatic gain control circuit and the programmable gain amplifier circuit in Embodiment 1 is shown below. Figure 3 As shown.
[0042] First, the automatic gain control circuit is electrically connected to a programmable gain amplifier (PGA) at the chip or board level. The RF output node of the PGA is directly coupled to the analog input signal Vin port of the automatic gain control circuit, so that the instantaneous output amplitude of the PGA can be monitored in real time.
[0043] The PGA output Vout is compared with the preset high reference level Vref_h and low reference level Vref_l. Only when Vout simultaneously satisfies Vref_l < V_peak < Vref_h will the comparator output generate a latch trigger pulse.
[0044] The latch trigger pulse is sent to the clock enable pin of the 5-bit counter, causing the counter's count value at the current binary search iteration step to be latched and frozen, thus completing the control of the current gain word D. ctrl Confirmation.
[0045] The 5-bit binary gain control word D output by the counter ctrl It is then fed into a 5-to-32 line decoder, which expands the 5-bit binary codeword bit by bit into 32 mutually exclusive switch control signals.
[0046] The aforementioned 32 switch control signals drive 32 sets of parallel switch arrays or switched capacitor / switched resistor networks, thereby finely adjusting the output gain of the PGA in 1dB steps to achieve 32-level gain closed-loop control within the range of 0dB to 31dB.
[0047] The entire bisection iterative process is repeatedly executed under the control of digital control logic until the peak voltage of the PGA output node remains stable between Vref_l and Vref_h, thus completing automatic gain locking.
[0048] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. An automatic gain control circuit based on the binary search method, characterized in that, The automatic gain control circuit includes a first peak detection circuit, a second peak detection circuit, a peak judgment logic module, a rising edge detection circuit, and a binary division logic module. The first and second peak detection circuits are respectively connected to the peak judgment logic module, which is connected to the rising edge detection circuit. The second peak detection circuit and the rising edge detection circuit are respectively connected to the binary division logic module. The first and second peak detection circuits are used to compare whether the input signal is within a reference range. The peak judgment logic module is used to generate a judgment signal based on the output levels of the first and second peak detection circuits. The rising edge detection circuit is used to extract the judgment signal and activate the binary division logic module. The binary division logic module is used to generate a gain control word.
2. The automatic gain control circuit based on the binary search method according to claim 1, characterized in that, The first peak detection circuit is used to compare the input signal with a first reference reference, and the second peak detection circuit is used to compare the input signal with a second reference reference, wherein the first reference reference is lower than the second reference reference.
3. The automatic gain control circuit based on the binary search method according to claim 1, characterized in that, The binary logic module is also connected to the clock signal CLK, and is used to shift the signal output of the second peak detection circuit under the control of the clock signal CLK.
4. The control method for an automatic gain control circuit based on the binary search method as described in claim 1, characterized in that, The control method includes the following steps: Connect the input signal Vin and the input reference voltage Vref_l to the input terminal of the first peak detection circuit, and connect the input signal Vin and the input reference voltage Vref_h to the input terminal of the second peak detection circuit, wherein the input reference voltage Vref_l is less than the input reference voltage Vref_lVref_h; When the input signal Vin is higher than the input reference voltage Vref_h and higher than the input reference voltage Vref_l, both the first peak detection circuit and the second peak detection circuit are set to 1, and the peak judgment logic module outputs a high level. When the input signal Vin is higher than the lower input reference voltage Vref_l and lower than the higher input reference voltage Vref_h, the first peak detection circuit is set to 1, the second peak detection circuit is set to 0, and the peak judgment logic module outputs a low level. When the input signal Vin is lower than the input reference voltage Vref_l and lower than the input reference voltage Vref_h, both the first peak detection circuit and the second peak detection circuit are set to 0, and the peak judgment logic module outputs a high level.
5. The control method according to claim 4, characterized in that, The output of the peak judgment logic module is connected to the input of the rising edge detection circuit to determine whether the input signal Vin is lower than or higher than the input reference voltage Vref_l. If a rising edge change is detected at the output of the peak judgment logic module, the set signal at the output of the rising edge detection circuit outputs a high level for one clock cycle.
6. The control method according to claim 5, characterized in that, When the set signal at the output terminal of the rising edge detection circuit goes high, the binary logic module will be activated.
7. The control method according to claim 6, characterized in that, After the binary logic module is started, under the control of the clock signal CLK, the signal at the output terminal of the second peak detection circuit is shifted and output.
8. The control method according to claim 7, characterized in that, The binary logic module uses a 5-bit width to generate a 5-bit gain control word.
9. The control method according to claim 8, characterized in that, The working process of the binary logic module includes: Step 1: When the rising edge detection circuit outputs a high signal (set signal), the binary logic module is reset and outputs a gain control word of 10000. Step 2: Under the control of the clock signal CLK, after the next clock cycle arrives, the signal at the output of the second peak detection circuit is retrieved and transmitted to the highest bit of the 5-bit wide binary logic module. At this time, the 5-bit wide binary logic module outputs the gain control word D51000, where D5 represents the fifth bit output result of the binary logic module, which may be 0 or 1. Step 3: Under the control of the clock signal CLK, after the next clock cycle arrives, the signal at the output of the second peak detection circuit is retrieved again, and the signal is transmitted to the second highest bit of the 5-bit wide binary logic module. At this time, the 5-bit wide binary logic module outputs the gain control word D5D4100, where D4 represents the fourth bit output result of the binary logic module. Step 4: Under the control of the clock signal CLK, after the next clock cycle arrives, the signal at the output of the second peak detection circuit is retrieved again, and the signal is transmitted to the 5-bit wide binary logic module to output the 3rd bit. At this time, the 5-bit wide binary logic module outputs the gain control word D5D4D310, where D3 represents the third bit output result of the binary logic module. Step 5: Under the control of the clock signal CLK, after the next clock cycle arrives, the signal at the output of the second peak detection circuit is retrieved again, and the signal is transmitted to the second lowest bit of the 5-bit wide binary logic module. At this time, the 5-bit wide binary logic module outputs the gain control word D5D4 D3D21, where D2 represents the second bit output result of the binary logic module. Step 6: Under the control of the clock signal CLK, after the next clock cycle arrives, the signal at the output of the second peak detection circuit is retrieved again, and the signal is transmitted to the least significant bit of the 5-bit wide binary logic module. At this time, the 5-bit wide binary logic module outputs the gain control word D5D4 D3D2D1, where D1 represents the first output result of the binary logic module.
10. The control method according to claim 9, characterized in that, After the 5-bit wide binary logic module completes one round of gain adjustment and outputs a stable output signal, the 5-bit wide binary logic module latches the output result D5D4 D3D2D1 until the input signal Vin deviates from the input reference voltage again, that is, it is lower than the input reference voltage Vref_l or higher than the input reference voltage Vref_h, at which point a new round of gain adjustment is performed.