Filter chip packaging structure

Abstract

The invention discloses a filter chip packaging structure. The filter chip packaging structure comprises a substrate and a filter chip which is inversely arranged on the substrate, the filter chip comprises a substrate, and the front surface of the substrate is provided with an interdigital transducer, a supporting wall, an organic dielectric layer, a plurality of metal electrodes and a plurality of electrode leading-out structures. The supporting wall surrounds the interdigital transducer, the organic dielectric layer covers the supporting wall, and the interdigital transducer is located in a cavity defined by the organic dielectric layer and the supporting wall; the metal electrode comprises a signal electrode and a grounding electrode which are respectively connected with the interdigital transducer, and the electrode leading-out structure is used for leading out the signal electrode and the grounding electrode to the top surface of the organic dielectric layer; and a metal covering layer is arranged on the surface of the organic dielectric layer, is connected with the electrode leading-out structure corresponding to the grounding electrode, and is insulated from the electrode leading-out structure corresponding to the signal electrode. According to the invention, while the advantage of miniaturization is maintained, the isolation, power tolerance and reliability of the filter are improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and more specifically, to a filter chip packaging structure. Background Technology

[0002] As consumer electronics products move towards miniaturization, higher frequencies, and greater integration, more stringent requirements are being placed on the performance of the filters used within them. Filters need to achieve higher out-of-band rejection (isolation), greater power handling capability, and better long-term reliability within an extremely small size.

[0003] Wafer-level packaging (WLP) technology has become the mainstream packaging form for filters in consumer electronics due to its small size and excellent electrical performance. However, in traditional WLP filter packaging, the complete ground plane is usually located on the substrate outside the package, resulting in a long ground loop path and a large parasitic inductance. This degrades the filter's out-of-band rejection and isolation performance, limiting its application in high-interference environments. In addition, traditional organic dielectric capping layers have limited barrier capabilities against water and oxygen, and poor heat dissipation paths, affecting the device's reliability and power handling capabilities in harsh environments. Summary of the Invention

[0004] The purpose of this invention is to propose a filter chip packaging structure that improves the isolation, power tolerance, and reliability of the filter while maintaining the advantages of miniaturization.

[0005] To achieve the above objectives, the present invention proposes a filter chip packaging structure, comprising: a substrate and a filter chip flip-chip mounted on the substrate; The filter chip includes a substrate, the side of the substrate facing the substrate is the front side, and the front side of the substrate is provided with an interdigital transducer, a support wall, an organic dielectric layer, multiple metal electrodes and multiple electrode lead-out structures. The support wall surrounds the interdigital transducer, the organic dielectric layer covers the support wall, and the interdigital transducer is located within the cavity formed by the organic dielectric layer and the support wall. The surface of the organic dielectric layer closest to the substrate is the top surface, and the surface of the organic dielectric layer closest to the substrate is the bottom surface; The metal electrode includes a signal electrode and a ground electrode respectively connected to the interdigital transducer, and the electrode lead-out structure includes a method for leading the signal electrode and the ground electrode to the top surface of the organic dielectric layer; The surface of the organic dielectric layer is provided with a metal cover layer, which is connected to the electrode lead-out structure corresponding to the ground electrode and is insulated from the electrode lead-out structure corresponding to the signal electrode.

[0006] Optionally, the metal capping layer is disposed on the top surface of the organic dielectric layer.

[0007] Optionally, the metal capping layer is disposed on the bottom surface of the organic medium layer.

[0008] Optionally, the metal coating layer is disposed on both the top and bottom surfaces of the organic dielectric layer.

[0009] Optionally, the electrode lead-out structures are all metal pillars; the metal pillars penetrate the supporting wall and the organic dielectric layer and are connected to the corresponding metal electrodes; the metal cover layer is connected to the metal pillar corresponding to the ground electrode, but not connected to the metal pillar corresponding to the signal electrode.

[0010] Optionally, the metal capping layer covers the surface of the organic dielectric layer, and a hollowed-out area is formed at the location of the metal pillar corresponding to the signal electrode, exposing the surface of the organic dielectric layer.

[0011] Optionally, the metal capping layer covers the top surface of the organic dielectric layer, the sidewalls of the organic dielectric layer, the sidewalls of the support wall, and the edge region of the front side of the substrate; The metal cover layer includes a first part and a second part that are disconnected. The first part is connected to the electrode lead-out structure corresponding to the ground electrode, and the second part is connected to the electrode lead-out structure corresponding to the signal electrode.

[0012] Optionally, the electrode lead-out structures are all metal traces, and the metal traces are extensions of the metal electrodes; The metal trace corresponding to the ground electrode extends along the front side of the substrate to the outside of the support wall and connects to the first part of the metal cover layer. The metal trace corresponding to the signal electrode extends along the front side of the substrate to the outside of the support wall and connects to the second part of the metal cover layer.

[0013] Optionally, the electrode lead-out structure includes both a metal pillar and a metal trace, wherein the metal trace is an extension of the signal electrode; The metal column penetrates the supporting wall and the organic dielectric layer and is connected to the corresponding grounding electrode; the first part of the metal covering layer is connected to the metal column. The metal trace corresponding to the signal electrode extends along the front side of the substrate to the outside of the support wall and connects with the second part of the metal cover layer.

[0014] Optionally, a portion of the plurality of grounding electrodes is connected to the metal cover layer through the grounding electrode lead-out structure, while another portion of the grounding electrodes is grounded separately through the substrate or left suspended.

[0015] Optionally, the metal coating is fabricated by photolithography, deposition, or electroplating. Alternatively, the metal overlay is a patterned metal film layer, which is bonded to the surface of the organic dielectric layer.

[0016] Optionally, the substrate is provided with signal pads and ground pads, and the electrode lead-out structures corresponding to the signal electrode and the ground electrode are respectively connected to the corresponding signal pads and ground pads through connecting metals.

[0017] The beneficial effects of this invention are as follows: (1) The present invention connects the metal cover layer and the ground electrode through the electrode lead-out structure, so that the height of the complete ground plane is reduced from the traditional substrate layer to the chip layer, which greatly reduces the loop area and loop parasitics, and significantly improves the out-of-band isolation performance and electromagnetic interference resistance of the filter. (2) A large area of ​​metal covering layer is well grounded to form a closed metal shield cavity on the chip surface, which effectively blocks external electromagnetic interference and prevents leakage of electromagnetic signals inside the chip. (3) By optimizing the grounding performance, the number of required grounding pins is reduced, and the metal overlay layer does not need to rely on the fixed position of the metal pillar, making the chip layout more flexible, further reducing the chip size, and improving the chip area utilization. (4) The extreme water and oxygen barrier properties of metals enable the covered area of ​​the metal coating to form a protective barrier, effectively reducing the water vapor intrusion channel and thus improving the product's resistance to water vapor. (5) By using a large area of ​​metal covering layer, the heat dissipation area is increased, allowing the heat inside the chip to be discharged faster and the device temperature to be reduced. On the other hand, the heat distribution is more uniform, avoiding local high temperature accumulation, thereby improving the power tolerance of the device.

[0018] The present invention has other features and advantages, which will be apparent from or will be set forth in detail in the accompanying drawings and the following detailed description, which together serve to explain the particular principles of the invention. Attached Figure Description

[0019] The above and other objects, features and advantages of the present invention will become more apparent from the accompanying drawings, in which like reference numerals generally denote like parts.

[0020] Figure 1 This is a cross-sectional view (along the direction of) a filter chip packaging structure according to Embodiment 1 of the present invention. Figure 2 (Position of the middle dashed line).

[0021] Figure 2 for Figure 1 Bottom view of the area within the dashed box (captured at the metal overlay).

[0022] Figure 3 for Figure 1 The figure shows a simulation comparison of filter performance between a package structure with a metal cover and a package structure without a metal cover.

[0023] Figure 4 This is a cross-sectional view (along the direction of) a filter chip packaging structure according to Embodiment 2 of the present invention. Figure 5 (position of the middle dashed line) Figure 5 for Figure 4 Bottom view of the area within the dashed box (captured at the organic media layer)

[0024] Figure 6 This is a cross-sectional view of a filter chip packaging structure according to Embodiment 3 of the present invention.

[0025] Figure 7 This is a cross-sectional view (along the direction of) a filter chip packaging structure according to Embodiment 4 of the present invention. Figure 8 (Position of the middle dashed line).

[0026] Figure 8 for Figure 7 Bottom view of the section within the dashed box (captured at the connecting metal).

[0027] Figure 9 This is a cross-sectional view (along the direction of) a filter chip packaging structure according to Embodiment 5 of the present invention. Figure 10 (Position of the middle dashed line).

[0028] Figure 10 for Figure 9 Bottom view of the area within the dashed box (captured at the connecting metal). Detailed Implementation

[0029] The invention will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the invention will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0030] Example 1

[0031] Figure 1 This is a cross-sectional view (along the direction of the filter chip packaging structure in this embodiment) Figure 2 (position of the middle dashed line) Figure 2 for Figure 1 The bottom view of the area within the dashed box (captured at metal overlay 9), as shown... Figure 1 and Figure 2 As shown, this embodiment provides a filter chip packaging structure, including: a substrate 11 and a filter chip flip-chip mounted on the substrate 11; The filter chip includes a substrate 1, the side of the substrate 1 facing the substrate 11 is the front side, and the front side of the substrate 1 is provided with an interdigital transducer 2, a support wall 3, an organic dielectric layer 4, multiple metal electrodes and multiple electrode lead-out structures. The support wall 3 surrounds the interdigital transducer 2, the organic dielectric layer 4 covers the support wall 3, and the interdigital transducer 2 is located in the cavity formed by the organic dielectric layer 4 and the support wall 3. The surface of the organic dielectric layer 4 closest to the substrate 11 is the top surface, and the surface of the organic dielectric layer closest to the substrate 1 is the bottom surface. The metal electrode includes a signal electrode 5 and a ground electrode 6 connected to the interdigital transducer 2, and the electrode lead-out structure is used to lead the signal electrode 5 and the ground electrode 6 to the top surface of the organic dielectric layer 4. The top surface of the organic dielectric layer 4 is provided with a metal cover layer 9, which is connected to the lead-out structure corresponding to the ground electrode 6 and is insulated from the lead-out structure corresponding to the signal electrode.

[0032] In this embodiment, the electrode lead-out structures are all metal pillars 7; the metal pillars 7 penetrate the supporting wall 3 and the organic dielectric layer 4 and are connected to the corresponding metal electrodes; the metal capping layer 9 is connected to the metal pillar 7 corresponding to the ground electrode 6, but not connected to the metal pillar 7 corresponding to the signal electrode 5. The metal capping layer 9 covers the top surface of the organic dielectric layer 4, and forms a hollow area exposed on the surface of the organic dielectric layer 4 at the location of the metal pillar 7 corresponding to the signal electrode 5.

[0033] Optionally, both the metal pillars and the metal covering layer 9 are made of copper or other metal materials. The organic dielectric layer 4 and the supporting wall 3 can be made of photosensitive organic materials such as dry film, which can be manufactured through a patterning process.

[0034] In this embodiment, the metal capping layer 9 can be formed on the organic dielectric layer 4 through photolithography and deposition processes, or it can be fabricated through electroplating. This method can cover not only the surface of the organic dielectric layer 4, but also the entire front side of the chip, including the sidewalls of the organic dielectric layer 4, the surface edges and sidewalls of the support wall 3, and the edge area of ​​the front side of the substrate 1, achieving large-area metal coverage. In other embodiments, the metal capping layer 9 can also be a patterned metal film (such as copper foil), which is formed by bonding the metal film to the surface of the organic dielectric layer 4.

[0035] In this embodiment, the substrate 11 is provided with signal pads 12 and ground pads 13. The metal pillars 7 corresponding to the signal electrode 5 and the ground electrode 6 are respectively connected to the corresponding signal pads 12 and ground pads 13 through connecting metal 10 (such as solder balls).

[0036] The packaging structure in this embodiment uses metal pillars as electrode lead-out structures to lead out the chip's signal and ground to the top surface of the organic dielectric layer 4. Then, through photolithography, deposition, and other processes, a metal film layer is coated on the device surface in areas other than the signal lead-out pins to form a metal capping layer 9, which connects all the ground metal pillars 7, thereby obtaining the following advantages: 1. The metal cover layer 9 covering the surface of the device and the ground connection led out from the chip can reduce the height of the complete ground plane from the substrate layer to the chip layer, reduce the loop area and parasitic loops, improve the out-of-band and isolation performance of the product, and enhance its anti-interference capability.

[0037] 2. Extensive metal coverage and good grounding can form an effective metal shielding cavity on the chip surface, thereby improving the product's electromagnetic shielding capability.

[0038] 3. Improved grounding performance can increase the flexibility of chip layout, reduce the number of grounding pins, reduce chip size, and improve chip area utilization.

[0039] 4. Metals have excellent water and oxygen barrier properties. Large-area metal coverage effectively reduces the area for water vapor intrusion, thereby improving the product's resistance to water vapor. 5. Metals have excellent thermal conductivity. Large-area metal coverage increases the heat dissipation area, allowing heat to be dissipated from the chip more quickly and reducing the device temperature. On the other hand, it also makes the heat distribution more uniform, avoiding local high temperature accumulation, thereby improving the power tolerance of the device.

[0040] 6. The packaging structure of this embodiment is easy to implement based on existing processes. It can be completed simply by adding a metal cover layer 9 (metal deposition or electroplating) after the basic packaging structure (including SAW chip, metal pillar 7, support wall 3 and organic dielectric layer 4) is made.

[0041] like Figure 3 As shown in the figure, the dark curve is Figure 1 The simulation performance of the package structure shown is represented by the light-colored curve. Figure 1 The simulation performance of the package structure shown without the metal cover layer 9 shows that adding the metal cover layer 9 improves the grounding performance of the filter chip and greatly enhances its out-of-band performance and isolation performance.

[0042] Example 2

[0043] Figure 4 This is a cross-sectional view (along the direction of the filter chip packaging structure in this embodiment) Figure 5 (position of the middle dashed line) Figure 5 for Figure 4The bottom view of the area within the dashed box (captured at organic media layer 4), as shown... Figure 4 and Figure 5 As shown, the packaging structure of this embodiment is basically the same as the basic structure of embodiment 1, and it also uses metal pillars 7 as electrode lead-out structures. The difference is that the metal cover layer 9 in this embodiment is disposed on the bottom surface of the organic dielectric layer 4, that is, the side surface close to the substrate 1. The metal cover layer 9 continuously covers the bottom surface of the organic dielectric layer 4 and is only connected to the metal pillars 7 corresponding to the ground electrode. A hollow area is formed at the location of the metal pillars 7 corresponding to the signal electrode 5, exposing the surface of the organic dielectric layer 4, so as to achieve insulation between the metal pillars 7 corresponding to the signal electrode.

[0044] Specifically, this implementation is different from Example 1 ( Figure 1 The position of the metal cover layer 9 in the structure shown has been adjusted, as follows: Figure 4 and Figure 5 As shown, a metal capping layer 9 is disposed on the bottom surface of the organic dielectric layer 4. The metal capping layer 9 is connected to all the metal pillars 7 corresponding to the ground electrode 6, but not connected to all the metal pillars 7 corresponding to the signal electrode 5. This makes the height of the complete ground plane closer to the chip, further improving the grounding performance of the product and obtaining better out-of-band performance.

[0045] Example 3

[0046] Figure 6 This is a cross-sectional view of a filter chip packaging structure according to this embodiment (the bottom view of the dashed box portion can be referenced). Figure 2 ),like Figure 6 As shown, this embodiment also uses metal pillars 7 as electrode lead-out structures. The difference from Embodiment 1 and Embodiment 2 is that in this embodiment, metal covering layers 9 are provided on both sides of the top and bottom surfaces of the organic dielectric layer 4. Both metal covering layers 9 are connected to the metal pillars 7 corresponding to the ground electrode 6, and are not connected to the metal pillars 7 corresponding to the signal electrode 5.

[0047] Specifically, although Example 2 ( Figure 4 The encapsulation structure shown can further reduce the height of the ground plane and improve out-of-band performance. However, since the metal cover layer 9 is located inside the organic dielectric layer 4, the metal coverage area is reduced and there is no metal cover on the outside of the organic dielectric layer 4. Therefore, the structure of Example 2 is different from that of Example 1. Figure 1 The structure shown will have numerous electromagnetic leakage channels and moisture intrusion channels, which will reduce reliability to some extent. Therefore, the packaging structure of this embodiment ( Figure 6 The structure shown combines Embodiment 1 and Embodiment 2, and simultaneously provides a metal cover layer 9 on the top and bottom surfaces of the organic dielectric layer 4. By combining the advantages of both, the product's grounding performance is improved, while its airtightness and heat dissipation capacity are increased, thereby improving its reliability.

[0048] Example 4

[0049] Figure 7 This is a cross-sectional view (along the direction of the filter chip packaging structure in this embodiment) Figure 8 (position of the middle dashed line) Figure 8 for Figure 7 The bottom view of the section within the dashed box (captured at connecting metal 10), as shown below. Figure 7 and Figure 8 As shown, the difference between the filter chip packaging structure of this embodiment and that of the above embodiment 1 is that, in this embodiment, the metal cover layer 9 is only disposed on the top surface of the organic cover layer 4, and the metal cover layer 9 covers the top surface of the organic dielectric layer 4, the sidewall of the organic dielectric layer 4, the sidewall of the support wall 3, and the edge area of ​​the front side of the substrate 1; the metal cover layer 9 includes a first part 91 and a second part 92 that are disconnected, the first part 91 is connected to the electrode lead-out structure corresponding to the ground electrode 6, and the second part is connected to the electrode lead-out structure corresponding to the signal electrode 5.

[0050] In this embodiment, the electrode lead-out structures are all metal traces 8, which are extensions of the metal electrodes. The metal trace 8 corresponding to the ground electrode 6 extends along the front side of the substrate 1 to the outside of the support wall 3 and connects with the first part 91 of the metal cover layer 9. The metal trace 8 corresponding to the signal electrode 5 extends along the front side of the substrate 1 to the outside of the support wall 3 and connects with the second part 92 of the metal cover layer 9.

[0051] Specifically, this embodiment ( Figure 7 The structure shown) and Example 1 ( Figure 1 Compared to the structure shown, metal pillar 7 was removed. Figure 7 (In the dashed section), the electrode lead-out structure of signal electrode 5 and ground electrode 6 has been changed from the original metal pillars to metal trace connections. The metal electrodes on the surface of substrate 1 are extended by metal traces 8, extending them beyond the support wall 3. The metal trace 8 corresponding to ground electrode 6 is connected to the first part 91 of the metal cover layer 9 outside the organic dielectric layer 4, and the metal trace 8 corresponding to signal electrode 5 is directly connected to the second part 92 of the metal cover layer 9 outside the organic dielectric layer 4. In this way, the metal pillars can be removed, making the layout more flexible. At the same time, the removal of the metal pillars used for electrical leads also helps to reduce chip size and improve chip utilization. Meanwhile, the connection metal 10 is not limited by the position of the metal pillars and can be more flexibly set on the metal cover layer 9 on the top surface of the organic dielectric layer 4.

[0052] This embodiment also possesses all the advantages of the structure in Embodiment 1: 1. The connection between the covered metal and the ground electrode 6 led out from the substrate 1 can reduce the height of the complete ground plane from the substrate layer to the chip layer, reduce the loop area and parasitic loops, improve the out-of-band and isolation performance of the product, and enhance its anti-interference capability.

[0053] 2. Extensive metal coverage and good grounding can form an effective metal shielding cavity on the chip surface, thereby improving the product's electromagnetic shielding capability.

[0054] 3. Removing metal lead-out pillars further improves the flexibility of chip layout, reduces the number of grounding pins, reduces chip size, and improves chip area utilization.

[0055] 4. Metals have excellent water and oxygen barrier properties. Large-area metal coverage effectively reduces the area for water vapor intrusion, thereby improving the product's resistance to water vapor. 5. Metals have excellent thermal conductivity. Large-area metal coverage increases the heat dissipation area, allowing heat to be dissipated from the chip more quickly and reducing the device temperature. On the other hand, it also makes the heat distribution more uniform, avoiding local high temperature accumulation, thereby improving the power tolerance of the device.

[0056] Furthermore, the metal trace method used in this embodiment is also applicable to the packaging structures of Embodiments 2 and 3.

[0057] Example 5

[0058] Figure 9 This is a cross-sectional view (along the direction of the filter chip packaging structure in this embodiment) Figure 10 (position of the middle dashed line) Figure 10 for Figure 9 The bottom view of the section within the dashed box (captured at connecting metal 10), as shown below. Figure 9 and Figure 10 As shown, the filter chip packaging structure of this embodiment is the same as that of embodiment 4. In this embodiment, the metal cover layer 9 is only disposed on the top surface of the organic cover layer 4. The metal cover layer 9 covers the top surface of the organic dielectric layer 4, the sidewall of the organic dielectric layer 4, the sidewall of the support wall 3, and the edge area of ​​the front side of the substrate 1. The metal cover layer 9 includes a first part 91 and a second part 92 that are disconnected. The first part 91 is connected to the electrode lead-out structure corresponding to the ground electrode 6, and the second part is connected to the electrode lead-out structure corresponding to the signal electrode 5.

[0059] The difference from Embodiment 4 is that the electrode lead-out structure in this embodiment includes both a metal pillar 7 and a metal trace 8, with the metal trace 8 being an extension of the signal electrode 5; the metal pillar 7 penetrates the support wall 3 and the organic dielectric layer 4 and is connected to the corresponding ground electrode 6, and the first part 91 of the metal cover layer 9 is connected to the metal pillar 7; the metal trace 8 corresponding to the signal electrode 5 extends along the front side of the substrate 1 to the outside of the support wall 3 and is connected to the second part of the metal cover layer 9.

[0060] Specifically, in Example 4, this embodiment... Figure 8 Based on the structure shown, the electrode lead-out structure simultaneously employs metal pillars and metal electrode extensions, with metal traces 8 connecting to the external metal covering layer 9, as shown. Figure 9 As shown, in this embodiment, the electrode lead-out structures corresponding to the signal electrode 5 all adopt metal traces 8, and the electrode lead-out structures corresponding to the ground electrode 6 all adopt metal pillars 7. The parallel connection between the electrode lead-out structures using metal pillars 7 and metal traces 8 and the external metal covering layer 9 not only possesses the advantages of the structure in Embodiment 1, but also helps to reduce parasitic inductance.

[0061] Example 6

[0062] This embodiment provides a filter chip packaging structure. Based on any of the packaging structures in embodiments 1-5 above, a portion of the multiple ground electrodes 6 are connected to the metal cover layer 9 through the corresponding electrode lead-out structure (metal pillar 7 or metal trace 8), while the other portion of the ground electrodes 6 are grounded separately through the substrate 11 or left floating.

[0063] Specifically, in embodiments 1-5 above, the metal capping layer 9 is connected to all ground electrodes 6 led out from the chip in order to effectively reduce the height of the ground plane and reduce loop parasitics. However, sometimes, in order to introduce specific parasitics and improve local performance (such as increasing the parasitic inductance of grounding, creating an out-of-band resonant zero), the metal capping layer 9 may only connect to some of the ground electrodes 6, and the unconnected electrodes may be grounded separately through the substrate 11, or left floating, etc.

[0064] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

Claims

1. A filter chip packaging structure, characterized in that, include: A substrate and a filter chip flip-chip on the substrate; The filter chip includes a substrate, the side of the substrate facing the substrate is the front side, and the front side of the substrate is provided with an interdigital transducer, a support wall, an organic dielectric layer, multiple metal electrodes and multiple electrode lead-out structures. The support wall surrounds the interdigital transducer, the organic dielectric layer covers the support wall, and the interdigital transducer is located within the cavity formed by the organic dielectric layer and the support wall. The surface of the organic dielectric layer closest to the substrate is the top surface, and the surface of the organic dielectric layer closest to the substrate is the bottom surface; The metal electrode includes a signal electrode and a ground electrode respectively connected to the interdigital transducer, and the electrode lead-out structure is used to lead the signal electrode and the ground electrode to the top surface of the organic dielectric layer; The surface of the organic dielectric layer is provided with a metal cover layer, which is connected to the electrode lead-out structure corresponding to the ground electrode and is insulated from the electrode lead-out structure corresponding to the signal electrode.

2. The filter chip packaging structure according to claim 1, characterized in that, The metal capping layer is disposed on the top surface of the organic medium layer.

3. The filter chip packaging structure according to claim 1, characterized in that, The metal capping layer is disposed on the bottom surface of the organic medium layer.

4. The filter chip packaging structure according to claim 1, characterized in that, The metal capping layer is disposed on both the top and bottom surfaces of the organic medium layer.

5. The filter chip packaging structure according to any one of claims 1-3, characterized in that, All electrode lead-out structures are metal pillars; The metal column penetrates the supporting wall and the organic dielectric layer and is connected to the corresponding metal electrode; The metal cover layer is connected to the metal post corresponding to the ground electrode, but not to the metal post corresponding to the signal electrode.

6. The filter chip packaging structure according to any one of claims 2-4, characterized in that, The metal capping layer covers the surface of the organic dielectric layer, and a hollowed-out area is formed at the location of the metal pillar corresponding to the signal electrode, exposing the surface of the organic dielectric layer.

7. The filter chip packaging structure according to claim 2, characterized in that, The metal capping layer covers the top surface of the organic dielectric layer, the sidewalls of the organic dielectric layer, the sidewalls of the support wall, and the edge region of the front side of the substrate; The metal cover layer includes a first part and a second part that are disconnected. The first part is connected to the electrode lead-out structure corresponding to the ground electrode, and the second part is connected to the electrode lead-out structure corresponding to the signal electrode.

8. The filter chip packaging structure according to claim 7, characterized in that, The electrode lead-out structures are all metal traces, and the metal traces are extensions of the metal electrodes; The metal trace corresponding to the ground electrode extends along the front side of the substrate to the outside of the support wall and connects to the first part of the metal cover layer. The metal trace corresponding to the signal electrode extends along the front side of the substrate to the outside of the support wall and connects to the second part of the metal cover layer.

9. The filter chip packaging structure according to claim 7, characterized in that, The electrode lead-out structure includes both metal pillars and metal traces, wherein the metal traces are extensions of the signal electrode. The metal column penetrates the supporting wall and the organic dielectric layer and is connected to the corresponding grounding electrode; the first part of the metal covering layer is connected to the metal column. The metal trace corresponding to the signal electrode extends along the front side of the substrate to the outside of the support wall and connects with the second part of the metal cover layer.

10. The filter chip packaging structure according to any one of claims 1-4, characterized in that, A portion of the plurality of grounding electrodes is connected to the metal cover layer through the grounding electrode lead-out structure, while the other portion of the grounding electrodes is grounded individually through the substrate or suspended.

11. The filter chip packaging structure according to any one of claims 1-4, characterized in that, The metal coating is fabricated by photolithography, deposition, or electroplating. Alternatively, the metal overlay is a patterned metal film layer, which is bonded to the surface of the organic dielectric layer.

12. The filter chip packaging structure according to claims 1-4, characterized in that, The substrate is provided with signal pads and ground pads, and the electrode lead-out structures corresponding to the signal electrode and the ground electrode are respectively connected to the corresponding signal pads and ground pads through connecting metal.

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