Response current monitoring circuit for silicon-based optical receiver chip integrated photodiode

Abstract

The application discloses a kind of for silicon-based optical receiver chip integrated photodiode response current monitoring circuit, belong to optical communication integrated circuit technical field, it includes transimpedance current detection unit, AGC current detection unit and current summation and output unit.The architecture is matched by voltage clamping and proportional device, respectively replicates transimpedance branch and AGC branch current, and is summed according to uniform proportion, and the monitoring current of linear relationship with original light response current is output.The application does not interfere with main signal path, does not introduce front-end noise, is suitable for CMOS / BiCMOS etc.standard process, and high-precision monitoring and receiver sensitivity are considered.

Description

Technical Field

[0001] This invention belongs to the field of optical communication integrated circuit technology, specifically, it relates to a photodiode response current monitoring circuit for silicon-based optical receiver chips. Background Technology

[0002] In modern optical communication and optical control applications, the optical receiver is a key component, and its performance directly affects the reliability and applicability of the system. A typical optical receiver architecture usually consists of two parts: a signal path and an optical response current detection circuit. The signal path uses a photodiode (PD) or an avalanche photodiode (APD) to convert the incident non-return-to-zero (NRZ) optical signal into a weak current signal, which is then amplified and shaped staged through a transimpedance amplifier (TIA), a gain stage (GAIN), and a driver stage (DRIVER) before being output. The optical response current detection circuit is used to monitor the response current generated by the photodiode to estimate the input optical power or calibrate the device responsivity, which is of great significance for system link monitoring, fault diagnosis, and production testing.

[0003] Currently, high-performance optical receiving systems mostly employ discrete photodiodes manufactured using special processes (such as germanium-silicon (GeSi) or gallium arsenide (GaAs)). These photodiodes have independently biased anodes and cathodes, facilitating high-precision current monitoring through operational amplifier clamping and current mirroring techniques. A typical solution is as follows: Figure 1 As shown. However, with the increasing demand for high electrical isolation, strong anti-interference capabilities, low cost, and high reliability in fields such as industrial automation, automotive electronics, and power management, photodiodes integrated based on standard silicon-based processes (such as CMOS or BiCMOS) are being widely used in low-speed, short-range (typically with a rate below 625MHz and a sensitivity below -30dBm) optical communication scenarios due to their advantages such as no need for additional processes and easy monolithic integration with back-end analog / digital circuits.

[0004] In standard CMOS or BiCMOS processes, there are two main types of achievable integrated photodiodes: one type uses a P+ injection region and an N-well to form the anode and cathode. While this type offers bias flexibility similar to discrete devices, its responsivity is typically below 0.1 A / W due to structural limitations, severely restricting receiver sensitivity. The other type uses a P-type substrate as the anode and an N-well as the cathode. This structure inherently requires the anode to be grounded to maintain substrate potential stability, while the cathode is directly connected to the TIA input to optimize the signal-to-noise ratio. For example... Figure 2 As shown, although this type of structure can provide a relatively high responsivity, the photoresponse current cannot be directly extracted for monitoring because the anode is fixedly grounded, and the traditional detection method based on cathode current mirror is no longer applicable.

[0005] For the latter, existing technologies propose a scheme that uses a common-gate NMOS transistor to provide reverse bias to the photodiode and utilizes a PMOS current mirror to replicate the photogenerated current to the monitoring terminal (e.g., Figure 3 (As shown). However, this method forces the photodiode cathode to be directly connected to the MOS source, causing the inherent thermal noise and 1 / f noise of the MOS device to be directly superimposed on the weak photoresponse current, significantly degrading the input signal-to-noise ratio and thus reducing the overall sensitivity of the receiver. Therefore, while achieving silicon-based integrated photodiode response current monitoring, existing technologies struggle to simultaneously meet the requirements of key receiver performance indicators—especially sensitivity.

[0006] In summary, there is an urgent need for a novel current monitoring circuit architecture capable of accurately detecting the response current generated by a silicon-based integrated photodiode with a P-type substrate as the anode, an N-well as the cathode, and the anode grounded, without introducing additional noise or affecting signal path performance. This architecture must be compatible with mainstream CMOS / BiCMOS processes, suitable for modern optical receivers with complex functions such as automatic gain control (AGC), and extendable to differential signal link structures. This will meet the pressing needs of high-reliability applications in industrial and automotive electronics for highly integrated, low-power, and robust optical receiver chips. Summary of the Invention

[0007] The purpose of this invention is to provide a monitoring circuit for the response current of an integrated photodiode in a silicon-based optical receiver chip, which mainly solves the problem that existing technologies sacrifice sensitivity, a key performance indicator of optical receivers, when detecting the response current of integrated photodiodes.

[0008] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0009] A photodiode response current monitoring circuit for silicon-based optical receiver chips includes:

[0010] A transimpedance current detection unit is used to detect the current I_RT flowing through the transimpedance RT in a silicon-based optical receiving signal link;

[0011] The AGC small current detection unit is used to detect the current I_NS flowing through the NS transistor and the current I_NM flowing through the NM transistor in the silicon-based optical receiving signal link.

[0012] The AGC high-current detection unit is used to detect the current I_NL flowing through the NL tube in the silicon-based optical receiving signal link;

[0013] The current summation and output unit is used to sum the detected currents I_RT, I_NS, I_NM, and I_NL according to a set uniform scaling factor, and output a monitoring current that is linearly related to the original response current I_PD of the photodiode.

[0014] Furthermore, in this invention, the transimpedance current detection unit includes operational amplifier OP5, operational amplifier OP6, NMOS transistor N9, NMOS transistor N10, NMOS transistor N11, PMOS transistor P6, resistor RT_M, and current sink IS3, wherein:

[0015] Operational amplifier OP5 has its non-inverting input connected to the filtered level signal V_TIA_OUT_LPF extracted from the TIA output node in the silicon-based optical signal receiving link. Its output drives the gate of NMOS transistor N9, and its inverting input is connected to the source of NMOS transistor N9. The drain of NMOS transistor N9 is connected to VDD, and the source of NMOS transistor N9 is also connected to one end of resistor RT_M and the input of current sink IS3. The output of current sink IS3 is grounded.

[0016] Operational amplifier OP6 has its non-inverting input connected to a filtered level signal V_IN_LPF extracted from the TIA input node in the silicon-based optical signal receiving link. Its output drives the gate of PMOS transistor P6, and its inverting input is connected to the other end of resistor RT_M and the source of PMOS transistor P6. The drain of PMOS transistor P6 is connected to the drain of NMOS transistor N10. The gate of NMOS transistor N10 is connected to the gate of NMOS transistor N11. The sources of NMOS transistor N10 and NMOS transistor N11 are both grounded. The drain of NMOS transistor N10 is connected to its gate. The drain of NMOS transistor N11 outputs a mirrored current I_R.

[0017] Furthermore, in this invention, the AGC low-current detection unit includes an operational amplifier OP3 whose non-inverting input is connected to an operational amplifier OP3 that extracts a filtered level signal V_X_LPF from any node in the silicon-based optical receiving signal link; an NMOS transistor N3 whose gate is connected to the output of operational amplifier OP3 and whose drain is connected to VDD; a current sink IS1 whose input is connected to the inverting input of operational amplifier OP3 and the source of NMOS transistor N3, and whose output is grounded; an NMOS transistor NS_M whose drain is connected to the source of NMOS transistor N3; an NMOS transistor NM_M whose drain is connected to the source of NMOS transistor N3; an operational amplifier OP4 whose inverting input is connected to the sources of both NMOS transistors NS_M and NM_M; and a PMO whose gate is connected to the output of operational amplifier OP4 and whose source is connected to the inverting input of operational amplifier OP4. The system consists of an S-channel transistor P4, an NMOS transistor N4 whose drain is connected to the drain of PMOS transistor P4 and whose source is grounded, and an NMOS transistor N5 whose gate is connected to the gate of NMOS transistor N4 and whose source is grounded. The gate of NMOS transistor N4 is connected to its drain. The gate of NMOS transistor NS_M is connected to the level signal V_AGC1, which is the level signal of the control voltage AGC1 output by the automatic gain control module AGC in the silicon-based optical receiving signal link after RC filtering. The gate of NMOS transistor NM_M is connected to the level signal V_AGC2, which is the level signal of the control voltage AGC2 output by the automatic gain control module AGC in the silicon-based optical receiving signal link after RC filtering. The non-inverting input of operational amplifier OP4 is connected to the level signal V_IN_LPF, which is the level signal extracted from the response current outflow node in the silicon-based optical receiving signal link after filtering. The drain of NMOS transistor N5 outputs the detection current I_AGC1.

[0018] Furthermore, in this invention, the AGC high-current detection unit includes an operational amplifier OP7 whose non-inverting input is connected to an operational amplifier OP7 that extracts a filtered level signal V_X_LPF from any node in the silicon-based optical receiving signal link; an NMOS transistor N6 whose gate is connected to the output of operational amplifier OP7 and whose drain is connected to VDD; a current sink IS2 whose input is connected to the inverting input of operational amplifier OP7 and the source of NMOS transistor N6, and whose output is grounded; an NMOS transistor NL_M whose drain is connected to the source of NMOS transistor N6; an operational amplifier OP8 whose inverting input is connected to the source of NMOS transistor NL_M; and an operational amplifier OP8 whose gate is connected to the output of operational amplifier OP8 and whose source is connected to operational amplifier OP8. The system consists of a PMOS transistor P5 connected to the inverting input terminal, an NMOS transistor N7 whose drain is connected to the drain of PMOS transistor P5 and whose source is grounded, and an NMOS transistor N8 whose gate is connected to the gate of NMOS transistor N7 and whose source is grounded. The gate of NMOS transistor N7 is connected to its drain. The gate of NMOS transistor NL_M is connected to the level signal V_AGC3, which is the level signal of the control voltage AGC3 output by the automatic gain control module AGC in the silicon-based optical receiving signal link after RC filtering. The non-inverting input terminal of operational amplifier OP8 is connected to the level signal V_IN_LPF, which is the level signal extracted from the response current outflow node in the silicon-based optical receiving signal link after filtering. The drain of NMOS transistor N8 outputs the detection current I_AGC2.

[0019] Further, in this invention, the current summation and output unit includes a PMOS transistor P7 whose drain is connected to the drain of NMOS transistor N5 and whose source is connected to VDD; a resistor R12 connected at one end to the gate of PMOS transistor P7; a capacitor C12 connected at one end to the other end of resistor R12 and at the other end to the source of PMOS transistor P7; a PMOS transistor P8 whose gate is connected to the common terminal of resistor R12 and capacitor C12 and whose source is connected to VDD; a PMOS transistor P9 whose drain is connected to the drain of NMOS transistor N8 and whose source is connected to VDD; a resistor R10 connected at one end to the gate of PMOS transistor P9; a capacitor C10 connected at one end to the other end of resistor R10 and at the other end to the source of PMOS transistor P9; and a gate connected to resistor R10. The PMOS transistor P10 is connected to the common terminal of capacitor C10 and its source is connected to VDD; the PMOS transistor P11 is connected to the drain of NMOS transistor N11 and its source is connected to VDD; a resistor R11 is connected to the gate of PMOS transistor P11; a capacitor C11 is connected to the other end of resistor R11 and the other end of PMOS transistor P11; and a PMOS transistor P12 is connected to the common terminal of resistor R11 and capacitor C11 and its source is connected to VDD. Among these, the gate and drain of PMOS transistor P7 are connected, the gate and drain of PMOS transistor P9 are connected, the gate and drain of PMOS transistor P11 are connected, and the drain of PMOS transistor P8 is connected to the drain of PMOS transistor P10 and the drain of PMOS transistor P12.

[0020] Furthermore, in this invention, the value of the resistor RT_M is 1 / K1 times the transresistance RT.

[0021] Furthermore, in this invention, the NMOS transistors N11 and NMOS transistors N10 constitute a mirror transistor with a mirror ratio of K2.

[0022] Furthermore, in this invention, the gate width and gate length of the NMOS transistors NS_M and NM_M are respectively proportional to the NS transistor and NM transistor in the silicon-based optical receiving signal link, which is K3. The NMOS transistors N4 and N5 constitute mirror transistors with a mirror ratio of K4.

[0023] Furthermore, in this invention, the ratio of the NMOS transistor NL_M to the NL transistor in the silicon-based optical receiving signal link is K5, and the NMOS transistors N7 and N8 constitute a mirror transistor with a mirror ratio of K6.

[0024] Furthermore, in this invention, PMOS transistors P7 and P8 form a mirror transistor with a mirror ratio of K9; PMOS transistors P9 and P10 form a mirror transistor with a mirror ratio of K8; and PMOS transistors P11 and P12 form a mirror transistor with a mirror ratio of K7.

[0025] Compared with the prior art, the present invention has the following beneficial effects:

[0026] (1) This invention achieves linear reconstruction of the original photoresponse current I_PD through the collaborative design of the transimpedance current detection unit, the AGC small current detection unit, the AGC large current detection unit, and the current summation unit. This scheme does not insert any active device between the photodiode cathode and the TIA input, nor does it change the grounding structure of the PD in the main path, effectively avoiding the impact on the noise performance of the main signal link, ensuring that the receiver sensitivity is not interfered with by the monitoring circuit, and taking into account both high-precision monitoring and the core performance indicators of the receiver.

[0027] (2) This invention employs voltage clamping technology and proportional device matching design to ensure that the V_GS and V_DS of the replica device in each detection unit are completely consistent with the original device, and can maintain high-precision current replication even under process corner, temperature and power fluctuation conditions. At the same time, the AGC small current and large current detection units adopt differentiated proportional coefficients (such as K3 taking 1 / 2 and K5 taking 1 / 10), which significantly reduces static power consumption while ensuring monitoring linearity. The power consumption is further optimized when the AGC branch is turned off in low light scenarios, meeting the requirements of low power consumption applications.

[0028] (3) This invention can be compatible with both single-ended and differential signal links by adjusting the circuit structure of the transimpedance current detection unit, making it highly versatile. In addition, the monitoring circuit only uses basic CMOS / BiCMOS standard process components (MOS transistors, operational amplifiers, resistors and capacitors), without the need for special processes. It is easy to integrate with the back-end analog / digital circuits on a single chip, reducing chip production costs and system complexity. It is suitable for scenarios with high integration and high reliability requirements, such as industrial automation and automotive electronics. Attached Figure Description

[0029] Figure 1 This is a typical photodiode current detection architecture in existing receivers.

[0030] Figure 2 This is a typical architecture for a photodiode cathode connected to a transimpedance amplifier in existing technology.

[0031] Figure 3 This is a typical current sensing architecture for photodiodes using P-type substrates and N-wells in the prior art.

[0032] Figure 4 This is a typical signal link architecture in existing technologies where the cathode of a photodiode is connected to the TIA input and the anode is grounded.

[0033] Figure 5 This is a schematic diagram of the transimpedance current detection unit of the present invention, in which the photoresponse current flows into the transimpedance RT.

[0034] Figure 6 This is a schematic diagram of the AGC small current detection unit for the photoresponse current flowing into the NS and NM transistors of the present invention.

[0035] Figure 7 This is a schematic diagram of the AGC high current detection unit for the photoresponse current flowing into the NL tube according to the present invention.

[0036] Figure 8 This is the schematic diagram of the current summation and output unit in this invention.

[0037] Figure 9 This is a typical architecture of a differential signal link in the existing technology, where the cathode of a photodiode is connected to the TIA input and the anode is grounded.

[0038] Figure 10 For the adaptation in this invention Figure 9 A schematic diagram of the transimpedance current detection unit. Detailed Implementation

[0039] The present invention will be further described below with reference to the accompanying drawings and embodiments. The embodiments of the present invention include, but are not limited to, the following embodiments.

[0040] This invention discloses a photodiode response current monitoring circuit for silicon-based optical receiver chips, such as... Figure 4The diagram shown illustrates a typical single-ended signal link architecture applicable to this invention. In this architecture, the anode of the photodiode PD is grounded, and the cathode is connected to the input node V_IN of the transimpedance amplifier TIA; the output of the transimpedance amplifier TIA is V_TIA_OUT; the gain stage GAIN and the driver stage DRIVER are cascaded sequentially after the TIA; the automatic gain control module AGC outputs three control signals V_AGC1, V_AGC2, and V_AGC3 based on the amplitude of the TIA output signal to dynamically adjust the conduction states of three NMOS transistors NS, NM, and NL, where NS is a small aspect ratio NMOS transistor, NM is a medium aspect ratio NMOS transistor, and NL is a large aspect ratio NMOS transistor; one end of each of these three MOS transistors is connected to the internal node V_X (which can be any intermediate potential node, such as the TIA output, gain stage input, or power rail), and the other end is connected to the V_IN node. Under no-light or low-light conditions, the AGC is off, and NS, NM, and NL are all cut off. As the optical power increases, the AGC sequentially turns on NS, NM, and NL to divert part of the photoresponse current, thereby maintaining a constant amplitude of the TIA output V_TIA_OUT. According to Kirchhoff's current law, at the V_IN node, the original response current I_PD generated by the photodiode is equal to the sum of the current I_RT flowing through the transimpedance resistor RT and the currents I_NS, I_NM, and I_NL flowing through NS, NM, and NL, i.e., I_PD = I_RT + I_NS + I_NM + I_NL. Therefore, if these four currents can be accurately replicated and summed, I_PD can be reconstructed.

[0041] Based on the above principles, this invention sets up a transimpedance current detection unit, an AGC small current detection unit, an AGC large current detection unit, and a current summation and output unit. Each unit ensures replication accuracy through voltage clamping and proportional device matching technology.

[0042] First, such as Figure 5 As shown, the transimpedance current detection unit is used to extract and replicate the current I_RT. In this unit, the operational amplifier OP5 has its non-inverting input connected to the filtered level signal V_TIA_OUT_LPF extracted from the TIA output node in the silicon-based optical signal receiving link. Its output drives the gate of NMOS transistor N9, and its inverting input is connected to the source of NMOS transistor N9. The drain of NMOS transistor N9 is connected to VDD, and the source of NMOS transistor N9 is also connected to one end of resistor RT_M and the input of current sink IS3. The output of current sink IS3 is grounded.

[0043] The non-inverting input of operational amplifier OP6 is connected to the filtered level signal V_IN_LPF extracted from the TIA input node in the silicon-based optical signal receiving link. The output drives the gate of PMOS transistor P6, and the source of PMOS transistor P6 is connected to the other end of resistor RT_M. The resistance value of RT_M is set to 1 / K1 times the original transimpedance RT, and can be an integer or a decimal, such as 1 or 1 / 2. Due to the negative feedback effect of OP5 and OP6, Figure 5 Node V_C2 is clamped to match the V_IN_LPF level, and V_C1 is clamped to match the _TIA_OUT_LPF level. Therefore, the voltage across RT_M is exactly the same as the transimpedance, and the current flowing through RT_M is I_RTM = K1·I_RT. This current flows through PMOS transistor P6 to the drain of the gate-drain connected NMOS transistor N10, and then through the common-gate connected NMOS transistor N11 to output a mirrored current I_R = K1*K2*I_RT at a ratio of K2. The derivation process is as follows:

[0044] Depend on:

[0045]

[0046]

[0047] therefore ;

[0048] The final detected I_R current is:

[0049] .

[0050] like Figure 6 As shown, the AGC small current detection unit is used to replicate I_NS and I_NM. In this unit, the non-inverting input of operational amplifier OP3 is connected to a filtered level signal V_X_LPF extracted from any node in the silicon-based optical receiving signal link. The output drives the gate of NMOS transistor N3, and the source of N3 is connected to the drain of replication transistors NS_M and NM_M. Simultaneously, this source is connected to the input of current sink IS1, thereby... Figure 6 The intermediate node V_C3 is clamped to the same level as V_X_LPF; the non-inverting input of operational amplifier OP4 is connected to V_IN_LPF, and its output drives the gate of PMOS transistor P4. The source of P4 is connected to the source of NS_M and the source of NM_M, and the drain of P4 is connected to the drain of NMOS transistor N4; the gate width and gate length of NMOS transistors NS_M and NM_M are respectively... Figure 4The NS and NM transistors maintain the same ratio K3; from a power-saving perspective, K3 is generally taken as a small multiple, such as 1 / 2. The gates of NMOS transistors NS_M and NM_M receive the AGC control voltages V_AGC1 and V_AGC2 after RC filtering, respectively. When AGC is enabled, NS_M and NM_M operate in the linear region, and finally output I_AGC1 = K3*K4*(I_NS+I_NM) through the common-gate NMOS transistor N5 in a mirror ratio K4. NMOS transistors N4 and N5 form a mirror transistor with a mirror ratio of K4. The specific derivation process of I_AGC1 is as follows:

[0051] Depend on ,

[0052] ,

[0053] ,

[0054] ,

[0055] Where VTH is the threshold voltage of the MOSFET (related to the process and substrate connection); H is a process-dependent constant. V_C4 is... Figure 6 The source terminal levels of NS_M and NM_M are given, and I_SUM is the current flowing out of PMOS transistor P4.

[0056] therefore ;

[0057] ;

[0058] ;

[0059] The final detected I_AGC1 current is:

[0060]

[0061] like Figure 7 As shown, the AGC high-current detection unit processes I_NL separately. Since the conduction current of NL under strong light is much greater than the sum of NS and NM (typically 10 times the sum of NS and NM), to reduce power consumption and ensure linearity, the gate width and gate length of the NMOS transistor NL_M are... Figure 4The ratio of the NL transistor is K5; from the perspective of saving power consumption, K5 is generally taken as a small multiple, such as 1 / 10. This unit is connected to the non-inverting input of operational amplifier OP7 to extract the filtered level signal V_X_LPF from any node in the silicon-based optical receiving signal link. Its output drives the gate of NMOS transistor N6 and, together with current sink IS2, clamps the drain level V_C5 of NL_M to V_X_LPF; operational amplifier OP8 drives PMOS transistor P5 to clamp the source level V_C6 of NL_M to V_IN_LPF; the gate of NL_M receives V_AGC3 filtered by R9 and C9; among them, NMOS transistors N7 and N8 form a mirror transistor with a mirror ratio of K6. Thus, the drain current of NL_M flows into the gate-drain connected NMOS transistor N7 through P5, and outputs I_AGC2=K5*K6*I_NL through the common-gate NMOS transistor N8 with a mirror ratio of K6. The specific derivation process of I_AGC2 is as follows:

[0062] Depend on ,

[0063] ,

[0064] ,

[0065] therefore ;

[0066] The final detected I_AGC2 current is:

[0067] .

[0068] Finally, as Figure 8 As shown, the current summation and output unit superimposes currents I_R, I_AGC1, and I_AGC2 with a uniform gain. Current I_R is injected into the drain of PMOS transistor P11 connected to the diode, and its gate, after being filtered by R11 and C11, drives PMOS transistor P12 with a mirror ratio of K7; I_AGC1 is injected into the drain of P7, and after being filtered by R12 and C12, drives P8 with a ratio of K9; I_AGC2 is injected into the drain of P9, and after being filtered by R10 and C10, drives P10 with a ratio of K8. The drains of P12, P8, and P10 are all connected to the output node Imonitor (…). Figure 8 (Monitoring current output). By designing the layout so that the scaling factor satisfies K1*K2*K7 = K3*K4*K9=K5*K6*K8=Con (Con is a constant, which can be set to 1 to achieve 1:1 monitoring, or greater than 1 to achieve amplification), then:

[0069]

[0070] A linear reconstruction of the original photoresponse current is completed.

[0071] This invention is also applicable to differential architectures. For example... Figure 9 As shown, in the differential signal link, the effective photodiode PD and the pseudo photodiode DUMMY_PD are connected to the negative input terminal V_TIA_IN and the positive input terminal V_TIA_IP of the differential transimpedance amplifier TIA_DIFF, respectively, with both anodes grounded. DUMMY_PD is shielded from light and does not generate photocurrent. The differential outputs V_TIA_OUTP and V_TIA_OUTN of TIA_DIFF are input to the differential gain stage, and the differential gain stage outputs signals to the differential driver stage, which outputs signals V_OUTP and V_OUTN. At this time, only PD generates I_PD, and V_TIA_IN and V_TIA_IP maintain the same common-mode level under feedback. Figure 10 As shown, the transimpedance current detection unit is adjusted accordingly: V_TIA_OUTP is filtered by R12 and C12 and then connected to the reference potential V_REF; V_TIA_OUTN is filtered by R14 and C13 and then connected to the output V_AMP of operational amplifier OP7; OP8 drives NMOS transistor N11 to clamp V_AMPB to V_AMP; one end of the replication resistor RT_M is connected to V_AMPB, and the other end is connected to V_REF; Current flowing through RT_M The current flows through diode N11 into PMOS transistor P13, and then through common-gate P14, outputting I_P14 = K1 * K10 * I_RT at a ratio of K10. This current then flows into NMOS transistor N12, and through common-gate N13, outputting I_R = K1 * K10 * K11 * I_RT at a ratio of K11. Figure 6 , Figure 7 , Figure 8 The AGC current detection and summation structure is designed, and the overall proportional coefficient is set to satisfy K1*K10*K11*K7=K3*K4*K9=K5*K6*K8=Con. This allows for the implementation of Imonitor = Con·I_PD in a differential architecture; where Imonitor is... Figure 9 The monitoring current output.

[0072] Throughout the implementation, all replication operations rely on a voltage clamping structure to ensure complete consistency of V_GS and V_DS between the original and replicated devices, thereby maintaining current replication accuracy under the same process angle, temperature, and power supply fluctuations. An RC low-pass filter network effectively isolates high-frequency signals, transmitting only DC bias to avoid AC interference and clamp stability. The scaling factor is precisely set in the layout using device geometry (resistance value, MOSFET width-to-length ratio) and current mirror area ratio. The MOSFET type in the AGC branch can be replaced with PMOS or BJT, and its connection node V_X can be the TIA output, gain stage input, or any other node participating in the current balancing of the V_IN node. The replica transistor size ratio can be flexibly adjusted according to power consumption and linearity requirements, with different K values ​​used in different branches, and the gain is ultimately unified through the scaling mirror of the summing unit. This architecture does not insert any active devices between the photodiode cathode and the TIA input, so the noise performance of the main signal path is unaffected, and the receiver sensitivity is maintained. Simultaneously, the monitoring circuit uses only standard process basic components, offering strong compatibility and low static power consumption, especially with the AGC branch shutting down in low light conditions, further saving energy. Therefore, this invention has significant advantages in high-reliability, high-integration optical receiving applications such as industrial automation and automotive power management.

[0073] The functional modules mentioned in this invention are described in the simplest form. Adding detailed descriptions of these modules will not affect the protection of this invention. Examples include transimpedance amplifier (TIA), automatic gain control (AGC) module, operational amplifier (OP), and current sink.

[0074] The three-channel AGC output control voltage mentioned in this invention is only a typical case; in other circuits, there may be one or more AGC control voltages. Changing the number of AGC output control circuits does not affect the protection of this invention.

[0075] The devices used for AGC output adjustment mentioned in this invention are NMOS transistors NS, NM, and NL, described in their most typical form. Changing the type and number of these devices does not affect the protection of this invention. For example, replacing the devices with PMOS transistors, BJT transistors, or their series combination with resistors does not affect the protection of this invention.

[0076] The V_X potential connected to one end of the NMOS transistors NS, NM, and NL mentioned in this invention is only a typical case. V_X can be any node in the circuit, and changing its connection position will not affect the protection of this invention. For example, one end of the NMOS transistors NS, NM, and NL can be directly connected to the TIA output V_TIA_OUT potential.

[0077] The method described in this invention, which involves detecting the currents flowing through NS and NM together and detecting the current flowing through NL separately, is the most typical form. Changing the combination of these detections does not affect the protection of this invention. For example, the currents NS, NM, and NL can be detected in one architecture or in three separate architectures.

[0078] The above embodiments are merely one of the preferred embodiments of the present invention and should not be used to limit the scope of protection of the present invention. Any modifications or refinements made to the main design concept and spirit of the present invention that are not of substantial significance, but solve the same technical problem as the present invention, should be included within the scope of protection of the present invention.

Claims

1. A silicon-based optical receiver chip integrated photodiode response current monitoring circuit, characterized in that, The application relates to a silicon-based optical receiving signal link AGC current detection device. A transimpedance current detection unit is arranged to detect the current I_RT flowing through the transimpedance RT in the silicon-based optical receiving signal link; An AGC small current detection unit is arranged to detect the current I_NS flowing through the NS tube and the current I_NM flowing through the NM tube in the silicon-based optical receiving signal link; An AGC large current detection unit is arranged to detect the current I_NL flowing through the NL tube in the silicon-based optical receiving signal link; A current summation and output unit is arranged to superimpose the detected currents I_RT, I_NS, I_NM and I_NL according to a set unified proportional coefficient, and output a monitoring current in linear relation with the original response current I_PD of the photodiode.

2. The integrated photodiode response current monitoring circuit for a silicon-based optical receiver chip of claim 1, wherein, The transimpedance current detection unit comprises an operational amplifier OP5, an operational amplifier OP6, an NMOS tube N9, an NMOS tube N10, an NMOS tube N11, a PMOS tube P6, a resistor RT_M and a current sink IS3, wherein: The operational amplifier OP5 is connected to the filtered level signal V_TIA_OUT_LPF extracted from the TIA output node in the silicon-based optical receiving signal link at the non-inverting input end, and drives the gate of the NMOS tube N9 at the output end; the inverting input end of the operational amplifier OP5 is connected to the source of the NMOS tube N9; the drain of the NMOS tube N9 is connected to VDD; the source of the NMOS tube N9 is further connected to one end of the resistor RT_M and the input end of the current sink IS3; and the output end of the current sink IS3 is grounded; The operational amplifier OP6 is connected to the filtered level signal V_IN_LPF extracted from the TIA input node in the silicon-based optical receiving signal link at the non-inverting input end, and drives the gate of the PMOS tube P6 at the output end; the inverting input end of the operational amplifier OP6 is connected to the other end of the resistor RT_M and the source of the PMOS tube P6; the drain of the PMOS tube P6 is connected to the drain of the NMOS tube N10; the gate of the NMOS tube N10 is connected to the gate of the NMOS tube N11; the source of the NMOS tube N10 and the source of the NMOS tube N11 are both grounded; the drain of the NMOS tube N10 is connected to the gate of the NMOS tube N10; and the drain of the NMOS tube N11 outputs the mirror current I_R.

3. The integrated photodiode response current monitoring circuit for a silicon-based optical receiver chip of claim 2, wherein, The AGC small current detection unit comprises an operational amplifier OP3 having a non-inverting input end connected to a filtered level signal V_X_LPF extracted from any node in the silicon-based optical receiving signal link, an NMOS tube N3 having a gate connected to an output end of the operational amplifier OP3 and a drain connected to VDD, a current sink IS1 having an input end connected to an inverting input end of the operational amplifier OP3 and a source connected to a source of the NMOS tube N3 and an output end connected to ground, an NMOS tube NS_M having a drain connected to the source of the NMOS tube N3, an NMOS tube NM_M having a drain connected to the source of the NMOS tube N3, an operational amplifier OP4 having an inverting input end connected to a source of the NMOS tube NS_M and a source of the NMOS tube NM_M, a PMOS tube P4 having a gate connected to an output end of the operational amplifier OP4 and a source connected to an inverting input end of the operational amplifier OP4, an NMOS tube N4 having a drain connected to a drain of the PMOS tube P4 and a source connected to ground, and an NMOS tube N5 having a gate connected to a gate of the NMOS tube N4 and a source connected to ground; wherein a gate of the NMOS tube N4 is connected to a drain of the NMOS tube N4, a gate of the NMOS tube NS_M is connected to an RC filtered level signal V_AGC1 of a control voltage AGC1 output by an automatic gain control module AGC in the silicon-based optical receiving signal link, a gate of the NMOS tube NM_M is connected to an RC filtered level signal V_AGC2 of a control voltage AGC2 output by the automatic gain control module AGC in the silicon-based optical receiving signal link, a non-inverting input end of the operational amplifier OP4 is connected to a filtered level signal V_IN_LPF extracted from a response current outflow node in the silicon-based optical receiving signal link, and a drain of the NMOS tube N5 outputs a detection current I_AGC1.

4. The integrated photodiode response current monitoring circuit for a silicon-based optical receiver chip of claim 3, wherein, The AGC large current detection unit comprises an operational amplifier OP7 having a non-inverting input end connected to a filtered level signal V_X_LPF extracted from any node in the silicon-based optical receiving signal link, an NMOS tube N6 having a gate connected to an output end of the operational amplifier OP7 and a drain connected to VDD, a current sink IS2 having an input end connected to an inverting input end of the operational amplifier OP7 and a source connected to ground, an NMOS tube NL_M having a drain connected to a source of the NMOS tube N6, an operational amplifier OP8 having an inverting input end connected to a source of the NMOS tube NL_M, a PMOS tube P5 having a gate connected to an output end of the operational amplifier OP8 and a source connected to an inverting input end of the operational amplifier OP8, an NMOS tube N7 having a drain connected to a drain of the PMOS tube P5 and a source connected to ground, and an NMOS tube N8 having a gate connected to a gate of the NMOS tube N7 and a source connected to ground; wherein a gate of the NMOS tube N7 is connected to a drain of the NMOS tube N7, a gate of the NMOS tube NL_M is connected to an RC filtered level signal V_AGC3 of a control voltage AGC3 output by an automatic gain control module AGC in the silicon-based optical receiving signal link, a non-inverting input end of the operational amplifier OP8 is connected to a filtered level signal V_IN_LPF extracted from a response current outflow node in the silicon-based optical receiving signal link, and a drain of the NMOS tube N8 outputs a detection current I_AGC2.

5. The integrated photodiode response current monitoring circuit for a silicon-based optical receiver chip of claim 4, wherein, The current summation and output unit comprises a PMOS tube P7 having a drain connected to a drain of the NMOS tube N5 and a source connected to VDD, a resistor R12 having one end connected to a gate of the PMOS tube P7, a capacitor C12 having one end connected to the other end of the resistor R12 and the other end connected to a source of the PMOS tube P7, a PMOS tube P8 having a gate connected to a common end of the resistor R12 and the capacitor C12 and a source connected to VDD, a PMOS tube P9 having a drain connected to a drain of the NMOS tube N8 and a source connected to VDD, a resistor R10 having one end connected to a gate of the PMOS tube P9, a capacitor C10 having one end connected to the other end of the resistor R10 and the other end connected to a source of the PMOS tube P9, and a PMOS tube P10 having a gate connected to a common end of the resistor R10 and the capacitor C10 and a source connected to VDD, a PMOS tube P11 having a drain connected to a drain of the NMOS tube N11 and a source connected to VDD, a resistor R11 having one end connected to a gate of the PMOS tube P11, a capacitor C11 having one end connected to the other end of the resistor R11 and the other end connected to a source of the PMOS tube P11, and a PMOS tube P12 having a gate connected to a common end of the resistor R11 and the capacitor C11 and a source connected to VDD; wherein a gate of the PMOS tube P7 is connected to a drain of the PMOS tube P7, a gate of the PMOS tube P9 is connected to a drain of the PMOS tube P9, a gate of the PMOS tube P11 is connected to a drain of the PMOS tube P11, and a drain of the PMOS tube P8 is connected to a drain of the PMOS tube P10 and a drain of the PMOS tube P12.

6. The integrated photodiode response current monitoring circuit for a silicon-based optical receiver chip of claim 5, wherein, The resistance RT_M has a value of 1 / K1 times of the transimpedance RT.

7. The integrated photodiode response current monitoring circuit for a silicon-based optical receiver chip of claim 6, wherein, The NMOS tube N11 and the NMOS tube N10 constitute mirror tubes, and a mirror ratio thereof is K2.

8. The integrated photodiode response current monitoring circuit for a silicon-based optical receiver chip of claim 7, wherein, A gate width and a gate length of the NMOS tube NS_M and the NMOS tube NM_M are kept in the same ratio K3 as those of the NS tube and the NM tube in the silicon-based optical receiving signal link, the NMOS tube N4 and the NMOS tube N5 constitute mirror tubes, and a mirror ratio thereof is K4.

9. The integrated photodiode response current monitoring circuit for a silicon-based optical receiver chip of claim 8, wherein, The NMOS tube NL_M and the NL tube in the silicon-based optical receiving signal link are kept in the ratio K5, the NMOS tube N7 and the NMOS tube N8 constitute mirror tubes, and a mirror ratio thereof is K6.

10. The integrated photodiode response current monitoring circuit for a silicon-based optical receiver chip of claim 9, wherein, The PMOS tube P7 and the PMOS tube P8 constitute mirror tubes, and a mirror ratio thereof is K9, the PMOS tube P9 and the PMOS tube P10 constitute mirror tubes, and a mirror ratio thereof is K8, and the PMOS tube P11 and the PMOS tube P12 constitute mirror tubes, and a mirror ratio thereof is K7.

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