Circuit board preparation method for inhibiting common-mode noise, circuit board and electronic equipment

Abstract

The invention discloses a circuit board preparation method for inhibiting common-mode noise, a circuit board and electronic equipment, and relates to the technical field of electronic circuits. The method specifically comprises the steps that a first wire, a second wire and a reference conductor are arranged on the printed circuit board, the second wire provides a current return path for the first wire, and the second wire is strategically arranged between the first wire and the reference conductor. Through the layout, the second wire is used as an in-situ electromagnetic shielding layer for the first wire, and an electromagnetic coupling path between the first wire and the reference conductor is effectively blocked. According to the invention, the generation of common-mode noise can be obviously inhibited from the source on the premise of not adding any additional component, and the effects of reducing the cost and saving the layout space of a circuit board are achieved. The invention aims to solve the problems of cost increase and space occupation caused by the fact that common-mode noise is suppressed by adding a common-mode inductor, a filter or a metal shielding cover in the prior art.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and in particular to a method for manufacturing a circuit board that suppresses common-mode noise, the circuit board, and electronic equipment. Background Technology

[0002] In modern electronic devices, electromagnetic interference (EMI) has become a major factor affecting product performance and reliability. One of the main forms of EMI is common-mode noise, which interferes with the device itself and surrounding equipment through both conduction and radiation paths.

[0003] To suppress common-mode noise, existing technologies typically employ methods such as adding common-mode inductors, filters, or external metal shielding to the circuit board. However, these solutions increase component costs and manufacturing processes, and occupy valuable circuit board layout space, presenting significant limitations for compact and cost-sensitive consumer electronics products.

[0004] Whether adding metal shielding or using dedicated filtering components, both directly increase product material and manufacturing costs. These solutions place significant demands on circuit board layout space. For example, filters require a certain amount of circuit board area, while shielding imposes additional limitations on the overall structure and size of the product. For modern, thinner and lighter electronic products, it is often difficult to provide enough space to accommodate additional components. Considering both cost and space, traditional solutions cannot meet the design requirements of current electronic products.

[0005] Therefore, the industry urgently needs a technical solution that can effectively suppress common-mode noise without significantly increasing costs and space requirements. Summary of the Invention

[0006] The main objective of this invention is to provide a method for fabricating a circuit board, a circuit board, and an electronic device for suppressing common-mode noise, aiming to solve the technical problem that suppressing common-mode noise in the prior art relies on additional components or complex multilayer board structures, which leads to increased costs and limited space.

[0007] To achieve the above objectives, the present invention proposes a method for fabricating a circuit board to suppress common-mode noise, comprising: Provide a printed circuit board; A first trace, a second trace, and a reference conductor are provided on the printed circuit board; wherein the second trace is electrically connected to the first trace, and the second trace provides a current return path for the first trace. The second trace is arranged between the first trace and the reference conductor so that the second trace serves as an electromagnetic shielding layer for the first trace.

[0008] Furthermore, including: The first trace is arranged on the first wiring layer of the printed circuit board; The second trace is arranged on the second wiring layer of the printed circuit board; and The reference conductor is disposed on the third wiring layer of the printed circuit board; The second wiring layer is located between the first wiring layer and the third wiring layer in the stacking direction of the printed circuit board.

[0009] Furthermore, it also includes a noise emitting element disposed on the printed circuit board; On a plane projection perpendicular to the stacking direction of the printed circuit board, the second trace is arranged between the first trace and the noise emitting element.

[0010] Furthermore, the first trace is a positive power supply trace, and the second trace is a negative power supply trace corresponding to the positive power supply trace.

[0011] Furthermore, the noise emitting element is a switching power device, which is a metal-oxide-semiconductor field-effect transistor.

[0012] Furthermore, the first trace is a signal trace; The second trace is electrically connected to the signal trace, and the second trace is the ground trace corresponding to the signal trace.

[0013] Furthermore, the width of the second trace is greater than or equal to the width of the first trace.

[0014] Furthermore, the printed circuit board has a plurality of grounding vias arranged along the length of the second trace to electrically connect the second trace to the ground plane within the printed circuit board.

[0015] This application also discloses a circuit board, comprising: First routing; A second trace, electrically connected to the first trace, is configured as a current return path for the first trace; and Reference conductor; The second trace is arranged between the first trace and the reference conductor.

[0016] This application also discloses an electronic device that includes a circuit board as described above.

[0017] The above technical solution has the following advantages: This invention uses the circuit's inherent second trace as a current return path and as an electromagnetic shielding layer for the first trace. It eliminates the need for any additional components, complex and expensive multilayer boards for dedicated shielding, and a robust chassis ground as the primary shielding element. By optimizing the printed circuit board layout, electromagnetic coupling between the first trace and the reference conductor is significantly suppressed without increasing material costs or manufacturing processes, thus reducing common-mode noise at its source. This circuit board fabrication method reduces costs and improves space utilization, making it suitable for cost-sensitive, compact consumer electronics products.

[0018] This invention also forms a three-dimensional electromagnetic shielding layer by arranging the first trace, the second trace, and the reference conductor on different circuit board layers. When the interference source originates from a specific component on the circuit board, the noise source is isolated by arranging the second trace between the first trace and the noise-emitting component in a planar projection. Setting the width of the second trace to be greater than or equal to the width of the first trace ensures that the electromagnetic shielding layer completely covers the protected trace, improving the shielding effect. Furthermore, this application adds multiple grounding vias to the second trace, which can firmly clamp it to ground potential, preventing the shielding layer from floating potential due to its own noise, further enhancing the stability of the shielding structure. Attached Figure Description

[0019] The present invention will now be described in detail with reference to specific embodiments and accompanying drawings, wherein: Figure 1 This is a schematic diagram of an existing circuit structure with the positive and negative terminals running parallel to ground.

[0020] Figure 2 This is the equivalent circuit diagram of the existing positive and negative terminals with parallel traces to ground.

[0021] Figure 3 This is a circuit structure diagram of the first trace, the second trace, and the reference conductor of the present invention.

[0022] Figure 4 This is a schematic diagram of the circuit structure for coupling existing switching power devices.

[0023] Figure 5 This is the equivalent circuit diagram of the switching power device coupling and circuit coupling of the present invention.

[0024] Figure 6 This is a schematic diagram of the layout for isolating the negative electrode trace in an embodiment of the present invention.

[0025] In the diagram: 100, first trace; 200, second trace; 300, reference conductor; 400, switching power device; 500, grounding via. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the following specific embodiments are only used to explain the invention and do not constitute a limitation thereof.

[0027] Explanation of the attached image: Figure 1 View a is a top view of the lines running parallel to the ground, representing the positive and negative poles. Figure 1 View b is the right view of the positive and negative poles running parallel to the ground. Figure 4 View a in the middle is a front view of the coupling of a prior art switching power device. Figure 4 View b is a left view of the coupling of a prior art switching power device. Figure 4 View C is a top view of the coupling of existing switching power devices; Figure 6 View a is a front view of the coupling between the switching power device and the circuit in this application. Figure 6 View b in the middle is the left view of the coupling between the switching power device and the circuit in this application. Figure 6 View c is a top view of the coupling between the switching power device and the circuit in this application.

[0028] The technical principles upon which this invention is based are explained. Common-mode noise in products mainly originates from electromagnetic coupling. In electronic devices, common-mode noise is primarily generated by noise sources or high-frequency signals in the circuit coupling with a reference conductor, such as the device casing or system ground, through a spatial electromagnetic field. Coupling mainly occurs through capacitive and inductive coupling, and its coupling component is directly proportional to the coupling area A and inversely proportional to the coupling distance d.

[0029] The relationship expression for the mutual capacitance value C of capacitive coupling is: (Equation 1).

[0030] The relationship expression for the mutual inductance value M in inductive coupling is: (Equation 2).

[0031] in, The vacuum permittivity, The permeability of vacuum is given by d. The core idea of ​​this invention is based on this: by designing the printed circuit board layout, the relative positions of the traces are actively changed to reduce the coupling area A or increase the coupling distance d, thereby effectively suppressing common-mode noise.

[0032] like Figure 3As shown, a method for manufacturing a circuit board to suppress common-mode noise includes setting a first trace 100, a second trace 200, and a reference conductor 300 on a printed circuit board, wherein the second trace 200 is electrically connected to the first trace 100 and provides a current return path for the first trace 100; the second trace 200 is arranged between the first trace 100 and the reference conductor 300 so that the second trace 200 serves as an electromagnetic shielding layer for the first trace 100.

[0033] Reference to existing technology layout Figure 1 and Figure 2 A common layout involves arranging the positive and negative input power traces of the DC / DC circuit in parallel on the same layer, above the reference conductor 300PE (ground). In this case, the positive trace can be considered as the first trace 100, and the negative trace as part of the second trace 200. The negative trace does not provide shielding, and both the positive and negative traces couple with PE, generating parasitic mutual inductances M1 and M2 and parasitic mutual capacitances C1 and C2, forming a common-mode noise loop, such as... Figure 2 The equivalent circuit is shown.

[0034] To quantify the impact of existing technologies, the following calculations are performed.

[0035] If the length of the positive electrode trace is 50mm and the width is 10mm; and the length of the negative electrode trace is 50mm and the width is 10mm.

[0036] The spacing d between the positive and negative traces and the PE is 10mm.

[0037] The interference voltages V1 (positive) and V2 (negative) on the trace are both 1V, with a frequency of 30MHz.

[0038] The angular frequency ω of 30MHz is: .

[0039] According to Equation 1, the mutual capacitance values ​​C1 and C2 between the positive and negative electrode traces and the PE are: ; ; Capacitive coupling common-mode voltage for: ; Capacitive coupling common-mode current for: ; According to Equation 2, the mutual inductances M1 and M2 between the positive and negative traces and PE are both: ; ; By resolving the above formulas, we can obtain the induced voltage V induced on the PE by the positive and negative terminals. MM The calculation formula is: ; According to Faraday's law of electromagnetic induction, the total inductive coupling common-mode current coupled to the PE can be calculated. for: ; At a frequency of 30MHz, the common-mode current generated by capacitive coupling is 1.67 × 10⁻⁶. -4 A) Much larger than the common-mode current generated by inductive coupling (8.3 × 10⁻⁶). -8 Therefore, at a frequency of 30MHz, the subsequent discussion will focus on the capacitive coupling common-mode component.

[0040] Reference Figure 3 This embodiment improves the above layout using the method of the present invention. The first trace 100 is the positive power supply trace, and the second trace 200 is the negative power supply trace. The negative power supply trace provides a current return path for the positive trace, and the reference conductor 300 is the PE (ground). The positive and negative traces are changed from being parallel on the same layer to being stacked on top of each other. Specifically, the second trace 200 is arranged between the first trace 100 and the reference conductor 300, using the negative trace as a physical barrier to block the electric field coupling path between the positive trace and the PE. At this time, the coupling between the positive trace and the PE is greatly weakened, and its coupling component can be basically ignored.

[0041] Quantitative calculation of the effect: After the improvement, the coupling capacitance C1 between the positive electrode trace and PE is reduced to 0.01pF, while the coupling capacitance C2 between the negative electrode trace and PE remains at 4.43 × 10⁻⁶ pF because the position remains unchanged. -13 F.

[0042] The common-mode voltage at this time for: ; The common-mode current at this time for: ; The data comparison is shown in Table 1 below: Table 1 is a comparison table of data for parallel positive and negative electrode traces and top and bottom traces.

[0043] Data comparison shows that the common-mode current generated by using the upper and lower layer routing method of the present invention is almost halved, proving that the circuit board manufacturing method of this application can effectively suppress common-mode noise.

[0044] like Figure 3 As shown, the first trace 100 is arranged on the first wiring layer of the printed circuit board; the second trace 200 is arranged on the second wiring layer of the printed circuit board; and the reference conductor 300 is arranged on the third wiring layer of the printed circuit board; wherein the second wiring layer is located between the first wiring layer and the third wiring layer in the stacking direction of the printed circuit board.

[0045] As one embodiment of this application, in a four-layer board design switching power supply module, the specific implementation of this method is as follows: The first trace 100 is preferably a positive power supply trace, such as a +12V power supply. The first trace 100 is arranged on the first wiring layer of the printed circuit board, such as the top layer. The first trace 100 carries the current flowing from the power input terminal to the load. Due to the high-speed switching action of the switching device, high-frequency voltage and current ripples will be superimposed on this trace, which is the main source of noise emission.

[0046] The second trace 200 is the negative power supply trace corresponding to the aforementioned positive power supply trace, such as GND or V-. The second trace 200 is arranged on the second wiring layer (Inner Layer 1) of the printed circuit board, and provides a return path for the current of the first trace 100. According to electromagnetic field theory, current always tends to choose the path of lowest impedance to return to the source. Under high-frequency voltage, such as a voltage with a frequency of 30MHz, the path of lowest impedance is also the current path with the shortest physical distance.

[0047] Reference conductor 300 is the ground plane of the printed circuit board. Reference conductor 300 is arranged on the third wiring layer (Inner Layer 2) of the printed circuit board. This ground plane is usually connected to the device housing or earth and is the main conductor in which common mode noise eventually forms a loop.

[0048] In printed circuit board layout, the second wiring layer is always located between the first and third wiring layers in the stack-up structure; that is, in this embodiment, the negative power supply trace is located between the positive power supply trace and the ground plane. The high-frequency electric field generated by the positive power supply trace will be captured and coupled by the negative power supply trace below it. Due to the physical barrier of the negative power supply trace, the electric field generated by the positive power supply trace is difficult to penetrate and couple to the lower ground plane. The negative power supply trace provides a shielding layer for the positive power supply trace, thereby significantly reducing the common-mode noise current injected into the ground plane.

[0049] In another embodiment of this application, the first trace 100 is a signal trace; the second trace 200 is electrically connected to the signal trace, and the second trace 200 is a ground trace corresponding to the signal trace. In printed circuit boards containing high-speed digital interfaces, such as USB and HDMI, the specific implementation of this method is as follows: The first trace 100 is a high-speed signal trace, such as the clock line CLK or the data line D+. High-speed signal traces carry rapidly changing digital signals, and their edges will generate electromagnetic radiation.

[0050] The second trace 200 is the ground trace corresponding to the high-speed signal trace, such as signal ground. The ground trace is arranged as a strip or planar conductor parallel to the first trace 100, such as a copper surface. The copper surface provides the shortest return current path for the first trace 100.

[0051] The reference conductor 300 can be the power plane of the printed circuit board or the ground connection layer of the chassis. The following uses the power plane as an example. If the power plane is coupled with a high-speed signal line, common-mode noise will be generated.

[0052] High-speed signal traces are placed on the top layer, with a complete copper surface on the second routing layer immediately below, dedicated to signal return. Power planes are placed on the third or fourth routing layer. By arranging them in the stack-up direction of the printed circuit board, the loop area between the signal current and its return current is minimized. This not only reduces differential-mode radiation, but the second trace 200 also effectively isolates the first trace 100 from the reference conductor 300 below, preventing capacitive coupling between them and thus suppressing the generation of common-mode noise.

[0053] The second trace 200 can be designed as a mesh structure with a specific grid or slots. By controlling the size and shape of the grid, it can be made to exhibit band-stop characteristics for electromagnetic waves in a specific frequency band, thereby achieving frequency-selective shielding and further optimizing the suppression effect on specific noise frequencies.

[0054] like Figures 4 to 6 As shown, this application also includes a noise emitting element disposed on the printed circuit board; in a plane projection perpendicular to the stacking direction of the printed circuit board, the second trace 200 is disposed between the first trace 100 and the noise emitting element.

[0055] Reference to existing technology layout Figure 4 and Figure 5 Taking MOSFETs as typical interference devices, power supply loops are arranged nearby with the positive and negative terminals in parallel. The electromagnetic noise of the MOSFET will be coupled to both the positive and negative power supply traces, and finally form common-mode noise through the coupling of the positive and negative power supply traces with PE.

[0056] If the positive power supply trace is 50mm long and 20mm wide, and the distance between it and the PE is 5mm; the negative power supply trace has the same dimensions and spacing.

[0057] The electromagnetic noise of the MOSFET induces a voltage V1 = 1V with a frequency of 30MHz in the positive terminal trace.

[0058] Because the coupling area is the same, the same voltage V2=1V is induced in the negative terminal trace.

[0059] From Equation 1, we can calculate C1=C2=1.77pF, common-mode voltage. for: ; common mode current for: ; This embodiment improves the above layout using the method of the present invention. The noise emitting element is a MOSFET, the first trace 100 is the positive power supply trace, and the second trace 200 is the negative power supply trace. The routing of the positive and negative power supplies is modified. On a plane projection perpendicular to the stacking direction of the printed circuit board, the second trace 200 is arranged between the first trace 100 and the noise emitting element, that is, the negative trace is arranged between the positive trace and the MOSFET. The second trace 200 forms a low-impedance trace, and the high-frequency electromagnetic field energy radiated by the MOSFET will be absorbed by the second trace 200 and guided to ground or the negative power supply, instead of continuing to propagate and couple to the first trace 100.

[0060] Reference Figure 6 As can be seen, in a complex circuit board, in order to achieve more comprehensive protection, upper and lower layer traces are used, and the negative trace is arranged between the positive trace and PE. Multiple positive power traces and multiple negative power traces are arranged in an adjacent or staggered manner on the plane projection, ensuring that at least one side of multiple positive traces is adjacent to a negative trace.

[0061] The negative electrode trace isolates the direct coupling of the MOSFET to the positive electrode trace on the plane, and simultaneously isolates the coupling of the positive electrode trace to the PE in the vertical direction. The specific quantitative calculations are as follows: Due to the isolation of the negative trace, the potential coupled to the positive power supply trace is extremely small, V1 decreases to 0.01V. Because of the layout adjustment, the coupling between the negative trace and the MOSFET is slightly enhanced, and the induced voltage V2 increases from 1V to 1.5V. Since the positive trace is isolated by the negative trace, its coupling with PE is also significantly reduced, C1 decreases to 0.01pF, while C2 remains unchanged at 1.77pF. The common-mode voltage at this time... for: ; common mode current for: ; The data comparison is shown in Table 2 below: Table 2 is a comparison table of data for MOS transistors with and without negative electrode trace isolation.

[0062] Data comparison shows that the improved common-mode voltage / current is two orders of magnitude smaller, proving that using negative terminal traces for double isolation is very effective in reducing common-mode noise.

[0063] The noise emitting element is a switching power device 400, which is a metal-oxide-semiconductor field-effect transistor. This embodiment has already been described in detail above using a MOSFET as the switching power device 400.

[0064] A protection layout for sensitive analog signal lines. The first trace 100 is a weak analog signal trace, and the second trace 200 is the analog ground (AGND) return trace corresponding to this analog signal line. The reference conductor 300 can be a digital ground plane (DGND). By placing the AGND trace or plane between the analog signal trace and the DGND plane, interference from digital noise to the analog signal can be effectively isolated.

[0065] The width of the second trace 200 is greater than or equal to the width of the first trace 100.

[0066] In implementing the above embodiments, for example, the first trace 100 serves as the positive power supply and has a width of 10 mm, while the second trace 200 serves as the negative power supply and has a width of 15 mm. The purpose is to ensure effective shielding coverage. Electric fields exhibit edge effects; if the shielding conductor and the shielded conductor have the same width, some edge electric field lines can easily bypass the shielding layer and couple to the reference conductor 300. Making the second trace 200 wider creates a more effective Faraday cage, ensuring that the first trace 100 is completely blocked by the second trace 200 from any angle viewed from the reference conductor 300, thereby maximizing the capture of electric field lines and achieving optimal shielding performance.

[0067] Reference Figure 6 The printed circuit board has a plurality of grounding vias 500 arranged along the length of the second trace 200, such as... Figure 6 In the main view, the second trace 200 on the right is a vertical connecting trace on the right side, and the first trace 100 on the left side is a vertical connecting trace. A grounding via 500 is used to electrically connect the second trace 200 to the ground plane in the printed circuit board.

[0068] In implementing the planar isolation layout of the above embodiment, the second trace 200 serves as a ground return trace, which is a copper strip located on the top layer. To ensure its shielding effectiveness, a grounding via 500 is drilled every 5mm along its length. These vias electrically connect the top layer ground trace to the inner layer's main ground plane. Although the top layer ground trace can intercept noise, if its connection impedance to the main ground plane is too high, it will experience a potential increase due to induced noise, becoming a new noise radiating antenna and causing shielding failure. By arranging dense grounding vias 500, it is equivalent to connecting to the main ground plane with multiple low-impedance paths, ensuring that its potential remains stable at 0V and effectively dissipating the absorbed noise current to ground.

[0069] A circuit board includes a first trace 100; a second trace 200 electrically connected to the first trace 100 and configured as a current return path for the first trace 100; and a reference conductor 300; wherein the second trace 200 is disposed between the first trace 100 and the reference conductor 300 to serve as an electromagnetic shielding layer for the first trace 100.

[0070] As one embodiment of this application, the circuit board employs a double-layer design. The top layer has a first trace 100, which is the positive power trace. The bottom layer is almost entirely covered with a second trace 200, which is a negative power copper film. The circuit board is housed in a plastic casing, but there is an unshielded USB data cable nearby, namely the reference conductor 300 of this application. The negative power copper film on the bottom layer is located between the positive trace on the top layer and the USB data cable, thereby shielding the power trace from radiative interference to the USB cable. This circuit board is manufactured using the method described in the claims.

[0071] An electronic device includes a circuit board on which the above-described circuit board is mounted.

[0072] The electronic device includes a portable charger, which internally includes the circuit board described in the above embodiments. Because this electronic device uses the circuit board layout of this application, it can meet electromagnetic radiation-related regulatory requirements without the need for additional shielding or large common-mode inductors.

[0073] The above description is merely a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural transformations made using the contents of the present invention's specification and drawings under the inventive concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. A method for fabricating a circuit board to suppress common-mode noise, characterized in that, include: Provide a printed circuit board; A first trace, a second trace, and a reference conductor are set on a printed circuit board; The second trace is electrically connected to the first trace, and the second trace provides a current return path for the first trace. The second trace is arranged between the first trace and the reference conductor so that the second trace serves as an electromagnetic shielding layer for the first trace.

2. The method for fabricating a circuit board to suppress common-mode noise as described in claim 1, characterized in that, include: The first trace is arranged on the first wiring layer of the printed circuit board; The second trace is arranged on the second wiring layer of the printed circuit board; as well as The reference conductor is disposed on the third wiring layer of the printed circuit board; The second wiring layer is located between the first wiring layer and the third wiring layer in the stacking direction of the printed circuit board.

3. The method for fabricating a circuit board to suppress common-mode noise as described in claim 1, characterized in that, It also includes a noise emitting element disposed on the printed circuit board; On a plane projection perpendicular to the stacking direction of the printed circuit board, the second trace is arranged between the first trace and the noise emitting element.

4. The method for fabricating a circuit board to suppress common-mode noise as described in any one of claims 1 to 3, characterized in that, The first trace is a positive power supply trace, and the second trace is a negative power supply trace corresponding to the positive power supply trace.

5. The method for fabricating a circuit board to suppress common-mode noise as described in claim 3, characterized in that, The noise emitting element is a switching power device, which is a metal-oxide-semiconductor field-effect transistor.

6. The method for fabricating a circuit board to suppress common-mode noise as described in claim 1, characterized in that, The first trace is a signal trace; The second trace is electrically connected to the signal trace, and the second trace is the ground trace corresponding to the signal trace.

7. The method for fabricating a circuit board to suppress common-mode noise as described in claim 1, characterized in that, The width of the second trace is greater than or equal to the width of the first trace.

8. The method for fabricating a circuit board to suppress common-mode noise as described in claim 1, characterized in that, The printed circuit board has multiple grounding vias arranged along the length of the second trace to electrically connect the second trace to the ground plane within the printed circuit board.

9. A circuit board, characterized in that, include: First routing; A second trace is electrically connected to the first trace, and the second trace is configured as the current return path of the first trace. as well as Reference conductor; The second trace is arranged between the first trace and the reference conductor.

10. An electronic device, characterized in that, It includes the circuit board as described in claim 9.

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