LED chip and manufacturing method thereof

Abstract

The invention provides an LED chip and a manufacturing method thereof, and the manufacturing method of the LED chip comprises two stages which are continuously carried out, in the first stage, a first photoresist layer is used as a mask, and a hard mask is etched to expose a part of the epitaxial lamination; in the second stage, the exposed epitaxial laminated layer is etched until the surface of the exposed substrate part forms a cutting channel, and the first photoresist and the hard mask are respectively used as masks in sequence during etching, so that N sections of slopes are formed on the side wall of the cutting channel; therefore, under the condition that the width of the bottom of the cutting channel is not reduced, the width of the top of the cutting channel is reduced, more space is reserved for MESA table board expansion, the area of the MESA table board is expanded under the condition that the size of a chip is not increased and the area of other regions is not sacrificed, and the production efficiency is improved. And the side wall angle of the cutting channel is ensured not to be too steep to influence the subsequent coating of a film layer (such as an insulating layer) and further influence the product reliability.

Description

Technical Field

[0001] This invention relates to the field of light-emitting diode technology, and more specifically, to an LED chip and its manufacturing method. Background Technology

[0002] LEDs, as a new generation of large solid-state lighting sources, have advantages such as energy saving, long lifespan, small size, and environmental friendliness, and are therefore widely used in lighting, display, image processing, and other fields. In some chip manufacturing processes, MESA (Mesh-on-Action) surfaces are first etched to form the boundary of the effective light-emitting area. Therefore, increasing the area of ​​the MESA surface means that a larger active area will participate in light emission, thus directly increasing the light-emitting area, and its total luminous flux increases linearly with the area.

[0003] To increase the area of ​​the Mesa, some approaches start from chip layout design, such as directly increasing the MESA mesa area by adjusting the photomask layout (mesa expansion). However, after considering the dimensional deviations during the photolithography process, either the die size is directly increased to achieve the mesa expansion, which will inevitably affect the yield of a single wafer; or the size is kept unchanged, and the MESA mesa area is increased by sacrificing the area of ​​other areas (such as the area where the N electrode is located), but this will affect other chip performance, such as the excessive reduction of the N electrode leading to a decrease in its push test (DIE) reliability.

[0004] Therefore, how to expand the MESA mesa area without increasing the chip size or sacrificing the area of ​​other regions has become an urgent problem to be solved. Summary of the Invention

[0005] In view of this, the present invention provides an LED chip and a method for manufacturing the same, which can increase the MESA mesa area without increasing the chip size or sacrificing the area of ​​other areas.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] A method for manufacturing an LED chip, comprising:

[0008] Provide a substrate;

[0009] An epitaxial stack is grown on one side surface of the substrate;

[0010] A hard mask is fabricated on the surface of the epitaxial stack that is away from the substrate;

[0011] A first photoresist layer with a dicing pattern is formed on the side of the epitaxial stack away from the substrate; the thickness of the first photoresist layer at the periphery of the dicing pattern is less than the thickness of other areas, and exposes a portion of the surface of the hard mask.

[0012] The epitaxial stack is etched to form dicing channels on the exposed substrate surface. The sidewalls of the dicing channels are composed of N inclined planes, where N is a positive integer greater than or equal to 2. The etching of the epitaxial stack includes two consecutive stages. In the first stage, the first photoresist layer is used as a mask to etch the hard mask to expose a portion of the epitaxial stack. In the second stage, the exposed epitaxial stack is etched to form dicing channels. In the second stage, the first photoresist layer is used as a mask. After the first photoresist layer around the dicing channel pattern is consumed and the exposed portion of the hard mask is exposed, the exposed hard mask is used as a mask for etching.

[0013] Remove the remaining hard mask and the first photoresist layer.

[0014] Preferably, in the second stage: during the period when the first photoresist layer is used as a mask, etching is performed to the surface of the exposed substrate portion to form an initial dicing channel with a beveled sidewall; during the period when the hard mask is used as a mask, a portion of the sidewall of the initial dicing channel is etched to become steeper to form a dicing channel with a sidewall composed of N beveled segments.

[0015] Preferably, the hard mask has N-1 layers;

[0016] When the number of hard mask layers is greater than 1, the density of each hard mask is different.

[0017] Preferably, the sidewalls of the cutting channel are subjected to wet passivation treatment.

[0018] Preferably, when fabricating the first photoresist layer with the dicing pattern, a photoresist with a thickness greater than 5 micrometers is first coated on the side of the epitaxial stack opposite to the substrate, and the dicing pattern is formed through photolithography, development and hardening steps.

[0019] Preferably, the material of each of the hard masks includes SiN. x Al2O3, SiO x One of the following: HfO2, ZrO2, Ta2O5, Ti3O5, Al, Cu, and Ti;

[0020] The total thickness of the hard mask is 0.6 micrometers to 1 micrometer, including the endpoint values.

[0021] Preferably, N is 2; the sidewall of the cutting channel includes a first inclined surface and a second inclined surface arranged sequentially along the direction close to the substrate; the angle between the first inclined surface and the horizontal plane is θ1, and the angle between the second inclined surface and the horizontal plane is θ2, where θ1 < 50° and θ2 > 60°; the vertical height from the lowest point to the highest point of the first inclined surface is H1, and the vertical height from the lowest point to the highest point of the second inclined surface is H2, H1 / H2 ≥ 1, and H1 > 2.4 micrometers.

[0022] Preferably, the etching gases in the first stage and the second stage are a first gas and a second gas, respectively;

[0023] The etching rate of the first gas on the hard mask is greater than the etching rate of the second gas on the hard mask;

[0024] In the second stage, the etching rate of the epitaxial stack is increased by changing the gas composition ratio of the second gas and increasing the total flow rate of the second gas during etching.

[0025] When fabricating a hard mask, by adjusting the composition ratio of the growth gas, a non-stoichiometric hard mask can be obtained, thereby reducing the selectivity ratio between the epitaxial stack and the hard mask during etching.

[0026] Preferably, the material of the hard mask is SiO2. x The material of the etched epitaxial stack is GaN;

[0027] The first gas includes CF4 and Ar;

[0028] The second gas includes Cl2, BCl3, and Ar;

[0029] When fabricating a hard mask, the N2O / SiH4 ratio is reduced to obtain a non-stoichiometric SiO2. x layer;

[0030] In the second stage, the etching rate of the epitaxial stack is increased by increasing the Cl2 / BCl3 ratio and increasing the total flow rate of Cl2, BCl3 and Ar.

[0031] The N2O / SiH4 ratio is 0.3-1, including the endpoint values;

[0032] The Cl2 / BCl3 ratio is 10-15, including the endpoints;

[0033] The total flow rate of Cl2, BCl3, and Ar is 180 sccm - 230 sccm, including endpoint values.

[0034] The present invention also provides an LED chip, characterized in that it is manufactured by the method of manufacturing an LED chip according to any one of claims 1-9.

[0035] Compared with existing technologies, the technical solution provided by this invention has at least the following advantages:

[0036] 1. The method for fabricating this LED chip utilizes the different etch selectivity ratios among the first photoresist layer, hard mask, and epitaxial stack. In the first stage, the pattern of the first photoresist layer is copied to the hard mask layer. In the second stage of etching, the first photoresist is used as a mask for etching. Since the first photoresist layer is also consumed during etching, albeit at a slower rate, and the thickness of the first photoresist layer at the periphery of the dicing pattern is less than that in other areas, it will be consumed first, exposing part of the hard mask as a mask. This makes the sidewalls of the dicing pattern steeper and composed of N inclined planes. In this way, while keeping the bottom width of the dicing pattern unchanged, the top width of the dicing pattern is reduced, reserving more space for MESA mesa expansion. This achieves the expansion of the MESA mesa area without increasing the chip size or sacrificing the area of ​​other areas.

[0037] In addition, since the LED chip manufacturing method uses a first photoresist layer and a hard mask as masks for etching and cutting paths in sequence, a cutting path with N bevels can be formed in one etching step, simplifying the process steps; compared with using only a hard mask, the combination of the first photoresist layer and the hard mask can reduce the thickness of the hard mask, thereby reducing the deposition time of the hard mask, greatly saving time and material costs of the hard mask, and can avoid the cutting path sidewalls being too steep, which would affect the coverage of the subsequent cover film layer.

[0038] 2. In the second stage, the first photoresist layer is used as a mask to etch until the surface of the substrate is exposed. At this time, due to the influence of the morphology of the first photoresist layer and the etching selectivity ratio of the epitaxial stack / first photoresist layer, the sidewall of the initial dicing channel is a slope with a small angle to the horizontal plane, and the opening size gradually decreases along the direction closer to the substrate. Then, during the period when the hard mask is used as a mask, part of the sidewall of the initial dicing channel becomes steeper after etching, making the bottom of the dicing channel wider. This ensures that the bottom width of the dicing channel after the second stage is not smaller than the bottom of the dicing channel in the prior art. In this way, the dicing pattern of the first photoresist layer can be set smaller, providing more space for MESA mesa expansion.

[0039] 3. When the number of hard mask layers is greater than 1, the density of each hard mask is different. By changing the selection ratio of hard mask and epitaxial stack, the sidewall of the cut channel is composed of more than two inclined planes.

[0040] 4. When N is large, the sharp corners at the joints of the bevels on the sidewall of the cutting track are relatively smooth, and the impact on the subsequent covering film layer can be ignored; however, when N is small and the joints of the sharp corners are not smooth enough, in order to avoid the impact of the sharp corners on the subsequent film layer, the sidewall of the cutting track can be wet passivated, so that it is not necessary to make an additional film layer for protection on the sidewall of the cutting track.

[0041] 5. If over-etching will increase the top width of the dicing path, the thickness of the photoresist applied when making the first photoresist is set to be greater than 5 micrometers to ensure that there is still photoresist residue on the hard mask after the second stage of etching, thus avoiding over-etching.

[0042] 6. If the total thickness of the hard mask is too large, it will increase the deposition time of the hard mask and make the sidewall angle of the cut track too steep. If the total thickness of the hard mask is too small, the sidewall cannot reduce the width of the top of the cut track without reducing the bottom width of the cut track. Therefore, it is better to set the total thickness of the hard mask to 0.6 micrometers to 1 micrometer.

[0043] 7. When the sidewall of the cutting channel is composed of two inclined planes, θ1<50°, θ2>60°, H1 / H2≥1, and H1>2.4 micrometers are set to ensure that the angle of the sidewall of the cutting channel is relatively gentle and will not affect the coverage of the subsequent film layer.

[0044] 8. Since the primary purpose of the first stage is to remove the hard mask and expose the epitaxial stack, while the primary purpose of the second stage is to etch the epitaxial stack, using the same gas for etching throughout would increase etching time due to the different objectives of the two stages. Therefore, a gas more suitable for etching the hard mask can be selected in the first stage to reduce the time occupied by the first stage. In the second etching stage, the etching rate of the epitaxial stack can be increased by changing the gas composition ratio of the second gas and increasing the total flow rate of the second gas, saving time and improving the sidewall angle of the initial kerf formed in the second stage, which helps to better connect the N-segment bevels. Adjusting the growth gas ratio to obtain a non-stoichiometric hard mask reduces the etch selectivity ratio of the epitaxial stack / hard mask during etching, saving time and avoiding excessively steep sidewalls of the kerf, which would result in poor coverage if other films are subsequently applied. In summary, the above settings save time overall, and the N-segment bevels of the kerf sidewalls can be better connected. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0046] Figure 1 This is a flowchart of a method for manufacturing an LED chip in one embodiment;

[0047] Figure 2 This is a schematic diagram of the structure of an epitaxial stack grown on a substrate in one embodiment;

[0048] Figure 3This is a schematic diagram of a structure in which grooves are machined on an epitaxial laminate in one embodiment;

[0049] Figure 4 for Figure 3 A schematic diagram of a local area structure after the hard mask and the first photoresist layer have been fabricated;

[0050] Figure 5-6 for Figure 4 A schematic diagram of the process of etching to form cutting lines;

[0051] Figure 7 for Figure 3 A structural diagram showing the completed cutting path;

[0052] Figure 8 This is a schematic diagram of another embodiment of the cutting channel;

[0053] Figure 9 This is a flowchart of a method for manufacturing an LED chip in another embodiment;

[0054] Figure 10-13 A schematic diagram of the manufacturing process after the dicing lines are made for the chip;

[0055] Figure 14 This is a schematic diagram of an embodiment of an LED chip.

[0056] Figure label:

[0057] Substrate 1; First type semiconductor layer 2; Active layer 3; Second type semiconductor layer 4; Hard mask 5; First hard mask 51; Second hard mask 52; First photoresist layer 6; Cutter pattern 61; Cutter 7; First bevel 71; Second bevel 72; Initial cut 7-1; Transparent conductive layer 8; DBR reflective layer 9; N electrode 10; P electrode 11; N-type pad 12; P-type pad 13. Detailed Implementation

[0058] To make the content of this invention clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0059] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0060] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included. In this application, unless specifically stated otherwise, all numerical ranges include endpoint values.

[0061] To address the problems mentioned in the background art, this application provides a method for manufacturing an LED chip, such as... Figure 1 As shown, the method includes:

[0062] S01: A substrate 1 is provided. The substrate 1 includes, but is not limited to, a sapphire substrate, and optionally the surface of the substrate 1 may be roughened.

[0063] S02: As Figure 2 As shown, an epitaxial stack is grown on one side surface of the substrate 1. Specifically, the epitaxial stack includes a first-type semiconductor layer 2, an active layer 3, and a second-type semiconductor layer 4 stacked along a direction opposite to the substrate 1. Figure 3 As shown, the epitaxial stack includes grooves exposing a portion of the surface of the first type semiconductor layer 2. After sequentially growing the first type semiconductor layer 2, the active layer 3, and the second type semiconductor layer 4 on the substrate 1, the enlarged MESA mesa pattern is transferred to the epitaxial stack using a photolithography process, and the grooves exposing a portion of the surface of the first type semiconductor layer 2 are formed by etching. Optionally, ICP etching technology is used, and the etching gas includes Cl2, BCl3, and Ar. The depth of the grooves is preferably 1.2 micrometers to 1.6 micrometers.

[0064] In this application, one of the first type semiconductor layer 2 and the second type semiconductor layer 4 is N-type doped, and the other is P-type doped. This application uses an example where the first type semiconductor layer 2 is an N-type semiconductor layer (N-GaN) and the second type semiconductor layer 4 is a P-type semiconductor layer (P-GaN). It should be understood that the materials of the N-type and P-type semiconductor layers are not limited to GaN and can be adjusted according to actual light emission requirements. The active layer 3 can employ a multi-quantum-well structure.

[0065] S03: A hard mask 5 is fabricated on the surface of the epitaxial stack facing away from the substrate 1. Specifically, Figure 4 It shows Figure 3 In the local area of ​​the epitaxial stack and substrate 1, this application takes a horizontal structure chip as an example. The dicing channel 7 is generally etched from the first type semiconductor layer 2 until the bare substrate is exposed. Therefore, in this step, a hard mask 5 is made on at least the surface of the first type semiconductor layer 2 away from the substrate 1.

[0066] S04: As Figure 4As shown, a first photoresist layer 6 with a dicing pattern 61 is formed on the side of the epitaxial stack away from the substrate 1; the thickness of the first photoresist layer 6 at the periphery of the dicing pattern 61 is less than the thickness of other areas, and exposes part of the surface of the hard mask 5.

[0067] S05: As Figure 4-6 The epitaxial stack is etched to form a dicing channel 7 on a portion of the surface of the exposed substrate 1. The sidewalls of the dicing channel are composed of N inclined planes, where N is a positive integer greater than or equal to 2. The etching of the epitaxial stack includes two consecutive stages; the first stage uses the first photoresist layer 6 as a mask to etch the exposed portion of the epitaxial stack (with the hard mask 5 exposed by the first photoresist layer 6 as a mask). Figure 4 For example, the exposed portion of the first type semiconductor layer 2); in the second stage, the exposed epitaxial stack is etched to form a dicing channel; in the second stage, the first photoresist layer 6 is used as a mask, and after the first photoresist layer 6 around the dicing channel pattern 61 is consumed and the exposed portion of the hard mask 5 is exposed, the exposed hard mask 5 is used as a mask for etching.

[0068] S06: As Figure 7 As shown, the remaining hard mask 5 and the first photoresist layer 6 are removed. The dicing 7 separates the epitaxial stack into several independent core regions.

[0069] The method for fabricating this LED chip utilizes the different etch selectivity ratios among the first photoresist layer 6, the hard mask 5, and the epitaxial stack, such as... Figure 4 As shown, in the first stage, the pattern of the first photoresist layer 6 is copied to the hard mask layer 5, as follows: Figure 5-6 As shown, in the second stage of etching, the first photoresist 6 is used as a mask for etching. Since the photoresist is also consumed during the etching process, but at a slower rate, the thickness of the first photoresist layer 6 around the dicing pattern 61 is less than that of other areas. Therefore, it will be consumed first, exposing part of the hard mask 5 as a mask. This makes the sidewall of the dicing 7 change from one slope to N slopes. In this way, while keeping the bottom width of the dicing 7 unchanged, the top width of the dicing 7 is reduced, reserving more space for MESA mesa expansion. This allows the MESA mesa area to be expanded and the light-emitting area to be increased without increasing the chip size or sacrificing the area of ​​other areas.

[0070] In addition, since the LED chip manufacturing method uses the first photoresist layer 6 and the hard mask 5 as masks for etching the cutting path 7 in sequence, the cutting path 7 with N inclined surfaces can be formed in one etching process, simplifying the process steps. Compared with using only the hard mask 5, the combination of the first photoresist layer 6 and the hard mask 5 can reduce the thickness of the hard mask 5, thereby reducing the deposition time of the hard mask 5, greatly saving time and material costs of the hard mask 5, and can avoid the sidewalls of the cutting path 7 being too steep, which would affect the coverage of the subsequent cover film.

[0071] Based on the above embodiments, preferably, such as Figure 5-6 As shown, in the second stage: during the period when the first photoresist layer 6 is used as a mask, etching is performed to a portion of the surface of the exposed substrate 1 to form an initial dicing channel 7-1 with a beveled sidewall; during the period when the hard mask 5 is used as a mask, a portion of the sidewall of the initial dicing channel 7-1 is etched to become steeper to form a dicing channel with N beveled sidewalls.

[0072] The first photoresist layer 6 is used as a mask for etching until a portion of the substrate 1 surface is exposed. At this time, due to the influence of the morphology of the first photoresist layer 6 and the etching selectivity ratio of the epitaxial stack / first photoresist layer, the sidewall of the initial dicing 7-1 is a slope with a small angle to the horizontal plane, and the opening size gradually decreases along the direction close to the substrate 1. Then, during the period when the hard mask 5 is used as a mask, part of the sidewall of the initial dicing 7-1 becomes steeper after etching, making the bottom of the dicing 7 wider. This ensures that the bottom width of the dicing 7 after the second stage is not reduced compared to the bottom of the dicing in the prior art. In this way, the dicing pattern 61 of the first photoresist layer 6 can be set to be smaller, providing more space for MESA mesa expansion.

[0073] More preferably, the hard mask 5 has N-1 layers. When the number of hard mask 5 layers is greater than 1, the density of each hard mask 5 is different. Different densities change the selectivity ratio of the hard mask 5 and the epitaxial stack, so that the sidewall of the dicing channel 7 is composed of more than two inclined planes. That is, when N is 2, the hard mask 5 has 1 layer; when N is 3, the hard mask 5 has 2 layers; when N is 4, the hard mask 5 has 3 layers, and so on. The density of each hard mask 5 gradually decreases along the direction away from the substrate 1.

[0074] like Figure 4-6 The diagram illustrates the formation process of the dicing channel 7 when N is 2. When N is 2, a hard mask layer 5 is applied. After the initial etching in the second stage, the sidewall of the formed initial dicing channel 7-1 is a slope, with an angle θ0 between the slope and the horizontal plane. After the photoresist layer around the dicing channel pattern 61 is etched away, the epitaxial layer (shown as the first type semiconductor layer 2 in the diagram) at the bottom of the initial dicing channel 7-1, using the hard mask 5 as a mask, is etched. The angle becomes steeper, and the bottom of the dicing channel 7 widens. Figure 6As shown, the sidewall of the final dicing track 7 is composed of two inclined planes, with angles θ1 and θ2 between the two inclined planes and the horizontal plane, respectively, where θ1 is less than θ2; theoretically, θ1 and θ0 are approximately the same. Therefore, it can be seen that the bottom of the dicing track 7 will be etched wider during the second stage. Thus, it is sufficient to ensure that the bottom width of the dicing track 7 after the second stage is not reduced compared to the bottom width of the dicing track 7 in existing technologies. This allows the dicing pattern 61 of the first photoresist layer 6 to be set smaller, providing more space for MESA mesa expansion. The aforementioned horizontal plane is parallel to the surface of the substrate 1 opposite to the epitaxial stack.

[0075] When N is 2, in a preferred embodiment, as follows: Figure 6 As shown, the sidewall of the dicing channel 7 includes a first inclined surface 71 and a second inclined surface 72 arranged sequentially along the direction close to the substrate 1. The angle between the first inclined surface 71 and the horizontal plane is θ1, and the angle between the second inclined surface 72 and the horizontal plane is θ2; wherein θ1 < 50° and θ2 > 60°. The vertical height from the lowest point to the highest point of the first inclined surface 71 is H1, and the vertical height from the lowest point to the highest point of the second inclined surface 72 is H2, where H1 / H2 ≥ 1, and H1 > 2.4 micrometers. By setting these parameters, it is ensured that the angle of the sidewall of the dicing channel 7 is relatively gentle and will not affect the coverage of subsequent film layers.

[0076] like Figure 8 The diagram shows a schematic of the chip dicing track 7 when N is 3. The hard mask 5 has two layers: a first hard mask 51 and a second hard mask 52 disposed on the side of the first hard mask 51 facing away from the substrate 1. The density of the second hard mask 52 is less than that of the first hard mask 51. The angle between the three inclined planes of the dicing track 7 and the horizontal plane gradually decreases along the direction facing away from the substrate 1. Understandably, by increasing the number of hard mask layers 5, the sidewalls of the dicing track 7 can be made smoother by more inclined planes, especially for deeper dicing tracks, where more hard mask layers 5 can be set.

[0077] Based on any of the above embodiments, in a preferred embodiment, the sidewall of the cutting channel 7 is subjected to wet passivation treatment.

[0078] When N is large, the sharp corners at the joints of the bevels on the sidewall of the cutting track 7 are relatively smooth, and the impact on the subsequent covering film layer can be ignored. However, when N is small, the joints at the sharp corners are not so smooth. In order to avoid the impact of the sharp corners on the subsequent film layer (such as the passivation layer and the DBR reflective layer), the sidewall of the cutting track 7 can be subjected to wet passivation treatment. In this way, it is not necessary to make an additional film layer for protection on the sidewall of the cutting track 7.

[0079] Based on any of the above embodiments, in a preferred embodiment, when fabricating the first photoresist layer 6 with the dicing pattern 61, a photoresist with a thickness greater than 5 micrometers is first applied to the side of the epitaxial stack facing away from the substrate 1, and the dicing pattern 61 is formed through photolithography, development, and hardening steps. If over-etching causes an increase in the top width of the dicing 7, the photoresist thickness applied when fabricating the first photoresist layer 6 is set to be greater than 5 micrometers to ensure that there is still photoresist residue on the hard mask 5 after the second-stage etching is completed, thus avoiding over-etching.

[0080] Among them, such as Figure 4 As shown, after photolithography, development and hardening, the sidewalls of the dicing pattern 61 form a slope. The thickness of the slope region gradually decreases along the direction close to the substrate 1. Therefore, during etching, the first photoresist layer 6 around the dicing pattern 61 will be consumed first.

[0081] Based on any of the above embodiments, in a preferred embodiment, the material of each of the hard masks 5 includes SiN. x Al2O3, SiO x The hard mask 5 can be one of the following: HfO2, ZrO2, Ta2O5, Ti3O5, Al, Cu, or Ti. When the number of hard mask layers 5 is greater than 1, each hard mask 5 can be made of the same material with different masses or made of different materials. When using the same material, hard masks 5 with different densities can be obtained by adjusting process parameters, such as adjusting parameters like gas ratio and temperature.

[0082] Based on any of the above embodiments, in a preferred embodiment, the total thickness of the hard mask 5 is 0.6 micrometers to 1 micrometer, including the endpoint values.

[0083] If the total thickness of the hard mask 5 is too large, it will increase the deposition time of the hard mask 5 and the sidewall angle of the cut track 7 will be too steep. If the total thickness of the hard mask 5 is too small, the sidewall cannot reduce the width of the top of the cut track 7 without reducing the bottom width of the cut track 7. Therefore, it is better to set the total thickness of the hard mask 5 to be between 0.6 micrometers and 1 micrometer.

[0084] Based on any of the above embodiments, in a preferred embodiment, the etching gases in the first stage and the second stage are respectively a first gas and a second gas; the etching rate of the hard mask by the first gas is greater than the etching rate of the hard mask by the second gas.

[0085] In the second stage, the etching rate of the epitaxial stack is increased by changing the gas composition ratio of the second gas and increasing the total flow rate of the second gas during etching.

[0086] When fabricating the hard mask 5, the composition ratio of the growth gas is adjusted to obtain a non-stoichiometric hard mask 5, thereby reducing the selectivity ratio of the epitaxial stack and the hard mask 5 during etching.

[0087] This setup addresses the issue that the primary objective of the first stage is to remove the hard mask 5 to expose the first type of semiconductor layer, while the primary objective of the second stage is to etch the epitaxial stack. Since the two stages have different objectives, using the same gas for etching throughout would increase etching time. Therefore, a gas more suitable for etching the hard mask can be selected in the first stage to reduce its time commitment. In the second etching stage, the etching rate of the epitaxial stack is increased by changing the composition ratio of the second gas and increasing its total flow rate, saving time and improving the sidewall angle of the initial dicing path 7 formed in the second stage, which helps to better connect the N-segment bevels. Adjusting the growth gas ratio to obtain a non-stoichiometric hard mask 5 reduces the etch selectivity ratio of the epitaxial stack / hard mask 5 during etching, saving time and preventing the sidewalls of the dicing path 7 from being too steep, which would result in poor coverage if other films are subsequently applied. In summary, the above setup saves overall time and allows for better connection of the N-segment bevels on the sidewalls of the dicing path 7.

[0088] Based on any of the above embodiments, the material of the hard mask 5 is SiO2. x Taking GaN as an example, the material of the epitaxial stack being etched is used for illustration. The first gas includes CF4 and Ar; the second gas includes Cl2, BCl3, and Ar. With this setup, when the hard mask 5 is made of SiO2... x In the first stage of etching, CF4 and Ar are used to accelerate the etching rate of the hard mask 5, saving time and costs. That is, in the first stage, a gas with a faster etching rate can be selected for etching the hard mask 5 based on its material, and in the second stage, a gas with a faster etching rate for the epitaxial stack can be selected based on its material, thereby accelerating the etching rate at each stage and saving time and costs.

[0089] Preferably, when fabricating the hard mask 5, the N2O / SiH4 ratio is reduced to obtain non-stoichiometric SiO2. x Layer. In the second stage, the etching rate of the epitaxial stack (shown as the first type semiconductor layer 2) is increased by improving the Cl2 / BCl3 ratio and increasing the total flux of Cl2, BCl3, and Ar.

[0090] More preferably, the N2O / SiH4 ratio is 0.3-1, including the endpoint value. The Cl2 / BCl3 ratio is 10-15, including the endpoint value. The total flow rate of Cl2, BCl3, and Ar is 180 sccm - 230 sccm, including the endpoint value.

[0091] After removing the remaining hard mask 5 and the first photoresist layer 6, as follows Figure 9-13 As shown, the method for manufacturing the LED chip in this application further includes the following steps, for ease of understanding. Figure 8-11 This illustration only shows one core region; in reality, subsequent steps are performed simultaneously in all core regions.

[0092] S07: As Figure 10 As shown, a transparent conductive layer 8 is fabricated and alloyed. Specifically, the transparent conductive layer 8 is located on the surface of the second type semiconductor layer 4 facing away from the substrate 1. A transparent conductive material is deposited on the side of the epitaxial stack facing away from the substrate 1, and then photoresist is coated. After exposure, development, and hardening processes, the photoresist layer is used to obtain the desired pattern. The transparent conductive material is etched to form a transparent conductive layer 8 smaller than the MESA mesa size on the surface of the second type semiconductor layer 4 facing away from the substrate 1, and then alloying is performed. Preferably, a magnetron sputtering equipment is used for deposition; the thickness of the transparent conductive layer 8 is preferably 200nm-250nm, including the endpoint values; and a wet etching method is used.

[0093] S08: As Figure 11 As shown, an N-electrode 10 and a P-electrode 11 are fabricated. The N-electrode 10 is electrically connected to the first type semiconductor layer 2, and the P-electrode 11 is electrically connected to the second type semiconductor layer 4. Specifically, photoresist is coated on the side of the epitaxial stack facing away from the substrate 1. After photolithography, an electrode pattern is obtained. Then, electrode material is deposited by vapor deposition, retaining the electrode material in the patterned area and removing the electrode material in the remaining areas to obtain the N-electrode 10 and the P-electrode 11. Preferably, the electrode material includes one or more of Cr, Al, Ti, and Pt; the vapor deposition method can be electron beam evaporation (E-Beam).

[0094] S09: Preparation of the passivation layer (not shown in the figure). Specifically, a passivation material is deposited on the side of the epitaxial stack facing away from the substrate 1, and then vias are etched to form the passivation layer, exposing the N electrode 10 and the P electrode 11. PECVD is preferably used to deposit the passivation layer; the thickness of the passivation layer is preferably 200 nm to 250 nm, including the endpoints; the material of the passivation layer includes, but is not limited to, SiO2. x .

[0095] like Figure 12 As shown, this application uses a flip-chip LED chip as an example for illustration. Therefore, in step S09, after depositing the passivation material, a DBR reflective material needs to be stacked on the passivation material, and then through-holes are fabricated to form the passivation layer and the DBR reflective layer 9. The through-holes expose the N electrode 10 and the P electrode 11. The DBR reflective layer 9 is preferably a periodically alternating layer of SiO2 and Ti3O5, with a period number of 20-30, including the endpoint values. Electron beam evaporation is preferably used to deposit the DBR reflective material. Figure 12 The intermediate passivation layer and DBR reflective layer 9 cover the exposed surface on one side of the back substrate 1 of the core region and the sidewalls of the dicing 7. If the sidewalls of the dicing 7 are subjected to wet passivation treatment, then no additional film layer is needed to protect the sidewalls of the dicing 7, i.e. Figure 14 As shown, the passivation layer and DBR reflective layer 9 may not extend to the sidewall of the cut channel 7.

[0096] Step S10: As Figure 13 As shown, N-type pads 12 and P-type pads 13 are fabricated. Specifically, N-type pads 12 and P-type pads 13 are fabricated on the side of the DBR reflective layer 9 facing away from the substrate 1. The N-type pad 12 is electrically connected to the N-electrode 10, and the P-type pad 13 is electrically connected to the P-electrode 11. Photoresist is coated on the side of the DBR reflective layer 9 facing away from the substrate 1. After photolithography, the pad pattern is obtained. Then, the pad material is vapor-deposited, retaining the pad material in the patterned area and removing the pad material in the remaining area to obtain N-type pads 12 and P-type pads 13. Preferably, the pad material includes one or more of Cr, Al, Ti, Ni, and Au; the vapor deposition method can be electron beam evaporation (E-Beam).

[0097] Step S11: Perform grinding, polishing and cutting processes to obtain several LED chips.

[0098] This application also provides an LED chip, which is manufactured using the LED chip manufacturing method described in any of the above embodiments. Since this LED chip is manufactured using the LED chip manufacturing method described in any of the above embodiments, it has any of the aforementioned beneficial effects.

[0099] Those skilled in the art should understand that, in the disclosure of this invention, the terms "lateral", "longitudinal", "upper", "lower", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the above terms should not be construed as limiting this invention.

[0100] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0101] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for manufacturing an LED chip, characterized in that, include: Provide a substrate; An epitaxial stack is grown on one side surface of the substrate; A hard mask is fabricated on the surface of the epitaxial stack that is away from the substrate; A first photoresist layer with a dicing pattern is formed on the side of the epitaxial stack opposite to the substrate; The thickness of the first photoresist layer at the periphery of the dicing pattern is less than that in other areas, and it exposes part of the surface of the hard mask. The epitaxial stack is etched to form a cleavage on the surface of the exposed substrate portion. The sidewall of the cleavage is composed of N inclined planes, where N is a positive integer greater than or equal to 2. The etching of the epitaxial stack includes two consecutive stages. In the first stage, the first photoresist layer is used as a mask to etch the hard mask to expose the portion of the epitaxial stack. The second stage involves etching the exposed epitaxial stack to form a cutting path; In the second stage, the first photoresist layer is used as a mask. After the first photoresist layer around the dicing pattern is consumed and the exposed hard mask is removed, the exposed hard mask is used as a mask for etching. Remove the remaining hard mask and the first photoresist layer.

2. The method for manufacturing an LED chip as described in claim 1, characterized in that, In the second stage: during the period when the first photoresist layer is used as a mask, etching is performed to the surface of the exposed substrate portion to form an initial cut path with a beveled sidewall; During the period when the hard mask is used as a mask, part of the sidewall of the initial cut channel is etched to become steeper, forming a cut channel with sidewalls composed of N inclined planes.

3. The method for manufacturing an LED chip as described in claim 1, characterized in that, The hard mask has N-1 layers; when the number of hard mask layers is greater than 1, the density of each hard mask is different.

4. The method for manufacturing an LED chip as described in claim 1, characterized in that, The sidewalls of the cutting channel are subjected to wet passivation treatment.

5. The method for manufacturing an LED chip as described in claim 1, characterized in that, When fabricating the first photoresist layer with the dicing pattern, a photoresist with a thickness greater than 5 micrometers is first coated on the side of the epitaxial stack away from the substrate, and the dicing pattern is formed through photolithography, development and hardening steps.

6. A method for manufacturing an LED chip as described in claim 1 or 3, characterized in that, The materials of each of the hard masks include SiN. x Al2O3, SiO x One of HfO2, ZrO2, Ta2O5, Ti3O5, Al, Cu, and Ti; the total thickness of the hard mask is 0.6 micrometers to 1 micrometer, including the endpoint values.

7. A method for manufacturing an LED chip as described in claim 1, characterized in that, The N is 2; the sidewall of the dicing channel includes a first inclined plane and a second inclined plane arranged sequentially along the direction close to the substrate; the angle between the first inclined plane and the horizontal plane is θ1, and the angle between the second inclined plane and the horizontal plane is θ2, where θ1 < 50° and θ2 > 60°; the vertical height from the lowest point to the highest point of the first inclined plane is H1, and the vertical height from the lowest point to the highest point of the second inclined plane is H2, H1 / H2 ≥ 1, and H1 > 2.4 micrometers.

8. The method for manufacturing an LED chip as described in claim 2, characterized in that, The etching gases used in the first and second stages are a first gas and a second gas, respectively. The etching rate of the first gas on the hard mask is greater than the etching rate of the second gas on the hard mask; In the second stage, the etching rate of the epitaxial stack is increased by changing the gas composition ratio of the second gas and increasing the total flow rate of the second gas during etching. When fabricating a hard mask, by adjusting the composition ratio of the growth gas, a non-stoichiometric hard mask can be obtained, thereby reducing the selectivity ratio between the epitaxial stack and the hard mask during etching.

9. The method for manufacturing an LED chip as described in claim 8, characterized in that, The hard mask is made of SiO2. x The material of the etched epitaxial stack is GaN; The first gas includes CF4 and Ar; The second gas includes Cl2, BCl3, and Ar; When fabricating a hard mask, the N2O / SiH4 ratio is reduced to obtain a non-stoichiometric SiO2. x layer; In the second stage, the etching rate of the epitaxial stack is increased by increasing the Cl2 / BCl3 ratio and increasing the total flow rate of Cl2, BCl3 and Ar. The N2O / SiH4 ratio is 0.3-1, including the endpoint values; The Cl2 / BCl3 ratio is 10-15, including the endpoints; The total flow rate of Cl2, BCl3, and Ar is 180 sccm - 230 sccm, including endpoint values.

10. An LED chip, characterized in that, It is manufactured using the method described in any one of claims 1-9.

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