Semiconductor equipment

Abstract

This helps to curb increases in manufacturing costs and chip size. [Solution] The semiconductor device of the embodiment comprises: a first resistor; a first switch element having a first terminal connected to the first resistor and a second terminal and gate connected to each other in common; a second switch element having a first terminal to which a voltage lower than a first voltage is input and a gate connected to the second terminal and gate of the first switch element; a level shifter to which a first voltage, the voltage at the first terminal of the second switch element, and a first signal are input and having a first output terminal and a second output terminal; a first capacitor having a first terminal connected to the first output terminal and a second terminal connected to a first node; a third switch element having a first terminal connected to a first node and a gate controlled according to a signal output to the second output terminal; and a fourth switch element having a first terminal controlled according to a signal output to the first node, a gate connected to the second output terminal, and a second terminal to which a first voltage is input.

Description

Technical Field

[0001] Embodiments relate to semiconductor devices.

Background Art

[0002] Semiconductor devices for supplying a voltage to a load are known. Such semiconductor devices include a charge pump for boosting a voltage.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Suppress an increase in manufacturing cost and an increase in chip size.

Means for Solving the Problems

[0005] The semiconductor device of the embodiment includes: a first resistor having a first terminal to which a first voltage is input and a second terminal; a first switch element having a first terminal connected to the second terminal of the first resistor, and a second terminal and gate that are commonly connected to each other; a second switch element having a first terminal to which a second voltage lower than the first voltage is input, a gate connected to the second terminal and gate of the first switch element, and a second terminal that is grounded; a level shifter having a first input terminal to which the first voltage is input, a second input terminal connected to the first terminal of the second switch element, a third input terminal to which a first signal is input, a first output terminal, and a second output terminal; and a first terminal connected to the first output terminal of the level shifter and a second terminal connected to a first node. The level shifter comprises a first capacitor, a third switch element having a first terminal connected to the first node and a gate controlled according to a signal output to the second output terminal of the level shifter, and a fourth switch element having a first terminal controlled according to a signal output to the first node, a gate connected to the second output terminal of the level shifter together with the gate of the third switch element, and a second terminal to which the first voltage is input. The level shifter is configured to output a second signal, which has been level-shifted to a higher voltage than the first signal, from the first output terminal based on the first voltage, the second voltage, and the first signal, and to output a third signal, which is the inverted signal of the second signal, from the second output terminal. [Brief explanation of the drawing]

[0006] [Figure 1] A block diagram showing an example of the configuration of a semiconductor device according to the embodiment. [Figure 2] A circuit diagram illustrating an example of the configuration of a semiconductor device according to the embodiment. [Figure 3] A timing chart illustrating the operation of a semiconductor device according to an embodiment. [Figure 4] A circuit diagram showing parts of a semiconductor device for explaining the operation of a semiconductor device according to an embodiment. [Figure 5] A circuit diagram showing parts of a semiconductor device for explaining the operation of a semiconductor device according to an embodiment. [Modes for carrying out the invention]

[0007] Embodiments will be described below with reference to the drawings. In the following description, components having the same function and configuration will be denoted by the same reference numerals.

[0008] 1. Embodiment A semiconductor device according to an embodiment will be described.

[0009] First, the configuration of the semiconductor device according to this embodiment will be described.

[0010] The configuration of the semiconductor device according to this embodiment will be explained using Figure 1. Figure 1 is a block diagram showing an example of the configuration of the semiconductor device according to this embodiment.

[0011] The semiconductor device 1 is, for example, an IC (Integrated Circuit) chip. The semiconductor device 1 generates a voltage Vout based on, for example, a voltage Vin supplied from an external power source 2 and a signal clk1. Voltage Vout is higher than voltage Vin (Vout > Vin). Signal clk1 is a clock signal. The "L (Low)" level voltage of signal clk1 is, for example, voltage VSS. Voltage VSS is the ground voltage. The "H (High)" level voltage of signal clk1 is, for example, voltage VDD. Voltage VDD is higher than voltage VSS (VDD > VSS). As described above, the semiconductor device 1 is configured to boost voltage Vin using the clock signal. Then, the semiconductor device 1 outputs voltage Vout to load 3.

[0012] The semiconductor device 1 includes terminals PVin, Pclk, and PVout.

[0013] Terminal PVin is connected, for example, to an external power source 2 of the semiconductor device 1. A voltage Vin is supplied to terminal PVin from the power source 2.

[0014] To the terminal Pclk, for example, a signal clk1 is supplied from a circuit outside the semiconductor device 1. Note that in the embodiment, an example where the signal clk1 is input from outside the semiconductor device 1 is shown, but it is not limited thereto. The signal clk1 may be generated by the internal configuration of the semiconductor device 1.

[0015] The terminal PVout is connected to the load 3. From the terminal PVout, a voltage Vout is supplied to the load 3.

[0016] Next, the circuit configuration of the semiconductor device 1 will be described with reference to FIG. 2. FIG. 2 is a circuit diagram for explaining an example of the configuration of the semiconductor device according to the embodiment.

[0017] The semiconductor device 1 includes switch elements Q1, Q2, Q3, Q4, Q5, Q6, Q7, and Q8, resistors R1 and R2, an operational amplifier AMP, a level shifter LS, capacitors CP1 and CP2, and circuits C1 and C2.

[0018] The switch elements Q2, Q3, Q6, and Q8 are, for example, N-type MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors). The switch element Q2 is, for example, an N-type MOSFET with a higher breakdown voltage than the switch elements Q3, Q6, and Q8. The switch elements Q1, Q4, Q5, and Q7 are, for example, P-type MOSFETs. The switch elements Q1 and Q4 are, for example, P-type MOSFETs with a higher breakdown voltage than the switch elements Q5 and Q7.

[0019] One end of the resistor R1 is connected to the terminal PVin. The other end of the resistor R1 is connected to the node N1. The resistor R1 is a resistor whose resistance value changes depending on temperature. The resistor R1 is configured such that, for example, the resistance value decreases as the temperature increases. The resistor R1 is, for example, a poly resistor (polysilicon resistor).

[0020] Note that the resistor R is configured such that the voltage of the node N1 becomes equal to the voltage (Vin - VDD).

[0021] One end of the switch element Q1 is connected to the node N1. The gate and the other end of the switch element Q1 are commonly connected to each other.

[0022] One end of the switch element Q2 is connected to the gate and the other end of the switch element Q1.

[0023] The operational amplifier AMP has a non-inverting input terminal (+), an inverting input terminal (-), and an output terminal. A voltage Vref that is independent of temperature is supplied to the non-inverting input terminal (+) of the operational amplifier AMP. The voltage Vref is, for example, a voltage lower than the voltage (Vin - VDD) (Vref < (Vin - VDD)). The inverting input terminal (-) of the operational amplifier AMP is connected to the other end of the switch element Q2. The output terminal of the operational amplifier AMP is connected to the gate of the switch element Q2. The operational amplifier AMP compares the magnitude relationship between the voltage Vref at the non-inverting input terminal (+) and the voltage at the inverting input terminal (-) (the voltage at the other end of the switch element Q2). When the voltage at the other end of the switch element Q2 is higher than the voltage Vref, a low voltage is output from the output terminal of the operational amplifier AMP. When the voltage at the other end of the switch element Q2 is less than or equal to the voltage Vref, a high voltage is output from the output terminal of the operational amplifier AMP. Through the above operation, the operational amplifier AMP is configured to make the voltage at the other end of the switch element Q2 equivalent to the temperature-independent voltage Vref.

[0024] One end of the resistor R2 is connected to the other end of the switch element Q2 and the inverting input terminal (-) of the operational amplifier AMP. The other end of the resistor R2 is grounded. Similar to the resistor R1, the resistor R2 is a resistor whose resistance value changes depending on temperature. Similar to the resistor R1, the resistor R2 is configured such that, for example, the resistance value decreases as the temperature increases. Similar to the resistor R1, the resistor R2 is, for example, a polysilicon resistor (polysilicon resistance). Since the voltage applied to the resistor R2 is the temperature-independent voltage Vref, the current flowing through the resistor R2 increases as the temperature increases. Since the same current also flows through the resistor R1, the voltage applied to the resistor R1 becomes independent of temperature. Thereby, the voltage at the node N1 is configured to be the voltage (Vin - VDD) without depending on temperature.

[0025] In the configuration described above, the section including the switching element Q2, the operational amplifier AMP, and the resistor R2 functions as a current source.

[0026] One end of switch element Q3 is connected to terminal PVin. The other end of switch element Q3 is connected to node N2. The gate of switch element Q3 is connected to node N1.

[0027] One end of switch element Q4 is connected to node N2. The other end of switch element Q4 is grounded. The gate of switch element Q4 is connected in common to the gate of switch element Q1 and the other end of switch element Q1.

[0028] In the configuration described above, the portion including the switch elements Q1 and Q4 is configured such that the voltage VN1 at node N1 and the voltage VN2 at node N2 are equal to each other. That is, voltages VN1 and VN2 are equivalent to the voltage (Vin-VDD).

[0029] Furthermore, in the configuration described above, switch element Q3 functions as a pull-up circuit for node N2. Switch element Q4 functions as a pull-down circuit for node N2.

[0030] To elaborate, for example, if voltage VN2 falls below voltage VN1 (voltage (Vin-VDD)) due to various influences, switch element Q3 acts as a pull-up circuit. This makes voltage VN2 equal to voltage VN1 (voltage (Vin-VDD)). Also, for example, if voltage VN2 rises above voltage VN1 (voltage (Vin-VDD)) due to various influences, switch element Q4 acts as a pull-down circuit. This makes voltage VN2 equal to voltage VN1 (voltage (Vin-VDD)).

[0031] Furthermore, the section including switch elements Q1, Q3, and Q4 functions as a buffer circuit capable of driving large currents. As a result, the currents flowing through switch element Q3 and switch element Q4 can be made larger than, for example, the currents flowing through resistor R1 and switch element Q2, and node N2 becomes a voltage source (voltage (Vin-VDD)) with low impedance.

[0032] The level shifter LS includes a first input terminal, a second input terminal, a third input terminal, a first output terminal, and a second output terminal. The first input terminal of the level shifter LS is connected to terminal PVin. This inputs the voltage Vin to the level shifter LS. The second input terminal of the level shifter LS is connected to node N2. This inputs the voltage VN2, which is equivalent to the voltage (Vin-VDD), to the level shifter LS. The signal clk1 is input to the third input terminal of the level shifter LS. The level shifter LS generates signals clk2 and clk2b using the input voltages Vin and VN2, as well as signal clk1. Signals clk2 and clk2b are clock signals, respectively. Signal clk2b is the inverted signal of signal clk2. The generation of signals clk2 and clk2b will be described later. Signal clk2 is output from the first output terminal of the level shifter LS. The signal clk2b is output from the second output terminal of the level shifter LS.

[0033] More specifically, regarding the generation of signals clk2 and clk2b, the level shifter LS generates signals clk2 and clk2b so that the "H" level voltage (high voltage) of signals clk2 and clk2b is equivalent to the voltage Vin. In addition, the level shifter LS generates signals clk2 and clk2b so that the "L" level voltage (low voltage) of signals clk2 and clk2b is equivalent to the voltage (Vin-VDD).

[0034] Circuit C1 includes a first input terminal, a second input terminal, a third input terminal, and an output terminal. The first input terminal of circuit C1 is connected to the first output terminal of the level shifter LS. The second input terminal of circuit C1 is connected to terminal PVin. The third input terminal of circuit C1 is connected to node N2. Circuit C1 generates a signal clk2' based on the signal clk2. Signal clk2' is a clock signal generated such that a "H" level voltage becomes voltage Vin and a "L" level voltage becomes voltage (Vin-VDD), similar to signal clk2. Signal clk2' is output from the output terminal of circuit C1. Circuit C1 has a configuration in which, for example, two inverter circuits are connected in series. With such a configuration, circuit C1 is provided to supply sufficient current to drive the charge pump when supplying the clock signal generated by the level shifter LS to the charge pump described later.

[0035] Circuit C2 includes a first input terminal, a second input terminal, a third input terminal, and an output terminal. The first input terminal of circuit C2 is connected to the second output terminal of the level shifter LS. The second input terminal of circuit C2 is connected to terminal PVin. The third input terminal of circuit C2 is connected to node N2. Circuit C2 generates a signal clk2b' based on the signal clk2b. Signal clk2b' is a clock signal generated such that a "H" level voltage becomes voltage Vin and a "L" level voltage becomes voltage (Vin-VDD), similar to signal clk2b. Signal clk2b' is the inverted signal of signal clk2b. Signal clk2b' is output from the output terminal of circuit C2. Circuit C2 has a configuration in which two inverter circuits are connected in series, for example, similar to circuit C1. With this configuration, circuit C2 is provided to supply sufficient current to drive the charge pump, for example, when supplying the clock signal generated by the level shifter LS to the charge pump, similar to circuit C1.

[0036] One end of capacitor CP1 is connected to the output terminal of circuit C1. The other end of capacitor CP1 is connected to node N3. With this configuration, a signal based on signal clk2' can be supplied to node N3 via capacitor CP1.

[0037] One end of capacitor CP2 is connected to the output terminal of circuit C2. The other end of capacitor CP2 is connected to node N4. With this configuration, node N4 can be supplied with a signal based on signal clk2b' via capacitor CP2.

[0038] One end of the switch element Q5 is connected to node N3. The gate of the switch element Q5 is connected to node N4. The other end of the switch element Q5 is connected to terminal PVout. The switch element Q5 is configured to be ON while the voltage Vin is applied to node N4. The switch element Q5 is also configured to be OFF while the voltage (Vin + VDD) is applied to node N4.

[0039] One end of switch element Q6 is connected to node N3. The gate of switch element Q6, along with the gate of switch element Q5, is connected to node N4. The other end of switch element Q6 is connected to terminal PVin. Switch element Q6 is configured to be ON while a voltage (Vin + VDD) is applied to node N4. Switch element Q6 is also configured to be OFF while a voltage Vin is applied to node N4.

[0040] One end of switch element Q7 is connected to node N4. The gate of switch element Q7 is connected to node N3. The other end of switch element Q7 is connected to terminal PVout, along with the other end of switch element Q5. Switch element Q7 is configured to be ON while the voltage Vin is applied to node N3. Switch element Q7 is also configured to be OFF while the voltage (Vin + VDD) is applied to node N3.

[0041] One end of switch element Q8 is connected to node N4. The gate of switch element Q8, along with the gate of switch element Q7, is connected to node N3. The other end of switch element Q8 is connected to terminal PVin. Switch element Q8 is configured to be ON while a voltage (Vin + VDD) is applied to node N3. Switch element Q8 is also configured to be OFF while a voltage Vin is applied to node N3.

[0042] Switch elements Q5 to Q8, as well as capacitors CP1 and CP2, function as charge pumps.

[0043] Next, the operation of the semiconductor device 1 according to the embodiment will be explained using Figures 3, 4, and 5. Figure 3 is a timing chart for explaining the operation of the semiconductor device according to the embodiment. Figure 3 shows the signals clk1, clk2, and clk2b in the operation of the semiconductor device 1, as well as the voltage VN3 at node N3 and the voltage VN4 at node N4. Figures 4 and 5 are circuit diagrams showing parts of the semiconductor device for explaining the operation of the semiconductor device according to the embodiment.

[0044] During the operation of the semiconductor device 1, as described above, the signal clk1 is input to the semiconductor device 1 as a clock signal. The period T1 during which the signal clk1 is at the "H" level and the period T2 during which the signal clk1 is at the "L" level have, for example, equivalent lengths.

[0045] In semiconductor device 1, based on the above configuration, signals clk2 and clk2b, which are inverted signals of each other, are generated based on signal clk1 and voltage Vin. Signal clk2 has a "H" level during period T1 and a "L" level during period T2. Signal clk2b has a "L" level during period T1 and a "H" level during period T2. Furthermore, the voltages of signals clk2' and clk2b' based on signals clk2 and clk2b change in the same way as signals clk2 and clk2b, so their figures are omitted from the illustration.

[0046] Furthermore, while signals clk2 and clk2' are at the "H" level and signals clk2b and clk2b' are at the "L" level, the charge pump, as described later, operates so that the voltage VN3 is set to (Vin + VDD) by capacitor CP1. On the other hand, the voltage VN4 is set to the voltage Vin.

[0047] Furthermore, while signals clk2 and clk2' are at the "L" level and signals clk2b and clk2b' are at the "H" level, the voltage VN4 is set to (Vin + VDD) by capacitor CP2 due to the operation of the charge pump described later. On the other hand, voltage VN3 is set to voltage Vin.

[0048] The operation of the charge pump during period T1 will be explained using Figure 4.

[0049] The capacitor CP1, charged by the operation during period T2 described later, and the signal clk2', which is set to voltage Vin, cause voltage VN3 to become voltage (Vin + VDD). As a result, switch element Q7 is turned off and switch element Q8 is turned on. Therefore, voltage VN4 is set to be equivalent to voltage Vin. Consequently, switch element Q5 is turned on and switch element Q6 is turned off. In this way, during period T1, a voltage approximately equivalent to voltage (Vin + VDD) is supplied to terminal PVout via the ON switch element Q5.

[0050] Furthermore, the voltage Vin input via terminal PVin charges the capacitor CP2 via the ON-state switch element Q8, based on the signal clk2b' which is defined as voltage (Vin-VDD).

[0051] The operation of the charge pump during period T2 will be explained using Figure 5.

[0052] During the operation of period T1, the capacitor CP2 is charged, and the signal clk2b', which is the voltage Vin, causes the voltage VN4 to become (Vin + VDD). As a result, switch element Q5 is turned off and switch element Q6 is turned on. Therefore, the voltage VN3 is equivalent to the voltage Vin. Consequently, switch element Q7 is turned on and switch element Q8 is turned off. In this way, during period T2, a voltage approximately equivalent to (Vin + VDD) is supplied to terminal PVout via the ON switch element Q7.

[0053] Furthermore, the voltage Vin input via terminal PVin charges capacitor CP1 via the ON-state switch element Q6, based on the signal clk2' which is defined as voltage (Vin-VDD).

[0054] As described above, during the operation of semiconductor device 1, a voltage (Vin + VDD) is output from terminal PVout to load 3.

[0055] According to the semiconductor device 1 of the embodiment, the semiconductor device 1 comprises a resistor R1, switch elements Q1, Q4, Q5, and Q6, a level shifter LS, and a capacitor CP1. The resistor R1 has a first terminal to which a voltage Vin is input. The switch element Q1 has a first terminal connected to the second terminal of the resistor R1, and a second terminal and a gate that are connected in common to each other. The switch element Q4 has a first terminal to which a voltage (Vin-VDD) is input, a gate connected to the second terminal and gate of the switch element Q1, and a second terminal that is grounded. The level shifter LS has a first input terminal to which a voltage Vin is input, a second input terminal connected to the first terminal of the switch element Q4, a third input terminal to which a signal clk1 is input, a first output terminal, and a second output terminal. The level shifter LS outputs a signal clk2, which is level-shifted to a higher voltage than signal clk1, from its first output terminal, and an inverted signal clk2b, from its second output terminal, based on the voltage Vin, the voltage (Vin-VDD), and the signal clk1. Capacitor CP1 has a first terminal connected to the first output terminal of the level shifter LS and a second terminal connected to node N3. Switch element Q5 has a first terminal connected to node N3 and a gate connected to the second output terminal of the level shifter LS. Switch element Q6 has a first terminal connected to node N3, a gate connected to the second output terminal of the level shifter LS together with the gate of switch element Q5, and a second terminal to which the voltage Vin is input. With the above configuration, it is possible to suppress an increase in manufacturing costs and chip size.

[0056] To elaborate, if the "L" level voltage of the clock signal used to charge the charge pump capacitor is set to the ground voltage (as in the comparative example), the potential difference between one end of the capacitor and the other becomes larger compared to when the capacitor is charged using a clock signal with a "L" level voltage higher than the ground voltage. As a result, the semiconductor device in the comparative example requires a high-voltage capacitor. Therefore, the use of a high-voltage capacitor leads to problems such as increased cost and chip size.

[0057] According to this embodiment, a signal clk2' is input to the other end of capacitor CP1 such that the "H" level is voltage Vin and the "L" level is a voltage higher than voltage VSS (Vin-VDD). This suppresses the increase in the potential difference between one end and the other end of capacitor CP1. Therefore, it is possible to suppress the increase in the cost and size of the capacitor.

[0058] 2 Others In the embodiments described above, the semiconductor device 1 is described as having a single-stage charge pump including switch elements Q5 to Q8, but it is not limited to this. The semiconductor device 1 may also have a charge pump having multiple stages.

[0059] Although not shown in the diagram, for example, if semiconductor device 1 includes a charge pump having two stages, semiconductor device 1 further includes switch elements Q9, Q10, Q11, and Q12, and capacitors CP3 and CP4. Switch elements Q9, Q10, Q11, and Q12, and capacitors CP3 and CP4 have the same configuration as switch elements Q5 to Q8, and capacitors CP1 and CP2, respectively.

[0060] One end of capacitor CP3 is connected to the output terminal of circuit C1, similar to capacitor CP1. The other end of capacitor CP3 is connected to node N5.

[0061] One end of capacitor CP4 is connected to the output terminal of circuit C2, similar to capacitor CP2. The other end of capacitor CP4 is connected to node N6.

[0062] One end of the switch element Q9 is connected to node N5. The gate of the switch element Q9 is connected to node N6. The other end of the switch element Q9 is connected to terminal PVout.

[0063] One end of switch element Q10 is connected to node N5. The gate of switch element Q10, along with the gate of switch element Q9, is connected to node N6. The other end of switch element Q10 is connected to the other ends of switch elements Q5 and Q7. In other examples, the other ends of switch elements Q5 and Q7 are connected to terminal PVout via a stage of a charge pump including switch elements Q9, Q10, Q11, and Q12.

[0064] One end of switch element Q11 is connected to node N6. The gate of switch element Q11 is connected to node N5. The other end of switch element Q11 is connected to terminal PVout, along with the other end of switch element Q9.

[0065] One end of switch element Q12 is connected to node N6. The gate of switch element Q12, along with the gate of switch element Q11, is connected to node N5. The other end of switch element Q12, along with the other end of switch element Q10, is connected to the other ends of switch elements Q5 and Q7.

[0066] In the configuration described above, the switch elements Q5 to Q8, and capacitors CP1 and CP2 function as the first stage of the charge pump. Furthermore, the switch elements Q9 to Q12, and capacitors CP3 and CP4 function as the second stage of the charge pump.

[0067] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0068] 1... Semiconductor device, 2... Power source, 3... Load, Q1~Q8... Switching elements, LS... Level shifter, R1, R2... Resistors, AMP... Operational amplifier, CP1, CP2... Capacitors, C1, C2... Circuit.

Claims

1. A first resistor having a first terminal to which a first voltage is input and a second terminal, A first switch element having a first end connected to the second end of the first resistor, and a second end and a gate that are connected in common to each other, A second switch element having a first terminal to which a second voltage lower than the first voltage is input, a gate connected to the second terminal and gate of the first switch element, and a second terminal that is grounded, A level shifter having a first input terminal to which the first voltage is input, a second input terminal connected to the first terminal of the second switch element, a third input terminal to which the first signal is input, a first output terminal, and a second output terminal, A first capacitor having a first end connected to the first output terminal of the level shifter and a second end connected to the first node, A third switch element having a first terminal connected to the first node and a gate controlled according to a signal output to the second output terminal of the level shifter, A fourth switch element having a first terminal controlled according to a signal output to the first node, a gate connected to the second output terminal of the level shifter together with the gate of the third switch element, and a second terminal to which the first voltage is input, Equipped with, The aforementioned level shifter is Based on the first voltage, the second voltage, and the first signal, a second signal that has been level-shifted to a higher voltage than the first signal is output from the first output terminal, and a third signal, which is the inverted signal of the second signal, is output from the second output terminal. It is configured in such a way. Semiconductor equipment.

2. A first current source having a first end connected to the second end and gate of the first switch element, and a second end connected to ground, Furthermore, The semiconductor device according to claim 1.

3. The first current source is, A fifth switch element having a first end connected to the second end and gate of the first switch element, and a second end, An operational amplifier having a non-inverting input terminal to which a third voltage is input, an inverting input terminal connected to the second end of the fifth switch element, and an output terminal connected to the gate of the fifth switch element, A second resistor having a first end connected to the second end of the fifth switching element and the inverting input terminal of the operational amplifier, and a second end connected to ground, including, The semiconductor device according to claim 2.

4. A sixth switch element having a first end connected to the first end of the first resistor, a gate connected to the second end of the first resistor and the first end of the first switch element, and a second end connected to the first end of the second switch element and the second input end of the level shifter, Furthermore, The semiconductor device according to claim 3.

5. The current flowing through the sixth switching element is greater than the current flowing through the first resistor. The semiconductor device according to claim 4.

6. The first resistor and the second resistor are configured such that their resistance decreases as the temperature increases. The semiconductor device according to claim 3.

7. A second capacitor having a first end connected to the second output terminal of the level shifter and a second end connected to the second node, A fifth switch element having a first end connected to the second node and a gate controlled according to a signal output to the first node, A sixth switch element having a first end controlled according to a signal output to the second node, a gate connected to the first node together with the gate of the fifth switch element, and a second end connected to the second end of the fourth switch element, Furthermore, The gate of the third switch element and the gate of the fourth switch element are connected to the second node. The semiconductor device according to claim 1.

8. The first switching element, the fourth switching element, and the sixth switching element are N-type transistors. The second switch element, the third switch element, and the fifth switch element are P-type transistors. The semiconductor device according to claim 7.

9. The first signal, the second signal, and the third signal are clock signals. The semiconductor device according to claim 1.

10. In the second and third signals, the high-voltage state is the state having the first voltage, and the low-voltage state is the state having the second voltage. The semiconductor device according to claim 9.

Images