Integrated circuit chip, manufacturing method thereof and packaging structure

Abstract

Embodiments of the invention provide a semiconductor structure including a through-silicon via (TSV) for transferring power from a backside power rail to a front side device layer, and a feed through-silicon via (FTV) for transferring signals between a backside interconnect structure and a front side interconnect structure. The TSVs provide reduced RC latency in the semiconductor structure. The embodiment of the invention also relates to an integrated circuit chip and a manufacturing method thereof, and a packaging structure.

Description

Technical Field

[0001] This application relates to integrated circuit chips, their manufacturing methods, and packaging structures. Background Technology

[0002] Traditionally, integrated circuits (ICs) are built in a stacked manner, with transistors at the lowest level and interconnects such as vias and lines on top of the transistors to provide connections to them. Power rails, such as metal lines used for voltage sources and ground planes, are also located above the transistors and can be part of the interconnects. As integrated circuits continue to shrink, so do the power rails. This shrinkage inevitably leads to an increase in voltage drop across the power rails and an increase in the power consumption of the integrated circuit. Summary of the Invention

[0003] One aspect of this application provides an integrated circuit chip, comprising: a substrate having a first surface and a second surface opposite to the first surface; a device layer disposed on the first surface of the substrate; a first interconnect structure disposed above the first surface of the substrate, wherein the first interconnect structure includes a plurality of first conductive layers; a second interconnect structure disposed above the second surface of the substrate, wherein the second interconnect structure includes a plurality of second conductive layers, and the second interconnect structure includes a power rail configured to transmit power to the device layer; and a through-silicon via extending from one of the first conductive layers in the first interconnect structure through the substrate to one of the second conductive layers in the second interconnect structure.

[0004] Another aspect of this application provides a packaging structure including a first integrated circuit chip. The first integrated circuit chip includes: a first substrate; a first device layer disposed on the front side of the first substrate; a first front interconnect structure disposed above the front side of the first substrate; a first back interconnect structure disposed above the back side of the first substrate, wherein the first back interconnect structure includes a first power rail configured to transmit power to the first device layer; and a first through-silicon via (TSV) extending from the first front interconnect structure through the first substrate and to the first back interconnect structure; and the packaging structure further includes a second integrated circuit chip stacked with the first integrated circuit chip, wherein a hybrid bonding surface is located between the first integrated circuit chip and the second integrated circuit chip, the hybrid bonding surface includes a metal-to-metal bond, and the first TSV is electrically connected to the metal-to-metal bond.

[0005] Another aspect of this application provides a method for manufacturing an integrated circuit chip, comprising: forming a device layer on a first surface of a substrate; forming a first interconnect structure over the device layer, wherein the first interconnect structure includes a first sealing structure surrounding a through-substrate via region; forming a second interconnect structure on a second surface of the substrate, wherein the second interconnect structure includes a power rail configured to supply power to the device layer and a second sealing structure surrounding the through-substrate via region; and forming a through-substrate via extending through the second interconnect structure and the substrate and into the first interconnect structure. Attached Figure Description

[0006] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0007] Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E ,and Figure 1F A semiconductor structure according to an embodiment of the present invention is illustrated schematically;

[0008] Figure 2 This is a flowchart of a method for manufacturing a semiconductor structure according to an embodiment of the present invention;

[0009] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G , Figure 3H ,and Figure 3I The various stages of manufacturing a semiconductor structure according to an embodiment of the present invention are illustrated schematically;

[0010] Figure 4A , Figure 4B ,and Figure 4C The packaging structure according to an embodiment of the present invention is illustrated schematically;

[0011] Figures 5-13 Various packaging structures according to embodiments of the present invention are illustrated schematically. Detailed Implementation

[0012] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower part," "above," "above," "top," and "upper part" may be used herein to readily describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientations shown in the figure, spatial relative terms are intended to encompass different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0014] Some embodiments of this disclosure describe an integrated circuit die having a device layer formed on the front side of a substrate, a front interconnect structure above the device layer, a back interconnect structure formed on the back side of the substrate, and a through-silicon via (TSV) formed through the substrate and a portion of the front interconnect structure and a portion of the back interconnect structure. The back interconnect structure includes power rails, such as super power rails (SPRs). The integrated circuit die also includes a feed through via (FTV) formed in the substrate and connecting the front interconnect structure and the back interconnect structure. The integrated circuit die can be used in a system-on-a-chip (SoIC) package, wherein a second die is stacked on top of the integrated circuit die. In some embodiments, the TSV can be used to deliver power directly to the second die. In some embodiments, the TSV is configured to deliver power, for example, from package bumps such as an under-bump metallization (UBM) connector to the second integrated circuit die stacked on the integrated circuit die. In some embodiments, the FTV is configured to transmit signals. For example, the FTV can be used to transmit signals from a UBM connector to the second die via a front engagement. Using TSV in conjunction with SPR in SO IC packaging can reduce RC delay and decouple power and signal transmission.

[0015] Figure 1A , Figure 1B , Figure 1C ,and Figure 1D An integrated circuit chip 100 according to an embodiment of the present invention is shown schematically. Figure 1A This is a schematic cross-section of integrated circuit chip 100.

[0016] Figure 1A An integrated circuit chip 100 is shown disposed on a carrier wafer 101, which is connected to the front side of the integrated circuit chip 100 for back-side processing. The carrier wafer 101 provides support during manufacturing and packaging processes and will be removed from the final product, such as an IC package. Figure 1A As shown, the integrated circuit chip 100 includes a substrate 102, and a device layer 104 is formed on the front side 102f of the substrate 102. A front interconnect structure 106 is formed over the device layer 104 and the front side 102f of the substrate 102. A back interconnect structure 108 is formed on the back side 102b of the substrate 102. The front interconnect structure 106 and the back interconnect structure 108 include wires and vias formed in a dielectric layer and configured to provide electrical connections to structures formed in the substrate 102.

[0017] In some embodiments, the front interconnect structure 106 includes one or more dielectric layers 130, wherein embedded conductors 132 are present. The conductors 132 include layered metal lines and vias. The conductors 132 are arranged in a metallized pattern and embedded within the dielectric layers 130. Figure 1A As shown, conductor 132 can be arranged in n layers, where n is M0, M1, M2, ..., Mn, and n is an integer. Layer M0 is positioned closest to device layer 104, and layer Mn is the top layer. The top layer Mn of the front interconnect structure 106 can be embedded in a passivation layer made of one or more suitable dielectric materials such as silicon oxide, silicon nitride, low-k dielectric, polyimide, or combinations thereof. In some embodiments, the passivation layer, such as the top layer of dielectric layer 130 of the front interconnect structure 106, has an opening exposing the top portion of the metallized pattern for further electrical connection. In some embodiments, the front interconnect structure 106 is electrically connected to device layer 104 for routing signals, such as electrical signals, power signals, and / or ground signals, to / from it.

[0018] In some embodiments, the back-side interconnect structure 108 includes one or more dielectric layers 134 having embedded conductors 136. The conductors 136 may include layered metal lines and vias. The conductors 136 are arranged in a metallized pattern and embedded within the dielectric layers 134. Figure 1AAs shown, conductor 136 can be arranged in m layers, where m is BM0, BM1, ..., BMm, and m is an integer. Layer BM0 is positioned closest to device layer 104, and layer BMm is the top layer. The top layer BMm of the back interconnect structure 108 can be referred to as the top metal layer. The back interconnect structure 108 is electrically connected to device layer 104 for routing signals, such as electrical signals, power signals, and / or ground signals, to / from it. In some embodiments, the back interconnect structure 108 may include a back power rail.

[0019] Dielectric layers 130 and 134 may be polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), nitrides such as silicon nitride, oxides such as silicon oxide, PSG, borosilicate glass (BSG), BPSG, combinations thereof, etc., and may be patterned using photolithography and / or etching processes. In some embodiments, dielectric layers 130 and 134 are formed using suitable manufacturing techniques, such as spin coating, CVD (e.g., PECVD), etc.

[0020] Conductors 132 and 136 can be made from conductive materials, such as copper, copper alloys, aluminum, aluminum alloys, or combinations thereof. The conductive materials can be formed by electroplating or deposition. Conductors 132 and 136 are fabricated in dielectric layers 130 and 134 using metallization processes, such as damascene processes. In some embodiments, conductors 132 and 136 are formed from one or more conductive materials. Conductive materials may include copper, copper alloys, nickel, aluminum, manganese, magnesium, silver, gold, tungsten, and combinations thereof. The conductive materials can be formed by processes such as electrochemical plating, CVD such as plasma-enhanced chemical vapor deposition (PECVD), ALD, PVD, and combinations thereof.

[0021] In some embodiments, one or more FTV conductors 110 are formed in the substrate 102. The FTV conductors 110 electrically connect the front interconnect structure 106 and the back interconnect structure 108. The FTV conductors 110 may penetrate the substrate 102 to connect the front interconnect structure 106 and the back interconnect structure 108. For example, the FTV conductors 110 maintain contact between conductors 132 in layer M0 of the front interconnect structure 106 and conductors 136 in layer BMO of the back interconnect structure 108. In some embodiments, the FTV conductors 110 have a height H 110 This height is related to the thickness T of the substrate 102. 102 Basically the same. In some embodiments, the height H of the FTV conductor is... 110The diameter is in the range of approximately 0.2 μm to approximately 0.5 μm. In some embodiments, the FTV conductor 110 may be fabricated during the back-side processing prior to the formation of the back-side interconnect structure 108. In some embodiments, a dielectric pad or isolation layer may be provided between the substrate 102 and the FTV conductor 110. In some embodiments, the FTV conductor 110 may be used to transmit signals between the front-side interconnect structure 106 and the back-side interconnect structure 108.

[0022] In some embodiments, the integrated circuit chip 100 includes one or more TSV conductors 112. In some embodiments, each of the TSV conductors 112 is formed to pass through at least a portion of the front interconnect structure 106, the substrate 102, and at least a portion of the back interconnect structure 108. In some embodiments, such as Figure 1A As shown, TSV conductor 112 connects the conductors in the topmost layer of the front interconnect structure 106 and the back interconnect structure 108. The topmost layer is the layer located furthest from the substrate 102. In some embodiments, TSV conductor 112 connects the conductor 136 in the top metal layer BMm of the back interconnect structure 108 and the conductor 132 in the topmost layer Mn of the front interconnect structure 106, as shown. Figure 1A As shown in the image.

[0023] Alternatively, the TSV conductor 112 is connected between conductors in other layers of the front interconnect structure 106 and the back interconnect structure 108. For example, the TSV conductor 112 is connected between conductor 136 in the top metal layer BMm of the back interconnect structure 108 and conductor 132 in the middle layer Mn-x of the front interconnect structure 106.

[0024] The TSV conductor 112 extends through the substrate 102. The TSV conductor 112 can be formed during the fabrication of the back-side interconnect structure 108. For example, the TSV conductor 112 can be formed between the formation of layer BMm-1 and the formation of layer BMm. In some embodiments, a dielectric pad or insulating layer can be disposed around the TSV conductor 112.

[0025] In some embodiments, the TSV conductor 112 can be used to transmit power to a second integrated circuit chip vertically stacked above the integrated circuit chip 100. The second integrated circuit chip can be bonded to the integrated circuit chip 100 above the front interconnect structure 106 or above the back interconnect structure 108. The second integrated circuit chip can have the same structure or a different structure.

[0026] In some embodiments, a sealing structure 114 is formed around the TSV conductor 112. The sealing structure 114 is configured to protect the device layer 104, dielectric layers 130, 134, and conductors 132 in the front interconnect structure 106 and conductors 136 in the back interconnect structure 108 during the formation of the TSV conductor 112. The sealing structure 114 may include conductive materials that form a continuous structure around one or more TSV conductors 112 in the dielectric layers 130, 134 and the substrate 102.

[0027] Figure 1B This is a partial enlarged view of the integrated circuit chip 100, showing details of the device layer 104. In some embodiments, the device layer 104 includes various semiconductor devices configured to implement one or more circuit functions. In some embodiments, the device layer 104 may include a plurality of transistors 116. The transistors 116 are interconnected with a front interconnect structure 106 and a back interconnect structure 108 to implement one or more functions, including, for example, a memory structure of a memory cell, a processing structure of a logic cell, an input / output (I / O) circuit of an I / O cell, etc. It should be understood that, in this disclosure, the number of transistors 116 included in a semiconductor device and the number of semiconductor devices included in the integrated circuit chip 100 are not limited, and each may be one or more. For example, one or more transistors 116 may be present in a semiconductor device, and / or one or more semiconductor devices may be present in an integrated circuit chip 100.

[0028] exist Figure 1B The image shows a multi-channel transistor. Transistor 116 includes two or more channel regions 120 formed above the front side 102f of substrate 102. Source / drain regions 118 are formed at the ends of the channel regions 120, and a gate structure 122 surrounds the channel regions 120. Spacers, such as gate sidewall spacers (not shown) and internal spacers, may be formed on the gate structure 122.

[0029] Substrate 102 may include a single-crystal semiconductor material, such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. Depending on the circuit design, substrate 102 may include various doping configurations. For example, substrate 102 may include a p-doped region or p-well and an n-doped region or n-well. One or more n-type devices, such as nFETs, will be formed above and / or inside the p-well. One or more p-type devices, such as pFETs, will be formed above and / or inside the n-well. In some embodiments, the p-well and n-well may be separated by one or more insulators (e.g., STI).

[0030] The channel region 120 includes a semiconductor material, such as an epitaxially grown semiconductor layer. In some embodiments, the channel region 120 may include: silicon; Ge; compound semiconductors, such as SiC, GeAs, GaP, InP, InAs, and / or InSb; alloy semiconductors, such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP; or combinations thereof.

[0031] The source / drain region 118 can be an epitaxially grown semiconductor material. The source / drain region 118 can be doped for n-type and p-type devices. In some embodiments, the epitaxial source / drain region 118 for an n-type device can include one or more layers of Si, SiP, SiC, and SiCP. The epitaxial source / drain region 118 for an n-type device can include n-type dopants such as phosphorus (P) and arsenic (As). In some embodiments, the epitaxial source / drain region 118 can be a Si layer including a phosphorus (P) dopant. The epitaxial source / drain region 118 for a p-type device can include one or more layers of Si, SiGe, or Ge, having a p-type dopant such as boron (B), for p-type devices such as pFETs. In some embodiments, the epitaxial source / drain region 118 can be a SiGe material including boron as a dopant. The epitaxial source / drain regions 118 can be formed by any suitable method, such as CVD, CVD epitaxy, molecular beam epitaxy (MBE), or any suitable deposition technique.

[0032] In some embodiments, the gate structure includes a gate dielectric layer and a gate electrode. The gate dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material, or a combination thereof. It should be noted that high-k dielectric materials are typically dielectric materials having a dielectric constant greater than 4 or even greater than about 10. High-k dielectric materials include metal oxides. Examples of metal oxides used for high-k dielectric materials include oxides of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, and / or combinations thereof. In some embodiments, the gate dielectric layer is a high-k dielectric layer having a thickness in the range of about 10 angstroms to 30 angstroms. The gate dielectric layer is formed using suitable processes, such as atomic layer deposition (ALD), chemical vapor deposition (CVD) such as flowable chemical vapor deposition (FCVD), physical vapor deposition (PVD), thermal oxidation, ultraviolet ozone oxidation, or a combination thereof. The gate electrode may comprise a single-layer or multi-layer structure. In some embodiments, the gate electrode may be a metal gate comprising a metal, a metal alloy, a metal silicide, or a combination thereof. Alternatively, the gate electrode may comprise a semiconductor material. For example, the gate electrode may be made of undoped or doped polycrystalline silicon, amorphous silicon, or a combination thereof. The gate electrode may be formed using suitable processes such as ALD, CVD, PVD, deposition, or a combination thereof.

[0033] In some embodiments, spacers are formed above the sidewalls of the gate structure 122. The spacers may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, fluorine-doped silicate glass (FSG), low-k dielectric materials, or combinations thereof. It should be noted that low-k dielectric materials are typically dielectric materials having a dielectric constant below 3.9. The spacers may have a multilayer structure comprising one or more pad layers. The pad layers comprise dielectric materials such as silicon oxide, silicon nitride, and / or other suitable materials.

[0034] Various dielectric materials are formed between the conductive and semiconductor materials of transistor 116, such as isolation regions, interlayer dielectric (ILD) layers, spacers, pads, and contact etch stop layers (CESL). For clarity, in Figures 1A-1D These dielectric materials are not shown or labeled in the text.

[0035] A gate contact 124 is provided between the gate structure 122 and the conductors in the front interconnect structure 106 or the back interconnect structure 108. In some embodiments, such as Figure 1BAs shown, the gate contact 124 is embedded in the dielectric material 125 above the front side 102f of the substrate 102 and contacts the conductor 132 of the front interconnect structure 106. In particular, the gate contact 124 contacts the conductor 132 in layer M0 of the front interconnect structure 106.

[0036] In some embodiments, the source / drain region 118 is connected to the front interconnect structure 106 and / or the back interconnect structure 108. In some embodiments, a front source / drain contact 126 is formed between the source / drain region 118 and the front interconnect structure 106. Specifically, the front source / drain contact 126 extends through the dielectric material on the front side 102f of the substrate 102 and contacts the conductor 132 in layer M0 of the front interconnect structure 106. In some embodiments, the front source / drain contact 126 is electrically connected to the source / drain region 118 through a silicide layer formed on the source / drain region 118.

[0037] In some embodiments, a back source / drain contact 128 is formed between the source / drain region 118 and the back interconnect structure 108. Specifically, the back source / drain contact 128 extends through the substrate 102 and contacts a conductor 136 in the layer BMO of the back interconnect structure 108. A dielectric pad or isolation layer may be provided between the substrate 102 and the back source / drain contact 128. In some embodiments, the back source / drain contact 128 is electrically connected to the source / drain region 118 via a silicide layer formed on the source / drain region 118. In some embodiments, the back source / drain contact 128 may be connected to a power rail in the back interconnect structure 108 to provide power to the transistor 116.

[0038] although Figure 1B The image shows a multi-channel transistor 116, but device layer 104 can include any suitable semiconductor device, such as a planar transistor, a FinFET transistor, etc.

[0039] Figure 1E This is a partial enlarged view of the integrated circuit chip 100, showing details of the device layer 104 in an alternative embodiment. In some embodiments, such as Figure 1E As shown, the back source / drain contact 128 may be misaligned with the source / drain region 118. In other embodiments, the back source / drain contact 128 and the front source / drain contact 126 may have different widths, such as... Figure 1E As shown in the image.

[0040] Figure 1C This is a partial enlarged view of the integrated circuit chip 100, showing details of the TSV conductor 112 and the sealing structure 114 surrounding the TSV conductor 112. Figure 1DThis is a partial enlarged view of the integrated circuit chip 100, showing details of a portion of the sealing structure 114 embedded in the substrate 102.

[0041] like Figure 1C As shown, the TSV conductor 112 passes through the substrate 102 and at least a portion of the back interconnect structure 108 and the front interconnect structure 106. The TSV conductor 112 can be formed by etching the dielectric layer 134, the substrate 102, and the dielectric layer 130 to form the TSV opening, and then filling the TSV opening with a conductive material. To protect the components in the back interconnect structure 108, the device layer 104, and the front interconnect structure 106 from processing chemicals, a sealing structure 114 can be formed around the TSV opening. The sealing structure 114 is formed during the fabrication of the device layer 104, the front interconnect structure 106, and the back interconnect structure 108.

[0042] TSV conductor 112 electrically connects the conductor in the top metal layer BMm of the back interconnect structure 108 to the conductor in the top layer Mn of the front interconnect structure 106. For example... Figure 1C As shown, the TSV conductor 112 contacts the top metal line 112T in layer BMm of the back interconnect structure 108. The TSV conductor 112 contacts the landing conductor 112L in layer Mn of the front interconnect structure 106. The top metal line 112T and the landing conductor 112L can also be connected to the power supply or power rail of another integrated circuit chip.

[0043] In some embodiments, the TSV conductor 112 has a height H 112 The height H of TSV conductor 112 112 The diameter is in the range of approximately 0.5 μm to approximately 10 μm. In some embodiments, the TSV conductor 112 has a diameter CD. 112 The through-hole. In some embodiments, the diameter CD of the TSV conductor 112 is... 112 The diameter CD of the TSV conductor 112 is in the range of approximately 0.1 μm to approximately 15 μm. In some embodiments, the diameter CD of the TSV conductor 112 is... 112 It can vary along the height. For example, the diameter CD of the TSV conductor 112 near the top metal wire 112T. 112 The diameter CD of the TSV wire 112 near the landing conductor 112L is larger than that of the landing conductor 112L. 112 .

[0044] In some embodiments, the integrated circuit chip 100 may include TSV conductors of different sizes. For example, the integrated circuit chip 100 may include a small-sized TSV conductor 112 having a diameter CD. 112Within the range of approximately 0.1 μm to approximately 2 μm. The integrated circuit chip 100 may include a medium-sized TSV conductor 112 having a diameter CD. 112 Within the range of approximately 2 μm to approximately 5 μm. The integrated circuit chip 100 may include a large TSV conductor 112 having a diameter CD. 112 It is in the range of approximately 5 μm to approximately 15 μm.

[0045] Different sizes of TSV conductor 112 can be selected based on the expected function, the available area for the TSV conductor in the circuit layout, or a combination of other factors. For example, a large TSV conductor 112 can be selected to power the IC chip, while medium and small TSV conductors 112 can be used to transmit signals between IC chips.

[0046] like Figure 1C As shown, in the layers of the front interconnect structure 106, the sealing structure 114 includes a conductor 132' embedded in the dielectric layer 130 of the front interconnect structure 106. The conductor 132' may include wires and vias stacked in layers. The conductor 132' is formed layer by layer with the conductor 132 in the front interconnect structure 106. In some embodiments, the conductor 132' in each layer may include a continuous wire surrounding the TSV conductor 112 and a via connecting to the conductor 132' in the adjacent layer.

[0047] In the layers of the back interconnect structure 108, the sealing structure 114 includes a conductor 136' embedded in the dielectric layer 134 of the back interconnect structure 108. The conductor 136' may include wires and vias stacked in layers. The conductor 136' is formed layer by layer with the conductor 136 in the back interconnect structure 108. In some embodiments, the conductor 136' in each layer may include a continuous wire surrounding the TSV conductor 112 and a via connecting to the conductor 136' in the adjacent layer.

[0048] In some embodiments, conductors 136' and 132' are connected by a through-hole structure 142 formed through the substrate 102. Figure 1DA via structure 142 according to some embodiments of the present invention is schematically illustrated. The via structure 142 may include a conductive via 126', a semiconductor via 118', and a conductive via 128'. The semiconductor via 118' is similar to the source / drain region 118 and may be formed using the same material and at the same time as the source / drain region 118. In some embodiments, the semiconductor via 118' may include an epitaxially formed semiconductor material. In some embodiments, the semiconductor via 118' may include a doped semiconductor material. The conductive via 126' connects the semiconductor via 118' and a conductor 132' in the front interconnect structure 106. The conductive via 126' may be formed simultaneously with and using the same material as the front source / drain contacts 126 in the device layer 104. The conductive via 128' connects the semiconductor via 118' and a conductor 136' in the back interconnect structure 108. The conductor via 128' can be formed simultaneously with the back source / drain contacts 128 in the device layer 104 and using the same material.

[0049] In some embodiments, the sealing structure 114 is electrically floated, meaning that the sealing structure 114 is electrically isolated from other conductive structures in the integrated circuit chip 100, such as the TSV conductor 112, the conductor 132 in the front interconnect structure 106, the conductor 136 in the back interconnect structure 108, the source / drain contacts 126, 128, and the gate contact 124. In some embodiments, such as Figure 1C As shown, conductor 132' is isolated from landing conductor 112L by dielectric layer 130. Conductor 136' is isolated from top metal line 112T by dielectric layer 134.

[0050] Figure 1F This is a partially enlarged view of the integrated circuit chip 100, showing details of a portion of the sealing structure 114 embedded in the substrate 102 in an alternative embodiment. Figure 1F As shown, the bottom conductor via 128' may be misaligned with the semiconductor via 118' and partially cover the sidewall of the semiconductor via 118'.

[0051] Figure 2 This is a flowchart of a method 200 for manufacturing an integrated circuit chip according to an embodiment of the present invention. Figures 3A-3I The various stages of manufacturing an integrated circuit chip 100 using method 200 are illustrated schematically.

[0052] In operation 202, a device layer and a sealing via for the TSV conductor are formed on the front side of the substrate. Figure 3A The integrated circuit chip 100 after operation 202 is schematically shown. For example... Figure 3AAs shown, device layer 104 is formed on the front side 102f of substrate 102. Semiconductor vias 118' and conductor vias 126' are also formed during the fabrication of device layer 104. For example, semiconductor vias 118' can be fabricated during the formation of the source / drain regions of transistors in device layer 104. Conductor vias 126' can be formed during the fabrication of front-side source / drain contacts. Conductor vias 126' are stacked over semiconductor vias 118'. In some embodiments, conductor vias 126' are electrically connected to semiconductor vias 118'. In some embodiments, a silicide layer can be formed between semiconductor vias 118' and conductor vias 126'. Semiconductor vias 118' and conductor vias 126' are formed around TSV region 111, where TSV conductors 112 will be formed.

[0053] In operation 204, a front interconnect structure and a front sealing structure are formed. Figure 3B The integrated circuit chip 100 after operation 204 is schematically shown. For example... Figure 3B As shown, a front interconnect structure 106 is formed over the front side 102f of the substrate 102. Conductors 132 in the front interconnect structure 106 are formed layer by layer over the device layer 104 to provide electrical connections to the device layer 104.

[0054] In some embodiments, the conductor 132' for the sealing structure 114 is formed layer by layer with the front interconnect structure 106. The conductor 132' includes wires and vias stacked above the conductor via 126' and defines a TSV region 111 within the front interconnect structure 106. The conductor via 126' forms a closed volume within the front interconnect structure 106 below the top layer Mn forming the landing conductor 112L. The conductor via 126' is isolated from the top layer Mn such that the conductor via 126', i.e., the sealing structure 114, is electrically isolated from the TSV conductor to be formed.

[0055] In the topmost layer Mn of the front interconnect structure 106, a landing conductor 112L is formed in the TSV region 111. The landing conductor 112L is configured to connect to the TSV conductor to be formed. The landing conductor 112L may be a plate covering the TSV region 111.

[0056] In some embodiments, an FTV conductor 132” is formed in the front interconnect structure 106. The FTV conductor 132” may include wires and vias in the various layers of the front interconnect structure 106. The FTV conductor 132” forms an electrical path to connect the FTVs formed through the substrate 102 in the FTV region 109. However, it should be noted that the FTV conductor 132” may not be limited to the FTV region 109 in the front interconnect structure 106. For example, the FTV conductor 132” in the MO layer is disposed in the FTV region 109 such that subsequently formed FTVs contact the FTV conductor 132” in the MO layer. However, depending on the circuit design, the FTV conductor 132” in the upper layer of the front interconnect structure 106 may be disposed outside the FTV region 109.

[0057] In operation 206, such as Figure 3C As shown, the carrier wafer 101 is connected to the integrated circuit chip 100, and then the integrated circuit chip 100 and the carrier wafer 101 are flipped, as... Figure 3D As shown in [the document]. Then, as [the document states]. Figure 3E As shown, substrate 102 is ground from the back side down for back side processing.

[0058] In operation 208, such as Figure 3F As shown, contact components, such as back source / drain contacts, conductor vias for sealing structures, and FTVs are formed on the back side of the substrate. Figure 3F The integrated circuit chip 100 after operation 208 is schematically shown. For example... Figure 3F As shown, the back source / drain contact 128, the FTV conductor 110, and the conductor via 128' are formed from the back side 102b in the substrate 102. The back source / drain contact 128 is disposed on the back side of the source / drain region 118 in the device layer 104. The FTV conductor 110 is formed through the substrate 102 to connect to the FTV conductor 132” in the front interconnect structure 106. A conductor via 128’ is disposed above a semiconductor via 118’ for sealing structure 114. In some embodiments, the back source / drain contacts 128, the FTV conductor 110, and the conductor via 128’ can be formed simultaneously by forming contact openings in the substrate 102 from the back side 102b and then filling the contact openings with a conductive material such as a metal. A planarization process can be implemented to expose the back source / drain contacts 128, the FTV conductor 110, and the conductor via 128’ on the back side 102b of the substrate 102.

[0059] In operation 210, a back-side interconnect structure and a back-side sealing structure are formed. Figure 3G The integrated circuit chip 100 after operation 210 is schematically shown. For example... Figure 3GAs shown, a backside interconnect structure 108 is formed over the backside surface 102b of the substrate 102. Conductors 136 in the backside interconnect structure 108 are formed layer by layer on the backside contacts in the device layer 104 to provide electrical connections to the device layer 104.

[0060] In some embodiments, the conductor 136' for the sealing structure 114 is formed layer by layer with the back interconnect structure 108. The conductor 136' includes wires and vias stacked above the conductor via 128' and defines a TSV region 111 within the back interconnect structure 108. The conductor via 128' forms a closed volume within the back interconnect structure 108.

[0061] In operation 210, the back interconnect structure 108 is formed only partially. In some embodiments, the back interconnect structure 108 is formed one layer below the top metal of the TSV conductor 112. For example, in operation 210, when the top metal plate of the TSV conductor 112 is located in the topmost layer BMm of the back interconnect structure 108, the back interconnect structure 108 is formed up to the BMm-1 layer.

[0062] In some embodiments, an FTV conductor 136” is formed in the back-side interconnect structure 108. The FTV conductor 136” may include wires and vias in various layers of the back-side interconnect structure 108. The FTV conductor 136” forms an electrical path to connect to the FTV conductor 110 in the substrate 102. The FTV conductor 136” in the BMO layer is disposed in the FTV region 109 such that the FTV conductor 110 contacts the FTV conductor 136” in the BMO layer. However, depending on the circuit design, the FTV conductor 136” in the upper layer of the back-side interconnect structure 108 may be disposed outside the FTV region 109.

[0063] In operation 212, a TSV conductor is formed. Figure 3H The integrated circuit chip 100 after operation 212 is schematically shown. For example... Figure 3H As shown, TSV conductor 112 is formed in TSV region 111. TSV conductor 112 is formed to pass through substrate 102 and partially pass through front interconnect structure 106 and back interconnect structure 108.

[0064] Following operation 212, dielectric layer 134 covers conductors 136, 136', and 136" so that TSV conductor 112 can extend over conductors 136, 136', and 136" to contact conductors in subsequent layers of the back interconnect structure 108. TSV conductor 112 can be formed by forming TSV openings in TSV region 111 through the back interconnect structure 108, substrate 102, and front interconnect structure 106 to expose landing conductor 112L in the front interconnect structure 106. Sealing structure 114 surrounds the TSV openings and prevents components outside TSV region 111 from being exposed to processing chemicals. The TSV openings are then filled with a conductive material such as a metal to form TSV conductor 112. A planarization process can be performed to remove excess conductive material and expose dielectric layer 134 and TSV conductor 112 for subsequent processing. Figure 3H As shown, the top surface of TSV conductor 112 extends over conductors 136, 136', and 136" .

[0065] In operation 214, a top metal layer is formed above the TSV conductor. Figure 3I The integrated circuit chip 100 after operation 214 is schematically shown. For example... Figure 3I As shown, a top metal layer BMn of a back-side interconnect structure 108 is formed above the TSV conductor 112. The top metal layer BMn includes wires and vias for connection to conductor 136 in the underlying layer. For example, the top metal layer BMn includes wires and vias connected to conductor 136 and FTV conductor 136" connected to device layer 104. Top metal wire 112T is formed in TSV region 111 and contacts TSV conductor 112. Conductor via 128' in sealing structure 114 is isolated from top metal layer BMn, such that conductor via 128', i.e. sealing structure 114, is electrically isolated from TSV conductor 112.

[0066] The integrated circuit chip 100 according to the present invention can be stacked with other integrated circuit chips in a 3DIC. The TSV conductor 112 of the integrated circuit chip 100 can be used to transmit power through integrated circuit chips 100 stacked above and below it. For example, the TSV conductor 112 of the integrated circuit chip 100 can be used to transmit power from a UBM formed on one side of the integrated circuit chip 100 to another integrated circuit chip stacked on the other side of the integrated circuit chip 100. In some embodiments, the FTV conductor 110 in the integrated circuit chip 100 can be used to transmit signals to other integrated circuit chips stacked above the integrated circuit chip 100. Therefore, power and signal transmission can be decoupled.

[0067] Figures 4A-4CA package structure 300 according to an embodiment of the present invention is schematically illustrated. The package structure 300 includes a first integrated circuit chip 100a and a second integrated circuit chip 100b. Both the first integrated circuit chip 100a and the second integrated circuit chip 100b have a structure similar to that of the integrated circuit chip 100 described above, having a front interconnect structure 106, a back interconnect structure 108, and a TSV conductor 112 formed through a substrate 102 and at least a portion of the front interconnect structure 106 and the back interconnect structure 108. The back interconnect structure 108 includes a back power rail configured to supply power to a device layer 104 formed in the substrate 102.

[0068] In the package structure 300, the first integrated circuit chip 100a and the second integrated circuit chip 100b are vertically joined through a front interconnect structure 106 facing each other. Figure 4A The package structure 300 is schematically shown before the first integrated circuit chip 100a and the second integrated circuit chip 100b are joined.

[0069] In some embodiments, a redistribution layer (RDL) 302 may be formed over the back interconnect structure 108 of the first integrated circuit chip 100a. The RDL 302 may be embedded in a passivation layer. The RDL 302 provides electrical connections to conductors in the top metal layer BMm. The first integrated circuit chip 100a is then connected to the carrier wafer 301 such that the front interconnect structure 106 faces upward.

[0070] In some embodiments, a bonding film 304 is formed over the front-side interconnect structure 106 of the first integrated circuit chip 100a and the second integrated circuit chip 100b. Bonding pad components 306 are formed in the bonding film 304. In some embodiments, the bonding film 304 can be formed using silicon oxide, silicon oxynitride, silicon nitride, or a low-k dielectric material having a k-value lower than about 3.0. Low-k dielectric materials may include carbon-containing low-k dielectric materials, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), etc. In some embodiments, the bonding film 304 can be formed using suitable manufacturing techniques, such as chemical vapor deposition (CVD), high-density plasma chemical vapor deposition (HDPCVD), or plasma-enhanced chemical vapor deposition (PECVD).

[0071] The bonding pad component 306 may be formed of copper or other suitable metal to facilitate subsequent bonding. In some embodiments, the bonding pad component 306 may be formed using suitable manufacturing techniques such as electroplating or deposition. In some embodiments, the bonding pad component 306 may be formed using a damascene process, such as a single damascene process or a double damascene process. The bonding pad component 306 may be connected to the conductor 132 in the front-side interconnect structure 106 via a via.

[0072] The bonding pad component 306 of the first integrated circuit chip 100a is configured to bond with the bonding pad component 306 of the second integrated circuit chip 100b. In some embodiments, the top surface of the bonding pad component 306 and the top surface of the bonding film 304 are substantially coplanar, thereby providing a suitable surface for subsequent bonding. For example, planarization steps such as chemical mechanical polishing (CMP) or mechanical abrasion can be achieved.

[0073] exist Figure 4B In this process, a first integrated circuit chip 100a and a second integrated circuit chip 100b are bonded together. In some embodiments, the first integrated circuit chip 100a and the second integrated circuit chip 100b are bonded using a hybrid bonding process. In the hybrid bonding, bonding pads 306 on the first integrated circuit chip 100a are bonded to bonding pads 306 on the second integrated circuit chip 100b via metal-to-metal direct bonding, while bonding films 304 on the first integrated circuit chip 100a are bonded to bonding films 304 on the second integrated circuit chip 100b via dielectric-to-dielectric bonding. In some embodiments, the metal-to-metal bonding at the hybrid bonding interface is copper-to-copper bonding. In some embodiments, dielectric-to-dielectric bonding at the hybrid bonding interface is achieved by generating Si-O-Si bonds.

[0074] After bonding, an RDL 308 can be formed over the back interconnect structure 108 of the second integrated circuit chip 100b. The RDL 308 provides electrical connections to conductors in the top metal layer BMm of the second integrated circuit chip 100b.

[0075] Then an external connector 310 is formed above RDL 308, such as... Figure 4B As shown in the diagram. External connector 310 can be a contact bump, such as a microbump or a controlled collapse chip connection (C4) bump. External connector 310 can include a material such as tin, or other suitable materials such as silver or copper. In some embodiments, external connector 310 can be used to provide power or signals to the first integrated circuit chip 100a and the second integrated circuit chip 100b. In some embodiments, one or more external connectors 310 are connected to a power source.

[0076] Figure 4C This is a schematic diagram of a packaging structure 300 having a carrier wafer 301 flipped to the top. Figure 4C A power path 312 according to an embodiment of the present invention is schematically shown. For example... Figure 4CAs shown, power supply to the first integrated circuit chip 100a can be achieved via power path 312, which begins at external connector 310, passes through RDL 308, TSV conductor 112 in the second integrated circuit chip 100b, metal-to-metal bonding between pad components 306, TSV conductor 112 in the first integrated circuit chip 100a, and ends at the back interconnect structure 108 of the first integrated circuit chip 100a. The back interconnect structure 108 of the first integrated circuit chip 100a includes power rails configured to supply power to the device layer 104 of the first integrated circuit chip 100a. Power path 312 has reduced RC due to the TSV conductor 112.

[0077] In some embodiments, signals between the first integrated circuit chip 100a and the second integrated circuit chip 100b can be transmitted via signal path 314. Signal path 314 extends between device layers 104 of the first integrated circuit chip 100a and the second integrated circuit chip 100b. For example... Figure 4C As shown, signal path 314 includes conductor 132 in the front interconnect structure 106 of the first integrated circuit chip 100a, metal-to-metal bonding between bonding pad components 306, and the front interconnect structure 106 of the second integrated circuit chip 100b.

[0078] The integrated circuit chip 100 according to the present invention can be packaged in various arrangements. Figures 5-13 Various packaging structures according to embodiments of the present invention are schematically illustrated. Figures 4A-4C and Figures 5-13 For clarity, the sealing structure around the TSV, such as sealing structure 114, has been omitted. Additionally, when a back power rail is present in an integrated circuit chip, the FTV is typically used for signal transmission. Figures 5-13 For clarity, the FTV is omitted in some integrated circuit chips with a rear power rail.

[0079] Figure 5 A package structure 300a according to an embodiment of the present invention is schematically shown. Package structure 300a is similar to package structure 300, except that in package structure 300a, the back interconnect structure 108 of the first integrated circuit chip 100a is bonded to the front interconnect structure 106 of the second integrated circuit chip 100b. In package structure 300a, power supply to the first integrated circuit chip 100a can originate from the external connector 310, pass through the RDL 308, the TSV conductor 112 in the second integrated circuit chip 100b, and the metal-to-metal bonding between the bonding pad components 306, to the back interconnect structure 108 of the second integrated circuit chip 100b.

[0080] Figure 6A package structure 300b according to an embodiment of the present invention is schematically shown. Package structure 300b is similar to package structure 300a, except that in package structure 300b, RDL 302 is disposed on the back interconnect structure 108 of the first integrated circuit chip 100a. In package structure 300b, power supply to the first integrated circuit chip 100a can originate from the external connector 310, pass through RDL 308, the TSV conductor 112 in the second integrated circuit chip 100b, the metal-to-metal bonding between the bonding pad components 306, and RDL 302, to the back interconnect structure 108 of the second integrated circuit chip 100b.

[0081] Figure 7 A package structure 300c according to an embodiment of the present invention is schematically illustrated. Package structure 300c is similar to package structure 300, except that in package structure 300c, the first integrated circuit chip 100a is replaced by an integrated circuit chip 400. Integrated circuit chip 400 includes a front interconnect structure 406 and a back interconnect structure 408. The back interconnect structure 408 includes power rails. However, integrated circuit chip 400 does not include a TSV between the front interconnect structure 406 and the back interconnect structure 408. Instead, an FTV 410 is formed between the front interconnect structure 406 and the back interconnect structure 408.

[0082] In package structure 300c, the front interconnect structure 106 of the second integrated circuit chip 100b is bonded to the front interconnect structure 406 of the integrated circuit chip 400. In package structure 300c, power supply to the integrated circuit chip 400 can start from external connector 310, through RDL 308, TSV conductor 112 in the second integrated circuit chip 100b, metal-to-metal bonding between bonding pad components 306, and FTV 410 in the integrated circuit chip 400, to the back interconnect structure 408 of the integrated circuit chip 400.

[0083] Figure 8 A package structure 300d according to an embodiment of the present invention is schematically shown. Package structure 300d is similar to package structure 300c, except that in package structure 300d, the front interconnect structure 106 of the second integrated circuit chip 100b is bonded to the back interconnect structure 408 of the integrated circuit chip 400. In package structure 300d, power supply to the integrated circuit chip 400 can originate from the external connector 310, pass through the RDL 308, the TSV conductor 112 in the second integrated circuit chip 100b, and the metal-to-metal bonding between the bonding pad components 306, to the back interconnect structure 408 of the integrated circuit chip 400.

[0084] Figure 9A package structure 300e according to an embodiment of the present invention is schematically shown. Package structure 300e is similar to package structure 300, except that in package structure 300e, the second integrated circuit chip 100b is replaced by integrated circuit chip 500. Integrated circuit chip 500 includes a front interconnect structure 506 and a TSV 512. However, integrated circuit chip 500 does not include a back interconnect structure or a back power rail. RDL 308 is formed above the front interconnect structure 506.

[0085] In package structure 300e, the front interconnect structure 106 of integrated circuit chip 100a is bonded to the front interconnect structure 506 of integrated circuit chip 500. In package structure 300e, power supply to the first integrated circuit chip 100a can start from external connector 310, through the TSV 512 of integrated circuit chip 500, RDL 308, metal-to-metal bonding between bonding pad components 306, TSV conductor 112 in the first integrated circuit chip 100a, to the back interconnect structure 108 of the first integrated circuit chip 100a.

[0086] Figure 10 A package structure 300f according to an embodiment of the present invention is schematically shown. Package structure 300f is similar to package structure 300e, except that the back interconnect structure 108 of the first integrated circuit chip 100a is bonded to the front interconnect structure 506 of the integrated circuit chip 500. In package structure 300f, power supply to the first integrated circuit chip 100a can originate from the external connector 310, through the TSV 512, RDL 308, and metal-to-metal bonding between the bonding pad components 306 and RDL 302 of the integrated circuit chip 500, to the back interconnect structure 108 of the first integrated circuit chip 100a.

[0087] Figure 11 A package structure 300g according to an embodiment of the present invention is schematically shown. Package structure 300g is similar to package structure 300e, except that a first integrated circuit chip 100a is bonded to the back side of integrated circuit chip 500. In package structure 300g, the first integrated circuit chip 100a and integrated circuit chip 500 are bonded by a hybrid bonding, wherein the hybrid bonding has a metal-to-metal bonding between the bonding pad component 306 on the first integrated circuit chip 100a and the TSV 512 of the integrated circuit chip 500.

[0088] In the package structure 300g, power supply to the first integrated circuit chip 100a can start from the external connector 310, through RDL 308, TSV 512 of integrated circuit chip 500, metal-to-metal bonding between bonding pad component 306 and TSV 512, TSV conductor 112 of the first integrated circuit chip 100a, to the back interconnect structure 108 of the first integrated circuit chip 100a.

[0089] Figure 12 A package structure 300h according to an embodiment of the present invention is schematically shown. Package structure 300h is similar to package structure 300g, except that the back interconnect structure 108 of the first integrated circuit chip 100a is bonded to the back side of the integrated circuit chip 500. In package structure 300h, power supply to the first integrated circuit chip 100a can originate from external connector 310, through RDL 308, TSV 512 of integrated circuit chip 500, metal-to-metal bonding between bonding pad component 306 and TSV 512, and RDL 302, to the back interconnect structure 108 of the first integrated circuit chip 100a.

[0090] Figure 13 A package structure 300i according to an embodiment of the present invention is schematically illustrated. Package structure 300i is similar to package structure 300, except that package structure 300i includes a first integrated circuit chip 100a' and a second integrated circuit chip 100b' having short TSV connectors 112' and / or a group of TSV conductors 112. The TSV connectors 112' extend between the top metal layer BMn of the back interconnect structure 108 and the middle layer Mx of the front interconnect structure 106. The short TSV connectors 112' provide flexibility in circuit design. Furthermore, the conductors 112 and the short TSV connectors 112' can form a group instead of a single TSV connector. Grouping TSV connectors can reduce the process load caused by the large CD of the TSV connectors relative to the conductors in the interconnect structure. It should be noted that the short TSV connectors 112' and / or the group of TSV connectors 112 can be combined with any of the package structures discussed above.

[0091] The various embodiments or examples described herein offer numerous advantages over the prior art. The integrated circuit chip according to the invention includes a TSV connector for delivering power to stacked circuit chips using reduced RC delay. Additionally, the integrated circuit chip includes both a TSV connector and an FTV to decouple power and signal delivery, thereby improving device performance.

[0092] Some embodiments of the present invention provide an integrated circuit chip, comprising: a substrate having a first side and a second side opposite to the first side; a device layer disposed on the first side of the substrate; a first interconnect structure disposed over the first side of the substrate, wherein the first interconnect structure includes a plurality of first conductive layers; a second interconnect structure disposed over the second side of the substrate, wherein the second interconnect structure includes a plurality of second conductive layers and includes a power rail configured to transmit power to the device layer; and a through-silicon via (TSV) extending from one of the first conductive layers in the first interconnect structure through the substrate to one of the second conductive layers in the second interconnect structure. In some embodiments, the integrated circuit chip further comprises: a feed through-hole disposed in the substrate, wherein the feed through-hole connects the first interconnect structure and the second interconnect structure. In some embodiments, the height of the feed through-hole is equal to the thickness of the substrate. In some embodiments, the height of the feed through-hole is substantially equal to the thickness of the substrate. In some embodiments, the height of the through-silicon via is greater than the thickness of the substrate. In some embodiments, the integrated circuit chip further includes: a first conductive plate disposed in one of the first conductive layers; and a second conductive plate disposed in one of the second conductive layers, wherein a first end of the through-silicon via (TSV) contacts the first conductive plate, and a second end of the TSV contacts the second conductive plate. In some embodiments, the second conductive plate is disposed in the top layer of the second conductive layer. In some embodiments, the first conductive plate is disposed in the top layer of the first conductive layer. In some embodiments, the integrated circuit chip further includes a sealing structure formed in the first interconnect structure, the substrate, and the second interconnect structure, wherein the sealing structure surrounds the TSV. In some embodiments, the sealing structure includes a via structure in the substrate, the via structure including a first conductive via formed in a first surface of the substrate, a second conductive via formed in a second surface of the substrate, and a semiconductor via disposed between the first conductive via and the second conductive via. In some embodiments, the sealing structure is electrically isolated from the first conductive plate and the second conductive plate. In some embodiments, the integrated circuit chip further includes a group of TSVs.

[0093] Some embodiments of the present invention provide a packaging structure including a first integrated circuit chip. The first integrated circuit chip includes: a first substrate; a first device layer disposed on the front side of the first substrate; a first front interconnect structure disposed above the front side of the first substrate; a first back interconnect structure disposed above the back side of the first substrate, wherein the first back interconnect structure includes a first power rail configured to transmit power to the first device layer; and a first through-silicon via (TSV) extending from the first front interconnect structure through the first substrate and to the first back interconnect structure. The packaging structure also includes a second integrated circuit chip stacked with the first integrated circuit chip, wherein a hybrid bonding surface is located between the first integrated circuit chip and the second integrated circuit chip, the hybrid bonding surface including a metal-to-metal bond, and the first TSV is electrically connected to the metal-to-metal bond. In some embodiments, the second integrated circuit chip includes: a second substrate; a second device layer disposed on the front side of the second substrate; and a second front interconnect structure disposed above the front side of the second substrate. In some embodiments, the second integrated circuit chip further includes a second through-silicon via extending from the second front interconnect structure through the second substrate, wherein the second through-silicon via is electrically connected to the first through-silicon via. In some embodiments, a hybrid bonding surface is located between the first front-side interconnect structure and the second front-side interconnect structure. In some embodiments, the second integrated circuit chip further includes a second back-side interconnect structure disposed above the back side of the second substrate, wherein the second through-silicon via extends vertically from the second front-side interconnect structure, through the second substrate, and to the second back-side interconnect structure. In some embodiments, a hybrid bonding surface is located between the first back-side interconnect structure and the second front-side interconnect structure.

[0094] Some embodiments of the present invention provide a method for manufacturing an integrated circuit chip, comprising: forming a device layer on a first surface of a substrate; forming a first interconnect structure over the device layer, wherein the first interconnect structure includes a first sealing structure surrounding a through-substrate via (TSV) region; forming a second interconnect structure on a second surface of the substrate, wherein the second interconnect structure includes a power rail configured to supply power to the device layer and a second sealing structure surrounding the TSV region; and forming a TSV extending through the second interconnect structure and the substrate and into the first interconnect structure. In some embodiments, the method further comprises: forming a feed through-via through the substrate prior to forming the second interconnect structure, wherein the feed through-via is electrically connected to the first interconnect structure. In some embodiments, forming the device layer comprises: forming a semiconductor via in the substrate and forming a conductive via on the semiconductor via, wherein the first sealing structure is subsequently formed over the conductive via.

[0095] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as this disclosure. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. An integrated circuit chip, comprising: A substrate having a first surface and a second surface opposite to the first surface; A device layer is disposed on the first surface of the substrate; A first interconnect structure is disposed above the first surface of the substrate, wherein the first interconnect structure includes a plurality of first conductive layers; A second interconnect structure is disposed above the second surface of the substrate, wherein the second interconnect structure includes a plurality of second conductive layers, and the second interconnect structure includes power rails configured to transmit power to the device layer; and A through-silicon via extends from a first conductive layer in the first interconnect structure through the substrate to a second conductive layer in the second interconnect structure.

2. The integrated circuit chip according to claim 1, further comprising: A feed through-hole is disposed in the substrate, wherein the feed through-hole is connected between the first interconnect structure and the second interconnect structure.

3. The integrated circuit chip according to claim 2, wherein, The height of the feed through-hole is equal to the thickness of the substrate.

4. The integrated circuit chip according to claim 1, wherein, The height of the through-silicon via is greater than the thickness of the substrate.

5. The integrated circuit chip according to claim 1, further comprising: A first conductive plate is disposed in one of the first conductive layers; and A second conductive plate is disposed in one of the second conductive layers, wherein the first end of the through-silicon via is in contact with the first conductive plate, and the second end of the through-silicon via is in contact with the second conductive plate.

6. The integrated circuit chip according to claim 5, wherein, The second conductive plate is disposed on the top layer of the second conductive layer.

7. The integrated circuit chip according to claim 5, wherein, The first conductive plate is disposed on the top layer of the first conductive layer.

8. The integrated circuit chip according to claim 5, further comprising a sealing structure formed in the first interconnect structure, the substrate, and the second interconnect structure, wherein, The sealing structure surrounds the through-silicon via.

9. A packaging structure, comprising: The first integrated circuit chip includes: First substrate; The first device layer is disposed on the front side of the first substrate; A first front-side interconnect structure is disposed above the front side of the first substrate; A first back-side interconnect structure is disposed above the back side of the first substrate, wherein the first back-side interconnect structure includes a first power rail configured to transmit power to the first device layer; and A first through-silicon via (TSV) extends from the first front-side interconnect structure through the first substrate and to the first back-side interconnect structure; and A second integrated circuit chip is stacked with the first integrated circuit chip, wherein a hybrid bonding surface is located between the first integrated circuit chip and the second integrated circuit chip, the hybrid bonding surface includes a metal-to-metal bond, and the first through-silicon via is electrically connected to the metal-to-metal bond.

10. A method for manufacturing an integrated circuit chip, comprising: A device layer is formed on the first surface of the substrate; A first interconnect structure is formed above the device layer, wherein the first interconnect structure includes a first sealing structure surrounding a through-substrate via region; A second interconnect structure is formed on a second surface of the substrate, wherein the second interconnect structure includes a power rail configured to supply power to the device layer and a second sealing structure surrounding the through-substrate via region; and A through-substrate via is formed that extends through the second interconnect structure and the substrate, and enters the first interconnect structure.

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