High-density chip packaging structure and preparation method thereof

Abstract

The invention discloses a high-density chip packaging structure and a preparation method thereof, and the chip packaging structure comprises a rigid interconnection layer which is provided with a conductive through hole; the first redistribution stacking layer is arranged on the first surface of the rigid interconnection layer; the second redistribution stacking layer is arranged on the second surface of the rigid interconnection layer; the at least one chip is mounted on one side, far away from the rigid interconnection layer, of the second rewiring stacking layer, and is electrically connected with the first rewiring stacking layer through the second rewiring stacking layer and the conductive through hole; the plastic package body is used for packaging the chip; and the signal export structure is electrically connected with the chip through the first redistribution stacking layer, the conductive through hole and the second redistribution stacking layer. By adopting the double-sided rewiring stack layer structure with the rigid interconnection layer as the core and combining the alternate preparation process, high interconnection density, ultra-thin thickness, low warping and lower comprehensive cost are simultaneously realized in high-density fan-out packaging, and the technical bottleneck of traditional organic substrate packaging is broken through.

Description

Technical Field

[0001] This invention relates to the field of semiconductor chip packaging technology, and in particular to high-density chip packaging structures and their fabrication methods. Background Technology

[0002] With the rapid development of AI computing chips, HBM storage modules, and 5G RF devices, the demand for "high-density interconnection and thinness" in packaging technology is becoming increasingly urgent. Fan-out packaging, due to its characteristics of not requiring a traditional substrate and being able to directly interconnect the chip with an external PCB, has become one of the mainstream technologies for high-end packaging. Currently, the mainstream fan-out packaging solutions in the industry still use organic substrates (such as ABF substrates and BT resin substrates) as the core interconnect carrier. The typical structure is a three-layer architecture of "chip-organic substrate interposer-PCB", and the fan-out and transmission of chip signals are achieved through the multilayer wiring process of the organic substrate.

[0003] However, existing organic substrate fan-out packaging has significant technical bottlenecks: in terms of integration density, limited by the photolithographic resolution and lamination process precision of organic materials, its I / O density is generally lower than 200 I / O / mm². 2 This makes it difficult to meet the demands of Chiplet heterogeneous integration (requiring tens of thousands of I / Os) and high-bandwidth HBM for high-density interconnects. Regarding thinning, the single-layer thickness of organic substrates is relatively large, resulting in a high total thickness after multi-layer stacking, which cannot meet the space constraints of "ultra-thin" consumer electronics and "high integration" server chips. Furthermore, the significant difference in thermal expansion coefficients between organic substrates and silicon chips and metal wiring leads to unidirectional stress accumulation during multi-layer RDL fabrication, with edge warpage heights of 12-inch wafers often exceeding 30μm. This not only affects subsequent bonding yield but also increases signal transmission loss, making it difficult to increase the number of RDL stacked layers and further limiting interconnect density improvements.

[0004] Furthermore, the supply chain and cost issues of organic substrates have become key constraints on the industry's development: core materials have long been monopolized by a few companies; multilayer wiring processes are complex and have long production cycles; and the yield of multilayer products is low. From a cost structure perspective, the cost of organic substrate materials accounts for a high proportion of the total packaging cost, and the cost increase is more significant with the number of layers. Technological monopolies also lead to supply chain risks for the industry, making it difficult to achieve independent control over packaging costs. In summary, existing fan-out packaging based on organic substrates has highlighted its pain points in terms of integration density, thinning, warpage control, and cost supply chain, failing to meet the technological requirements of high-end chips. A new fan-out packaging technology is urgently needed to overcome these bottlenecks. Summary of the Invention

[0005] To address the aforementioned technical problems, the present invention aims to provide a high-density chip packaging structure and its fabrication method. By employing a double-sided redistribution stacked layer structure with a rigid interconnect layer at its core, and combining it with alternating fabrication processes, the present invention simultaneously achieves high interconnect density, ultra-thin thickness, low warpage, and lower overall cost in a high-density fan-out package, breaking through the technical bottlenecks of traditional organic substrate packaging.

[0006] To achieve the above-mentioned technical objectives and effects, the present invention is implemented through the following technical solution: This invention provides a high-density chip packaging structure, comprising: A rigid interconnect layer having conductive vias penetrating both the upper and lower surfaces; A first wiring stack layer is disposed on the first surface of the rigid interconnect layer; A second wiring stack layer is disposed on the second surface of the rigid interconnect layer opposite to the first surface; At least one chip is mounted on the side of the second rewiring stack away from the rigid interconnect layer and is electrically connected to the first rewiring stack through the second rewiring stack and the conductive via. A molding compound encapsulates at least one chip; and Multiple signal output structures are disposed on the side of the first rewiring stack layer away from the rigid interconnect layer, and are electrically connected to the chip through the first rewiring stack layer, the conductive via, and the second rewiring stack layer; The number of wiring layers in both the first and second wiring stack layers is greater than or equal to 4.

[0007] Preferably, the rigid interconnect layer is made of silicon, glass, or silicon carbide.

[0008] Furthermore, the conductive via is filled with conductive pillars.

[0009] Furthermore, the first and / or second wiring stack layers comprise alternating layers of organic passivation layers and metal wiring layers.

[0010] Furthermore, the line width / spacing of the metal wiring layer is less than or equal to 1.5μm / 1.5μm.

[0011] Furthermore, the total number of layers in the first routing stack is equal to the total number of layers in the second routing stack.

[0012] Furthermore, the first and second wiring stack layers are mirror-symmetric or nearly mirror-symmetric with respect to the rigid interconnect layer in terms of material type, number of wiring layers, and thickness distribution.

[0013] Furthermore, the chip is flip-chip mounted on the outermost pad of the second multi-layer wiring stack via bumps, and an underfill layer is filled between the chip and the pad.

[0014] Another aspect of the present invention provides a method for fabricating a high-density chip packaging structure, comprising the following steps: Provides a rigid interconnect layer with conductive vias; A first rewiring stack layer is constructed on the first surface of the rigid interconnect layer; A second rewiring stack layer is constructed on the second surface of the rigid interconnect layer; The construction process of the first and second wiring stack layers is carried out alternately, and a temporary carrier board is used for flipping support during the construction process. The chip is mounted on the completed second wiring stack layer and then encapsulated. A signal sourcing structure is formed on the completed first wiring stack layer.

[0015] Furthermore, the steps of constructing the first and second wiring stack layers include alternately forming an organic passivation layer and a metal wiring layer.

[0016] Furthermore, the alternating construction process includes: firstly, constructing a first portion of a first rewiring stack layer on the first surface of the rigid interconnect layer; after flipping and supporting it with a first temporary carrier, constructing a first portion of a second rewiring stack layer on the second surface of the rigid interconnect layer; after flipping and supporting it with a second temporary carrier, continuing construction on the first portion of the first rewiring stack layer to complete the first rewiring stack layer; after flipping it again, supporting it with a third temporary carrier, continuing construction on the first portion of the second rewiring stack layer to complete the second rewiring stack layer.

[0017] The beneficial effects of this invention are as follows: (1) Achieve ultra-high integration density, miniaturized and thinner packaging This invention directly fabricates ultra-high density redistribution layers using semiconductor-grade photolithography and electroplating processes, achieving linewidth / spacing (L / S) exceeding 1.5μm / 1.5μm and I / O density exceeding 1000 I / O / mm. 2This achieves more than five times the throughput of traditional organic substrate solutions, meeting the demand for tens of thousands of I / O interconnects in Chiplet heterogeneous integration and HBM high-bandwidth storage. Furthermore, this invention directly replaces traditional organic substrates with double-sided ultra-high-density RDL layers. The RDL layers (redistribution layers) employ thin dielectric and metal structures, ensuring that even with more than 20 redistribution layers stacked on both sides, the total package thickness can be controlled to around 200 micrometers, far lower than the nearly 1-millimeter thickness of traditional 6-layer organic substrates. This significantly promotes the evolution of packaging structures towards miniaturization and thinning, adapting to scenarios with stringent space constraints, such as AI chips and HBM.

[0018] (2) Low warp design supports ultra-high layer number RDL stacking This invention employs a "rigid interconnect layer double-sided batch fabrication" process: A rigid interconnect layer is used as the core, and RDL layers are fabricated sequentially in batches on both sides, with the wiring structure and dielectric / metal material ratio of the RDL layers on both sides being essentially symmetrical. Through this symmetrical structural design, the tension formed by the RDL layers on both sides cancels each other out, eliminating stress-induced warpage at its source. Measured edge warpage height on a 12-inch wafer is ≤5μm. Based on this design, double-sided ≥20-layer RDL stacking can be achieved, further improving I / O density and chip integration while reducing warpage, making it particularly suitable for high-end chiplet heterogeneous integration and multi-chip stacking scenarios.

[0019] (3) High structural flexibility and the ability to achieve cost optimization and break through monopoly. The RDL technology used in this invention has significant cost and supply chain advantages: First, the cost of RDL decreases with the number of layers. When the number of layers is greater than 6, the cost per unit area is lower than that of organic substrates. For example, the cost per unit area of ​​a 6-layer RDL is 20-30% lower than that of an ABF substrate with the same number of layers. Second, RDL design and fabrication are highly flexible. Packaging companies can independently complete the layout design and manufacturing, and adjust the wiring scheme in real time according to customer needs without relying on external substrate suppliers. Third, the localization rate of the RDL industry chain is higher—the localization rate of related materials, equipment and processes reaches more than 60%, which can break the import monopoly and further reduce supply chain risks and manufacturing costs. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the structure obtained in step S1 of the preparation method of the present invention; Figure 2 This is a schematic diagram of the structure obtained in step S2 of the preparation method of the present invention; Figure 3 This is a schematic diagram of the structure obtained in step S3 of the preparation method of the present invention; Figure 4 This is a schematic diagram of the structure obtained in step S4 of the preparation method of the present invention; Figure 5This is a schematic diagram of the structure obtained in step S5 of the preparation method of the present invention; Figure 6 This is a schematic diagram of the structure obtained in step S6 of the preparation method of the present invention; Figure 7 This is a schematic diagram of the structure obtained in step S7 of the preparation method of the present invention; Figure 8 This is a schematic diagram of the structure obtained in step S8 of the preparation method of the present invention; Figure 9 This is a schematic diagram of the structure obtained in step S9 of the preparation method of the present invention; Figure 10 This is a schematic diagram of the structure obtained in step S10 of the preparation method of the present invention; Figure 11 This is a schematic diagram of the structure obtained in step S11 of the preparation method of the present invention; Figure 12 This is a schematic diagram of the structure obtained in step S12 of the preparation method of the present invention; In the figure, 1: Rigid interconnect layer; 101: Conductive pillar; 102: Insulating layer; 2: First dielectric layer; 3: First redistribution stack layer; 4: Second redistribution stack layer; 5: Organic passivation layer; 6: Metallic wiring layer; 7: Second dielectric layer; 8: First temporary carrier; 9: First release adhesive; 10: First temporary bonding adhesive; 11: Second temporary carrier; 12: Second release adhesive; 13: Second temporary bonding adhesive; 14: Third temporary carrier; 15: Third release adhesive; 16: Third temporary bonding adhesive; 17: Pad; 18: Chip; 19: Underfill layer; 20: Molding body; 21: Signal extraction structure. Detailed Implementation

[0021] The technical solutions of the present invention will be clearly and completely described below with reference to specific embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] like Figure 12 A preferred embodiment of a high-density chip packaging structure is shown, which includes a rigid interconnect layer 1, a first rewiring stack layer 3, a second rewiring stack layer 4, a chip 18, a molding compound 20, and a signal output structure 21.

[0023] The rigid interconnect layer 1 has conductive vias penetrating both the upper and lower surfaces; an insulating layer 102 covers the sidewalls of the conductive vias, and conductive pillars 101 are filled within the conductive vias. The rigid interconnect layer 1 is preferably made of silicon wafers, glass wafers, SiC wafers, etc.; the conductive pillars 101 are preferably made of copper; and the insulating layer 102 is preferably made of silicon nitride or silicon oxide. A first dielectric layer 2 is respectively covered on the first and second surfaces of the rigid interconnect layer 1. This first dielectric layer 2 is preferably made of silicon nitride or silicon oxide and serves an insulating function.

[0024] The first rewiring stack layer 3 is disposed on the first surface of the rigid interconnect layer 1; the first rewiring stack layer 3 includes alternating layers of organic passivation layer 5 and metal wiring layer 6.

[0025] The second rewiring stack layer 4 is disposed on the second surface of the rigid interconnect layer 1 opposite to the first surface; the second rewiring stack layer 4 includes alternating layers of organic passivation layer 5 and metal wiring layer 6.

[0026] In this embodiment, the first wiring stack layer 3 and the second wiring stack layer 4 each have 4 or more wiring layers. Preferably, in this preferred embodiment, the first wiring stack layer 3 and the second wiring stack layer 4 each have 8 wiring layers. The number of organic passivation layers 5 corresponds to the number of metal wiring layers 6.

[0027] The first wiring stack layer 3 and the second wiring stack layer 4 are mirror-symmetric or nearly mirror-symmetric with respect to the rigid interconnect layer 1 in terms of material type, number of wiring layers and thickness distribution.

[0028] The metal wiring layer 6 is preferably made of copper, and the line width / spacing of the metal wiring layer 6 is less than or equal to 1.5 μm / 1.5 μm. The organic passivation layer 5 is made of PI film or solid dry film.

[0029] Chip 18 is mounted on the side of the second rewiring stack 4 away from the rigid interconnect layer 1, and is electrically connected to the first rewiring stack 3 through the second rewiring stack 4 and the conductive via; the number of chips 18 is one or more. In this preferred embodiment, chip 18 is a high I / O density chip, and the number mounted is two. More specifically, chip 18 is flip-chip mounted on the outermost pad 17 of the second rewiring stack 4 via bumps; the bumps of chip 18 are made of materials such as copper, nickel, tin, and silver. An underfill layer 19 is also filled between chip 18 and pad 17. The underfill of chip 18 can reduce the warpage of the package after molding and protect the bottom of chip 18 and the bumps.

[0030] The molding compound 20 encapsulates the chip 18, which can protect the chip 18 and provide support in subsequent processes.

[0031] The signal outgoing structure 21 is disposed on the side of the first rewiring stack 3 away from the rigid interconnect layer 1, and is electrically connected to the chip 18 through the first rewiring stack 3, the conductive via, and the second rewiring stack 4. The signal outgoing structure 21 can be a solder ball or a solder bump; in this preferred embodiment, the signal outgoing structure 21 is preferably a solder ball.

[0032] like Figures 1 to 12 A preferred embodiment of the method for fabricating the high-density chip packaging structure shown includes the following steps: S1, such as Figure 1 As shown, a substrate with conductive vias is provided as a rigid interconnect layer 1; an insulating layer 102 covers the walls of the conductive vias. A first dielectric layer 2 is deposited on the first surface of the substrate; in this embodiment, the material of the first dielectric layer 2 is silicon oxide.

[0033] S2, such as Figure 2 As shown, a first portion of the first rewiring stack 3 is constructed on the first dielectric layer 2, including alternating layers of organic passivation layer 5 and metal wiring layer 6. In this preferred embodiment, the metal wiring layer 6 is electroplated Cu wiring, and the organic passivation layer 5 is formed by curing a liquid PI film. During the fabrication of the topmost wiring in the first portion of the first rewiring stack 3, the sputtered seed layer is not used for wiring but serves as a protective layer to protect the bottom wiring during the subsequent bonding / debonding process. It will then be used for wiring fabrication when the second portion of the first rewiring stack 3 is fabricated.

[0034] S3, such as Figure 3 As shown, a first release adhesive 9 is coated on the first temporary carrier 8, and a first temporary bonding adhesive 10 is coated on the first rewiring stack layer 3 of the first portion. The structure obtained in step S2 is flipped over, and the side of the first rewiring stack layer 3 away from the rigid interconnect layer 1 is bonded to the first temporary carrier 8 by a temporary bonding process. The first temporary carrier 8 is a glass carrier.

[0035] S4, such as Figure 4 As shown, a second dielectric layer 7 is deposited on the second surface of the rigid interconnect layer 1. In this embodiment, the material of the second dielectric layer 7 is silicon oxide.

[0036] S5, such as Figure 5As shown, a first portion of the second rewiring stack 4 is constructed on the second dielectric layer 7, comprising alternating layers of organic passivation layer 5 and metal wiring layer 6. In this preferred embodiment, the metal wiring layer 6 is electroplated Cu wiring, and the organic passivation layer 5 is formed by curing a liquid PI film. During the fabrication of the topmost wiring layer of the first portion of the second rewiring stack 4, the sputtered seed layer is not used for wiring but serves as a protective layer to protect the bottom wiring during the subsequent bonding / debonding process. It will then be used for wiring fabrication when the second portion of the second rewiring stack 4 is fabricated.

[0037] S6, such as Figure 6 As shown, a second release adhesive 12 is coated on the second temporary carrier 11, and a second temporary bonding adhesive 13 is coated on the second rewiring stack layer 4 in the first part. The structure obtained in step S5 is flipped over, and the side of the second rewiring stack layer 4 away from the rigid interconnect layer 1 is bonded to the second temporary carrier 11 by a temporary bonding process. The second temporary carrier 11 is a glass carrier.

[0038] S7, such as Figure 7 As shown, the first temporary carrier board 8 is debonded by the debonding process, and the first super-wiring stack layer 3 of the first part is cleaned and exposed. The first temporary bonding adhesive 10 is removed. According to step S2, the first super-wiring stack layer 3 of the second part is constructed. During the fabrication of the topmost line of the first super-wiring stack layer 3 of the second part, the sputtered seed layer is not used for the line, but is used as a protective layer to protect the bottom line layer in the subsequent bonding / debonding process. The line fabrication will continue when the signal output structure 21 is fabricated.

[0039] S8, such as Figure 8 As shown, a third release adhesive 15 is coated on the third temporary carrier 14, and a third temporary bonding adhesive 16 is coated on the first rewiring stack layer 3 in the second part. The structure obtained in step S7 is flipped over, and the side of the first rewiring stack layer 3 away from the rigid interconnect layer 1 is bonded to the third temporary carrier 14 by a temporary bonding process. The third temporary carrier 14 is a glass carrier.

[0040] S9, such as Figure 9 As shown, the second temporary carrier board 11 is debonded by the debonding process, and the second super-wiring stack layer 4 of the first part is cleaned and exposed. The second temporary bonding adhesive 13 is removed and the second super-wiring stack layer 4 of the second part is prepared. A window is opened on the outermost organic passivation layer 5, and a pad 17 is prepared at the corresponding window position. The material of the pad 17 is electroplated copper.

[0041] S10, such as Figure 10As shown, two chips 18 with bumps are mounted on the second wiring stack layer 4. The bumps of the chips 18 are connected to the pads 17, thereby electrically connecting the chips 18 to the metal wiring layer 6 in the second wiring stack layer 4 for signal transmission. In this embodiment, both chips 18 are high I / O density chips.

[0042] S11, such as Figure 11 As shown, the bottom of the chip 18 is filled with an underfill material to form an underfill layer 19, which can further reduce package warpage; then a molding process is performed to form a molding body 20, which encapsulates the chip 18, providing protection and support in the subsequent processes.

[0043] S12, such as Figure 12 As shown, the third temporary carrier board 14 is debonded through processes such as circumferential cutting and debonding, and the exposed first rewiring stack layer 3 is cleaned to remove the bonding adhesive from its surface. During the debonding process, the structure is flipped upside down, and the molding compound 20 is used as a supporting carrier board to complete the outermost circuit structure. A signal output structure 21 is then fabricated on the outermost circuit structure for electrical signal transmission. In this embodiment, the signal output structure 21 is a solder ball.

[0044] This invention achieves high interconnect density, ultra-thin thickness, low warpage, and lower overall cost in high-density fan-out packaging by employing a double-sided redistribution stacked layer structure with a rigid interconnect layer as the core, combined with alternating fabrication processes, thus breaking through the technical bottleneck of traditional organic substrate packaging.

[0045] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within the present invention.

[0046] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A high-density chip packaging structure, characterized in that, include: A rigid interconnect layer having conductive vias penetrating both the upper and lower surfaces; A first wiring stack layer is disposed on the first surface of the rigid interconnect layer; A second wiring stack layer is disposed on the second surface of the rigid interconnect layer opposite to the first surface; At least one chip is mounted on the side of the second rewiring stack away from the rigid interconnect layer and is electrically connected to the first rewiring stack through the second rewiring stack and the conductive via. A molding compound encapsulates at least one chip. as well as Multiple signal output structures are disposed on the side of the first rewiring stack layer away from the rigid interconnect layer, and are electrically connected to the chip through the first rewiring stack layer, the conductive via, and the second rewiring stack layer; The number of wiring layers in both the first and second wiring stack layers is greater than or equal to 4.

2. The high-density chip packaging structure according to claim 1, characterized in that, The rigid interconnect layer is made of silicon, glass, or silicon carbide.

3. The high-density chip packaging structure according to claim 1, characterized in that, The conductive through-hole is filled with conductive pillars.

4. The high-density chip packaging structure according to claim 1, characterized in that, The first and / or second wiring stack layer comprises alternating layers of organic passivation layers and metal wiring layers.

5. The high-density chip packaging structure according to claim 4, characterized in that, The line width / spacing of the metal wiring layer is less than or equal to 1.5μm / 1.5μm.

6. The high-density chip packaging structure according to claim 1, characterized in that, The total number of layers in the first rewiring stack is equal to the total number of layers in the second rewiring stack.

7. The high-density chip packaging structure according to claim 1, characterized in that, The chip is flip-chip mounted on the outermost pad of the second overlay stack layer via bumps, and an underfill layer is filled between the chip and the pad.

8. A method for fabricating a high-density chip packaging structure according to any one of claims 1-7, characterized in that, Includes the following steps: Provides a rigid interconnect layer with conductive vias; A first rewiring stack layer is constructed on the first surface of the rigid interconnect layer; A second rewiring stack layer is constructed on the second surface of the rigid interconnect layer; The construction process of the first and second wiring stack layers is carried out alternately, and a temporary carrier board is used for flipping support during the construction process. The chip is mounted on the completed second wiring stack layer and then encapsulated. A signal sourcing structure is formed on the completed first wiring stack layer.

9. The method for fabricating a high-density chip packaging structure according to claim 8, characterized in that, The steps of constructing the first and second wiring stack layers include alternately forming organic passivation layers and metal wiring layers.

10. The method for fabricating a high-density chip packaging structure according to claim 8, characterized in that, The alternating construction process includes: firstly, constructing a first portion of a first rewiring stack layer on the first surface of the rigid interconnect layer; after flipping and supporting it with a first temporary carrier, constructing a first portion of a second rewiring stack layer on the second surface of the rigid interconnect layer; after flipping and supporting it with a second temporary carrier, continuing construction on the first portion of the first rewiring stack layer to complete the first rewiring stack layer; after flipping it again, supporting it with a third temporary carrier, continuing construction on the first portion of the second rewiring stack layer to complete the second rewiring stack layer.

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