Semiconductor device and forming method thereof

Abstract

The present disclosure relates to methods, devices, systems, and techniques for gate line structures in semiconductor devices. An example semiconductor device includes a semiconductor structure including a stack of alternating conductive layers and isolation layers. The semiconductor device also includes a channel structure extending in a first direction through the stack. The channel structures include at least a first channel structure having a top end and a bottom end in a first direction. The first channel structure includes a channel plug at the top end. The semiconductor device also includes a gate line structure extending in a first direction through the stack. The gate line structure includes a top portion and a body portion arranged in a first direction. A top portion of the gate line structure is further away from a bottom end of the first channel structure than the channel plug in the first direction.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and methods of manufacturing the same. Background Technology

[0002] Semiconductor devices (e.g., memory devices) can have various structures to increase the density of memory cells and lines on a chip. For example, three-dimensional (3D) memory devices are attractive because they can increase array density by stacking more layers within a similar footprint. 3D memory devices typically include a memory array of memory cells and peripheral circuitry to facilitate the operation of the memory array. Summary of the Invention

[0003] This disclosure describes methods, apparatus, systems, and techniques related to gate line structures in semiconductor devices.

[0004] One aspect of this disclosure features a semiconductor device. The semiconductor device includes a semiconductor structure comprising a stack of conductive and insulating layers alternating with each other along a first direction. The semiconductor device also includes a channel structure extending through the stack along the first direction. The channel structure includes at least a first channel structure having a top end and a bottom end along the first direction. The first channel structure includes a channel plug at the top end. The semiconductor device also includes a gate line structure extending through the stack along the first direction. The gate line structure includes a top portion and a body portion arranged along the first direction. The top portion of the gate line structure is further away from the bottom end of the first channel structure along the first direction than the channel plug.

[0005] In some embodiments, the semiconductor structure includes an array region and a connection region adjacent to the array region in a second direction perpendicular to the first direction.

[0006] In some embodiments, the side surface of the top portion includes a curved surface and a flat surface. The flat surface is located between the curved surface and the body portion along the first direction. The side surface of the body portion includes a series of curved surfaces arranged along a second direction perpendicular to the first direction.

[0007] In some embodiments, the side surface of the main body portion includes a wave pattern that repeats along the second direction.

[0008] In some embodiments, the side surface of the top portion has a uniform profile along the second direction, and the flat surface of the side surface of the top portion is a smooth surface without lumps or dents.

[0009] In some embodiments, a first cross-section and a second cross-section of the top portion contact the curved surface and are perpendicular to the first direction, and the first cross-section of the top portion is further away from the body portion along the first direction than the second cross-section. The dimension of the first cross-section along a third direction perpendicular to both the first and second directions is greater than the dimension of the second cross-section along that third direction.

[0010] In some embodiments, the top portion includes a first portion and a second portion arranged along the first direction. The second portion is connected to the body portion. The first portion is further away from the body portion along the first direction than the second portion. The dimension of the first portion along a third direction perpendicular to both the first and second directions is greater than or equal to the dimension of the second portion along that third direction.

[0011] In some embodiments, the third section of the top portion contacts the flat surface and is perpendicular to the first direction, and the dimension of the third section along the third direction is smaller than the dimension of the section of the main body portion along the third direction.

[0012] In some embodiments, the second portion of the top portion is smaller in size along the third direction than the body portion is in size along the third direction.

[0013] In some embodiments, the top portion of the gate line structure extends along the first direction beyond the length of the channel plug in the range of 20 nanometers (nm) to 300 nm.

[0014] In some embodiments, the gate line structure includes an outer layer and an inner layer surrounded by the outer layer, the outer layer comprising a dielectric material and the inner layer comprising a semiconductor material.

[0015] In some embodiments, the semiconductor structure includes a semiconductor layer connected to the body portion of the gate line structure and the bottom end of the first channel structure.

[0016] In some embodiments, the semiconductor structure is a first semiconductor structure, the semiconductor device further includes a second semiconductor structure, the second semiconductor structure includes peripheral circuitry configured to control the channel structure, and the first semiconductor structure is connected to the second semiconductor structure along the first direction.

[0017] In some embodiments, the semiconductor device further includes a substrate and peripheral circuitry. The peripheral circuitry is configured to control the channel structure. The peripheral circuitry is located between the stack and the substrate along the first direction. The peripheral circuitry is connected to the body portion of the gate line structure and the bottom end of the first channel structure.

[0018] Another aspect of this disclosure features a method comprising forming a semiconductor structure including a stack of sacrificial layers and isolation layers alternating with each other along a first direction. The method further includes forming a channel structure extending through the stack along the first direction. The channel structure includes at least a first channel structure having a top end and a bottom end along the first direction. The first channel structure includes a channel plug at the top end. The method further includes forming a gate line structure. The gate line structure includes a top portion and a body portion arranged along the first direction. The top portion of the gate line structure is further away from the bottom end of the first channel structure along the first direction than the channel plug.

[0019] In some embodiments, the method further includes depositing a dielectric layer on top of the stack to cover the channel structure and gate line vias. The gate line vias are spaced apart from each other along a second direction perpendicular to the first direction and are filled with a filler material. The method further includes forming trenches in the dielectric layer to expose the filler material in the gate line vias; removing the filler material from the gate line vias; and forming gate line spaces by extending the trenches and the gate line vias, wherein the extended gate line vias are connected.

[0020] In some embodiments, the gate line space includes a top portion formed by an extended trench and a body portion formed by an extended gate line via. A first cross-section and a second cross-section of the top portion are perpendicular to the first direction. The first cross-section of the top portion is further away from the body portion along the first direction than the second cross-section. The dimension of the first cross-section along a third direction perpendicular to both the first and second directions is greater than the dimension of the second cross-section along that third direction.

[0021] In some embodiments, the third section of the top portion is adjacent to the main body portion and perpendicular to the first direction, and the dimension of the third section along the third direction is smaller than the dimension of the main body portion along the third direction.

[0022] In some embodiments, the method further includes forming gate line vias and channel vias extending through the stack along the first direction. The gate line vias include gate line vias in the array region of the semiconductor structure and gate line vias in the connection region of the semiconductor structure. The channel structure is formed in the channel vias.

[0023] In some embodiments, the method further includes forming a channel structure in the channel via before forming the gate line space by extending the trench and the gate line via. The channel structure is formed by depositing a high-k layer, a barrier layer, a charge trapping layer, a tunneling layer, a channel layer, and a core filler layer into each of the channel vias.

[0024] In some embodiments, forming the semiconductor structure includes: depositing a plurality of decks of sacrificial and isolation layers, wherein the stack comprises the plurality of decks; and forming the gate line vias and the channel vias in each of the plurality of decks by a corresponding etching process.

[0025] In some embodiments, the method further includes removing the sacrificial layer in the stack and forming a conductive layer between the isolation layers in the stack by filling the gate line space with an etchant.

[0026] In some embodiments, forming the gate line structure includes: forming an outer layer of the gate line structure by depositing a dielectric material on the inner surface of the gate line space; and forming an inner layer of the gate line structure by depositing a semiconductor material into the gate line space.

[0027] Another aspect of this disclosure features a memory system. The memory system includes a memory device and a memory controller coupled to and configured to control the memory device. The memory device includes a semiconductor structure comprising a stack of conductive and insulating layers alternating with each other along a first direction. The memory device also includes a channel structure extending through the stack along the first direction. The channel structure includes at least a first channel structure having a top end and a bottom end. The first channel structure includes a channel plug in the top end. The memory device also includes a gate line structure extending through the stack along the first direction. The gate line structure includes a top portion and a body portion arranged along the first direction. The top portion is further away from the bottom end of the first channel structure along the first direction than the channel plug.

[0028] In some embodiments, the side surface of the top portion includes a curved surface and a flat surface, the flat surface being located between the curved surface and the body portion along the first direction, and the side surface of the body portion includes a series of curved surfaces arranged along a second direction perpendicular to the first direction.

[0029] In some embodiments, the top portion of the gate line structure extends along the first direction beyond the length of the channel plug in the range of 20 nm to 300 nm.

[0030] Details of one or more embodiments of the subject matter of this disclosure are set forth in the accompanying drawings and the following description. Other features, aspects, and advantages of the subject matter will become apparent from the specification, drawings, and claims. Attached Figure Description

[0031] Figure 1A-1F An example semiconductor device is shown.

[0032] Figure 2A-2U An example process for manufacturing a semiconductor device is shown.

[0033] Figure 3A-3N Another example process for manufacturing a semiconductor device is shown.

[0034] Figure 4 A flowchart illustrating an example process for manufacturing a semiconductor device is shown.

[0035] Figure 5 A block diagram of the example system is shown.

[0036] Similar reference numerals and names in the various figures indicate similar elements. It should also be understood that the various exemplary embodiments shown in the figures are merely illustrative representations and are not necessarily drawn to scale. Detailed Implementation

[0037] Due to the demand for cheaper memory devices with higher density, memory devices (e.g., 3D NAND flash memory) can be formed with multiple stacks, each stack potentially containing a large number of layers. The large number of layers and high aspect ratio of such memory devices can pose challenges to the manufacturing process. For example, increasing the depth of the memory device can introduce or exacerbate overlay (OVL) problems during manufacturing. In some implementations, the same etch mask can be used to form both channel vias and gate line vias in the same etch process. Gate line vias can be extended to form gate line slits (also known as gate line spaces). This process, referred to as channel-to-gate-line via merging, can widen the process window during manufacturing and mitigate or resolve OVL problems. During the manufacturing process, a channel structure is formed in the channel vias, and the gate line spaces are filled with a filler material such as polysilicon. The channel plug at the top of the channel structure can also comprise polysilicon. Therefore, if the tops of the gate line spaces and the channel structures are on the same vertical plane, a protective film can be formed to protect the channel plug when the polysilicon is removed from the gate line spaces. The protective film may require a separate manufacturing process and may include an opening aligned with the top of the gate line space, which imposes stringent processing window requirements and increases the cost of the manufacturing process.

[0038] Embodiments of this disclosure provide systems, apparatus, methods, and techniques for managing gate line structures in semiconductor devices, which can address one or more of the problems described above. In some embodiments, the semiconductor device includes a gate line structure and a channel structure. The gate line structure includes a top portion and a body portion arranged in a vertical direction. The top portion of the gate line structure is higher than the channel plug in the vertical direction. For example, the top portion of the gate line structure may be further away from the bottom end of the channel structure in the vertical direction than the channel plug of the channel structure.

[0039] Embodiments of this disclosure may provide one or more of the following technical advantages and / or benefits. For example, the channel plug is below the top of the gate line structure and is therefore protected by a dielectric layer on top of the channel plug. Therefore, a separate process for forming a protective film may not be necessary, thereby increasing product yield and reducing manufacturing costs. The gate line space containing the gate line structure may have trench-shaped openings, thereby addressing the OVL (Out-of-Vehicle) problem and expanding the processing window.

[0040] This technology can be applied to various types of semiconductor devices, volatile memory devices (e.g., DRAM memory devices), or non-volatile memory (NVM) devices (e.g., NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase-change memory (PCM) (e.g., PCRAM), spin-transfer torque (STT)-magnetoresistive random access memory (MRAM), etc.). It can also be applied to charge-trap-based memory devices, such as silicon-oxide-nitride-oxide-silicon (SONOS) memory devices and floating-gate-based memory devices. This technology can be applied to three-dimensional (3D) memory devices. It can be applied to various memory types, such as SLC (single-cell) devices, MLC (multi-cell) devices (e.g., 2-cell devices), TLC (triple-cell) devices, QLC (quadruple-cell) devices, or PLC (five-cell) devices. Alternatively or concurrently, this technology can be applied to various types of devices and systems, such as secure digital cards (SD cards), embedded multimedia cards (eMMC), solid-state drives (SSDs), embedded systems, etc.

[0041] It should be noted that, Figure 1A-1F The X, Y, and Z axes (also referred to as the X, Y, and Z directions) are included to further illustrate the spatial relationships of various components in a semiconductor device. The substrate of a semiconductor device may include two lateral surfaces extending laterally in the XY plane: a top surface on the front side of the substrate, on which components of the semiconductor device may be formed; and a bottom surface on the back side opposite the front side of the substrate. The Z direction is perpendicular to the X and Y directions. As used in this disclosure, when the substrate is positioned in the lowest plane of the semiconductor device in the Z direction (a direction perpendicular to the XY plane, e.g., the thickness direction of the substrate), the Z direction relative to the substrate of the semiconductor device determines whether one component (e.g., a layer or device) of the semiconductor device is “on,” “above,” or “below” another component (e.g., a layer or device). The same concepts used to describe spatial relationships are applied throughout this disclosure.

[0042] Figure 1A A top view of an example semiconductor device 100 is shown. Semiconductor device 100 may be a memory device, such as a three-dimensional (3D) NAND memory device. Semiconductor device 100 may include one or more array regions and one or more connection regions configured to provide conductive connections for the one or more array regions. In some embodiments, such as Figure 1AAs shown, the semiconductor device 100 includes two array regions 111 and a connection region 109 between the two array regions along a first horizontal direction (e.g., the X direction). Each array region 111 may include an array of channel structures 112. Each channel structure 112 can be used to form a string of memory cells coupled in series along a vertical direction perpendicular to the first horizontal direction (e.g., the Z direction). In some embodiments, the connection region 109 may include a stepped structure (not shown) and an array of contact structures 114 formed on the stepped structure. In some other embodiments, the conductive layer in the connection region 109 (e.g., as described below) Figure 1B The conductive layer 104A in the array of contact structures 114 can form a structure different from the stepped structure. For example, the contact structures in the array of contact structures 114 can be connected to the corresponding conductive layer and can extend through other conductive layers, and spacers for isolation can be formed between the contact structures and other conductive layers.

[0043] In some implementations, the gate line structure 116 extending in the X direction can divide the array region into multiple portions, each portion being referred to as a memory block (e.g., such as...). Figure 1A (Referring to memory blocks 118-1 and 118-2). In some embodiments, two adjacent portions 118-1 and 118-2 may be considered a single memory block, and each of portions 118-1 and 118-2 may be referred to as a memory finger. In some embodiments, at least some gate line structures 116 may be used as common source contacts for channel structures 112 in array region 111. Top Select Gate (TSG) cutouts 120 may be provided, for example, in each of memory blocks 118-1 and 118-2 to divide the memory block into smaller portions. In some cases, each TSG cutout 120 may extend through (e.g., vertically) a stack of alternating conductive and insulating layers in the semiconductor device 100 (e.g., as described below). Figure 1B One or more conductive layers are located on top of the stack 104. In some embodiments, the array region 111 and the connection region 109 may include dummy channel structures or dummy memory strings (not shown) for process variation control during manufacturing and / or for additional mechanical support.

[0044] Figure 1B It shows along Figure 1A The image shows a cross-sectional view of the semiconductor device 100 along the cut line AA'. The semiconductor device 100 may include a semiconductor structure 101 and a semiconductor structure 102. In some embodiments, the semiconductor device 100 is a bonded chip, with semiconductor structure 101 stacked on top of semiconductor structure 102 (e.g., along the Z direction). Semiconductor structures 101 and 102 may have a bonding structure or bonding layer therebetween. Figure 1B(Not shown in the image) is bonded at the location. In some embodiments, as a result of hybrid bonding (also known as “metal / dielectric hybrid bonding”), the bonding structure is disposed between semiconductor structures 101 and 102. Hybrid bonding is a direct bonding technique (e.g., forming a bond between surfaces without using an intermediate layer, such as solder or adhesive) and can simultaneously achieve metal-to-metal bonding and dielectric-to-dielectric bonding.

[0045] Semiconductor structure 102 may include a substrate (not shown), which may include silicon (e.g., single-crystal silicon, c-Si), SiGe, GaAs, Ge, SOI, or any other suitable material. Semiconductor structure 102 may include peripheral circuitry (not shown) on the substrate. The peripheral circuitry may be configured to control components of semiconductor structure 101 (e.g., conductive layer 104A and channel structure 112 as described below). In some embodiments, the peripheral circuitry includes multiple transistors (e.g., planar transistors and / or 3D transistors). Trench isolation (e.g., shallow trench isolation (STI)) and doped regions (e.g., transistor wells, sources, and drains) may also be formed on or in the substrate. In some examples, the peripheral circuitry is formed using complementary metal-oxide-semiconductor (CMOS) technology, and semiconductor structure 102 may be formed on a semiconductor die referred to as a control die or CMOS die.

[0046] Semiconductor structure 101 may have two sides 130 and 132 that are opposite to each other along the Z direction. In some embodiments, side 132 of semiconductor structure 101 may be bonded to semiconductor structure 102. Side 130 is further away from semiconductor structure 102 and may be referred to as the top side. Side 132 may be referred to as the bottom side.

[0047] Semiconductor structure 101 may include a stack 104 of alternating conductive layers 104A and isolation layers 104B. The stack 104 may extend across both memory blocks 118-1 and 118-2. The stack 104 may extend in a second horizontal direction (e.g., the Y direction) perpendicular to the first horizontal direction. The conductive layers 104A and isolation layers 104B may alternate in a vertical direction (e.g., the Z direction) perpendicular to the second horizontal direction. The thicknesses of the conductive layers 104A may be the same or different from each other, for example, ranging from 10-500 nm, such as about 35 nm. The thicknesses of the isolation layers 104B may also be the same or different from each other, for example, ranging from 10-500 nm, such as about 25 nm. It should be noted that... Figure 1BThe number of conductive layers 104A and insulating layers 104B shown is for illustrative purposes only; any suitable number of conductive layers 104A and insulating layers 104B may be included in the stack 104. In some embodiments, the stack 104 may include multiple stacks stacked in a vertical direction (e.g., the Z direction). Each of the multiple stacks may include a subset of the conductive layers 104A and insulating layers 104B in the stack 104.

[0048] The conductive layer 104A may comprise any suitable conductive material, such as tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), polycrystalline silicon, doped silicon, silicide, or any combination thereof. The isolation layer 104B may comprise a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the isolation layer 104B may also comprise a high-k dielectric material, such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, lanthanum oxide, or any combination thereof. In some embodiments (… Figure 1B (Not shown in the diagram), the stack 104 includes a padding layer. The padding layer may cover part or all of the sides of the corresponding conductive layer 104A and is located between the conductive layer 104A and two insulating layers 104B adjacent to the corresponding conductive layer 104A. The padding layer may include a high-k dielectric material (e.g., Al2O3). In some examples, the conductive layer 104A includes a metallic material (e.g., W) and an adhesive material (e.g., TiN), and the adhesive material may be deposited between the metallic material and the high-k dielectric material. In some examples, the conductive layer 104A includes a metallic material (e.g., W), and the padding layer includes an adhesive material (e.g., TiN) and a high-k dielectric material.

[0049] In some embodiments, the semiconductor structure 101 may further include a semiconductor layer 103 positioned vertically between the stack 104 and the semiconductor structure 102. The semiconductor layer 103 may comprise any suitable semiconductor material (e.g., polysilicon). In some embodiments, the semiconductor layer 103 may be removed from the semiconductor structure 101 in subsequent processes for manufacturing the semiconductor device 100.

[0050] like Figure 1BAs shown, each memory block of the semiconductor device 100 (e.g., memory block 118-1 or 118-2) includes a channel structure 112 extending vertically through the stack 104. Each channel structure 112 may be cylindrical or pillar-shaped and may include a high-k layer 112a, a barrier layer surrounded by the high-k layer, a charge trapping layer (or storage layer) surrounded by the barrier layer, a tunneling layer surrounded by the charge trapping layer, a channel layer 112c surrounded by the tunneling layer, and a core filler layer 112d surrounded by the channel layer 112c, and a channel plug 112e formed above the core filler layer 112d and in contact with the channel layer 112c. In some embodiments, the channel layer 112c may include silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon; the tunneling layer may include silicon oxide, silicon nitride, or any combination thereof; the barrier layer may include silicon oxide, silicon nitride, a high-k dielectric, or any combination thereof; and the charge trapping layer may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. In some embodiments, the tunneling layer, charge trapping layer, and barrier layer (collectively referred to as storage film 112b) may include an ONO dielectric (silicon oxide-silicon nitride-silicon oxide).

[0051] Each channel structure 112 has two ends 122 and 124 arranged opposite to each other along the Z direction. End 122 is closer to the top side 130 of the semiconductor structure 101. Channel plugs 112e of the channel structures 112 are located in the ends 122. The semiconductor structure 101 may also include an interconnect layer 126 adjacent to the top side 130. The channel plugs 112e of each channel structure 112 may be coupled to the interconnect layer 126 (e.g., via...). Figure 1B The vertical conductive structure 113 shown. An isolation structure 115, which may include a dielectric material such as silicon oxide, may be formed between the vertical conductive structures 113 to isolate them. An interconnect layer 126 may include interconnects and may transmit electrical signals between the channel structure 112 and external circuitry, for example, for pad take-out purposes. In some embodiments, the end 124 of each channel structure 112 is connected to a semiconductor layer 128 adjacent to the bottom side 132. For example, the high-k layer 112a and the memory film 112b (e.g., ONO) at the end 124 may be removed to expose the channel layer 112c (e.g., polysilicon). The channel layer 112c at the end 124 may be connected to the semiconductor layer 128. The semiconductor layer 128 may be made of any suitable semiconductor material (e.g., polysilicon) and may serve as a common source for an array of memory strings (e.g., channel structures 112) of the semiconductor device 100.

[0052] like Figure 1A As shown, one or more gate line structures 116 may be formed in the array region 111 in a first horizontal direction (e.g., the X direction) to divide the semiconductor device 100 into a plurality of memory blocks (e.g., memory blocks 118-1 and 118-2). Figure 1B A cross-sectional view of one of the gate line structures 116 is shown. The gate line structure 116 extends along a first horizontal direction (e.g., the X direction) and is located between memory blocks 118-1 and 118-2 (e.g., as shown in the diagram). Figure 1A As shown). Figure 1B As shown, the gate line structure 116 extends through the stack 104 and the semiconductor layer 103 in a direction perpendicular to the first horizontal direction (e.g., the X direction) and the second horizontal direction (e.g., the Y direction). The gate line structure 116 isolates the conductive layer 104A of memory block 118-1 from the conductive layer 104A of memory block 118-2. For example, the gate line structure can contact the sidewalls of memory block 118-1 and memory block 118-2 along the Y direction.

[0053] The gate line structure 116 includes a top portion 138 and a body portion 140 arranged along the Z direction. The top portion 138 of the gate line structure 116 is further away from the bottom end 124 of the channel plug 112e along the Z direction. In some embodiments, the top portion 138 of the gate line structure 116 may extend along the Z direction beyond the length of the channel plug 112e between 20 nanometers (nm) and 300 nm. For example, the distance (along the Z direction) between the top tip of the gate line structure (closer to the end of the top side 130 of the semiconductor structure 101) and the channel plug 112e may be in the range of 50 nm to 150 nm. In some embodiments (e.g., as shown in the figure), Figure 1A As shown), the gate line structure 116 may have an outer layer 134 and an inner layer 136 surrounded by the outer layer (e.g., in each of the top portion 138 and the body portion 140). The outer layer 134 comprises a dielectric material (e.g., silicon oxide), and the inner layer 136 comprises a semiconductor material (e.g., polysilicon). The semiconductor layer 128 may be connected to the body portion 140 of the gate line structure 116 (e.g., the end of the inner layer 136 closer to the bottom side 132 of the semiconductor structure 101). In some other embodiments (e.g., Figure 3N In the gate line structure 316), the gate line structure 116 can be a solid semiconductor structure made of a suitable semiconductor material such as polycrystalline silicon.

[0054] Figure 1C An enlarged view of the gate line structure 116 is shown. (As shown) Figure 1CAs shown, the top portion 138 has two side surfaces 142 opposite to each other in the Y direction relative to the inner layer 136. The body portion 140 also has two side surfaces 150 opposite to each other in the Y direction relative to the inner layer 136. The top portion 138 includes a first portion 138a and a second portion 138b arranged in the Z direction. The second portion 138b is connected to the body portion 140 of the gate line structure 116. The first portion 138a is further away from the body portion 140 in the Z direction than the second portion 138b. Each side surface 142 includes a curved surface 142a (e.g., the side surface of the first portion 138a) and a flat surface 142b (e.g., the side surface of the second portion 138b). The flat surface 142b is located in the Z direction between the curved surface 142a and the body portion 140. The flat surface 142b may be a smooth surface without lumps or dents. In some embodiments, the dimension (e.g., the maximum dimension) of the first portion 138a in the Y direction may gradually increase in the Z direction. For example, sections 144 and 146 of the first portion 138a contact the curved surface 142a and are perpendicular to the Z direction. Section 144 is further away from the main body portion 140 along the Z direction than section 146. The dimension (e.g., maximum dimension) of section 144 along the Y direction is greater than the dimension (e.g., maximum dimension) of section 146 along the Y direction. In some examples, the dimension may be the length along the Y direction.

[0055] The dimension (e.g., maximum dimension) of the first portion 138a along the Y direction may be greater than or equal to the dimension (e.g., maximum dimension) of the second portion 138b along the Y direction. In some embodiments, the dimension of the second portion 138b along the Y direction may be consistent along the Z direction. In some embodiments, the dimension of the second portion 138b along the Y direction may be smaller than the dimension (e.g., maximum dimension) of the main body portion 140 along the Y direction. For example, section 148 of the second portion 138b contacts the flat surface 142b and is perpendicular to the Z direction. Section 149 of the main body portion 140 contacts the surface 150 and is perpendicular to the Z direction. The dimension (e.g., maximum dimension) of section 148 along the Y direction is smaller than the dimension (e.g., maximum dimension) of section 149 along the Y direction. It should be understood that... Figure 1C The examples shown are for illustrative purposes only and are not intended to be limiting. In some implementations (e.g., such as...), Figure 2R and Figure 2T As shown in the diagram, the dimension of the second portion 138b along the Y direction may be the same as the dimension of the main portion 140 along the Y direction. In some other embodiments, the dimension of the second portion 138b along the Y direction may be larger than the dimension of the main portion 140 along the Y direction.

[0056] Figure 1D-1E It shows along Figure 1A A cross-sectional view of the semiconductor device 100 with cut lines BB' and CC'. (See figure) Figure 1D As shown, the side surface 142 of the top portion 138 of the gate line structure 116 can have a uniform profile along the X direction. For example... Figure 1E As shown, the lateral cross-section of the main body portion 140 of the gate line structure 116 is a partially circular shape arranged in the X direction and connected together. Each side surface 150 of the main body portion 140 includes a series of curved surfaces 152 arranged in the X direction. That is, the side surface 150 includes a wave pattern (e.g., 152) that repeats in the X direction.

[0057] Figure 1F Semiconductor device 100-1 is shown, which is another embodiment of semiconductor device 100. Semiconductor device 100-1 includes a stack 104, a semiconductor layer 103, a channel structure 112, a gate line structure 116, and an interconnect layer 126, which may be the same as or similar to corresponding components in semiconductor device 100. Semiconductor device 100-1 may also include a substrate 154 and peripheral circuitry 156. Substrate 154 may be any suitable semiconductor substrate having any suitable semiconductor material, such as single-crystal, polycrystalline, or monocrystalline semiconductor. For example, substrate 154 may include silicon, silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium nitride, silicon carbide, III-V compounds, or any combination thereof. Peripheral circuitry 156 is located between stack 104 and substrate 154 along the Z-direction. Peripheral circuitry 156 may be configured to control components of semiconductor device 100-1 (e.g., conductive layer 104A and channel structure 112). In some implementations, the peripheral circuitry 156 may be connected to the bottom of the gate line structure 116 (e.g., the inner layer of the main body portion of the gate line structure 116) and the channel structure 112 (e.g., the channel layer of each channel structure 112).

[0058] Figure 2A-2U It shows the manufacturing of semiconductor devices (such as...) Figure 1A-1F Example process of semiconductor device 100 or semiconductor device 100-1 shown. Figure 2A-2U Cross-sectional views of an example semiconductor structure at various stages of the manufacturing process are shown (e.g., along the...). Figure 1A (The cutting line at the same position as the cutting line AA').

[0059] like Figure 2AAs shown, a semiconductor structure 200a is formed. The semiconductor structure 200a includes a substrate 254 and a stack 204-1 of a sacrificial layer 204C and an isolation layer 204B. The sacrificial layer 204C and the isolation layer 204B may alternate with each other along a vertical direction (e.g., the Z direction). Each of the substrate 254 and the sacrificial layer 204C and the isolation layer 204B may extend in an XY plane. The semiconductor structure 200a also includes a semiconductor layer 203 located between the stack 204-1 and the substrate 254 along the Z direction. The semiconductor layer 203 may be made of a suitable semiconductor material (e.g., polycrystalline silicon). The semiconductor structure 200a can be formed, for example, by depositing the stack 204-1 of the sacrificial layer 204C and the isolation layer 204B over the semiconductor layer 203. The isolation layer 204B may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the sacrificial layer 204C may include a dielectric material different from that of the isolation layer 204B. For example, the isolation layer 204B may include silicon oxide, and the sacrificial layer 204C may include silicon nitride.

[0060] Semiconductor structure 200a includes gate line vias 217-1 disposed in a line extending along the X direction. The gate line vias 217-1 are spaced apart from each other along the line. The gate line vias 217-1 may include an array region of semiconductor structure 200a (e.g., Figure 1A The gate line vias in the array region 111) and the connection regions of the semiconductor structure 200a (e.g., Figure 1A The semiconductor structure 200a also includes an array of channel vias 213-1 on both sides of the gate via 217-1 along the Y direction. The gate via 217-1 and the channel via 213-1 extend along the Z direction through the stack 204-1 and the semiconductor layer 203 and into the substrate 254. In some embodiments, the gate via 217-1 and the channel via 213-1 can be formed by the same etching process (e.g., a first etching process).

[0061] like Figure 2BAs shown, a semiconductor structure 200b is formed. The semiconductor structure 200b includes a stack 204-2 consisting of a sacrificial layer 204C and an isolation layer 204B on top of a stack 204-1. The sacrificial layer 204C and the isolation layer 204B in the stack 204-2 may alternate with each other along a vertical direction (e.g., the Z direction). The semiconductor structure 200b includes gate line vias 217-2 and channel vias 213-2 in the stack 204-2. The gate line vias 217-2 and the channel vias 213-2 may extend through the stack 204-2 along the Z direction. Each of the gate line vias 217-2 may be disposed on top of a corresponding gate line via 217-1. Each of the channel vias 213-2 may be disposed on top of a corresponding channel via 213-1. That is, each gate via 217-2 is connected to and aligned with the corresponding gate via 217-1 along the Z direction, and each channel via 213-2 is connected to and aligned with the corresponding channel via 213-1 along the Z direction. The gate vias 217-2 and 213-2 can be formed by the same etching process (e.g., a second etching process).

[0062] like Figure 2C As shown, the semiconductor structure 200c is formed by filling, for example, gate line vias 217-1 and 217-2 and channel vias 213-1 and 213-2 with a sacrificial material (e.g., carbon).

[0063] Figure 2D A semiconductor structure 200d is shown, comprising a stack 204-3 including a sacrificial layer 204C and an isolation layer 204B. The sacrificial layer 204C and the isolation layer 204B in the stack 204-3 may alternate with each other along a vertical direction (e.g., the Z direction). For example, the semiconductor structure 200d can be formed by depositing a stack 204-3 of sacrificial layer 204C and isolation layer 204B on top of a stack 204-2.

[0064] like Figure 2EAs shown, a semiconductor structure 200e is formed. The semiconductor structure 200e includes a gate line via 217-3 and a channel via 213-3 in a stack 204-3. The gate line via 217-3 and the channel via 213-3 extend through the stack 204-3 in the Z direction and expose sacrificial material in the gate line via 217-2 and the channel via 213-2. Each of the gate line vias 217-3 may be disposed on top of the corresponding gate line via 217-2. Each of the channel vias 213-3 may be disposed on top of the corresponding channel via 213-2. That is, each gate via 217-3 is aligned along the Z-direction with its corresponding gate via 217-2 (and the corresponding gate via 217-1 below it), and each channel via 213-3 is aligned along the Z-direction with its corresponding channel via 213-2 (and the corresponding channel via 213-1 below it). The gate vias 217-3 and 213-3 can be formed using the same etching process (e.g., a third etching process). The sacrificial material in the gate vias 217-2 and 217-1 and the channel vias 213-2 and 213-1 can be removed, for example, by burn-off. The aligned gate vias 217-1, 217-2, and 217-3 can form a gate via 217. The aligned channel vias 213-1, 213-2, and 213-3 can form a channel via 213. Stacks 204-1, 204-2, and 204-3 may form a stack 204. It should be understood that while in semiconductor structure 200e, the stack 204 comprises three stacks (e.g., stacks 204-1, 204-2, and 204-3), and each of the gate line via 217 and the channel via 213 has three segments, semiconductor structure 200e is merely an illustrative example. In practice, the stack 204 may comprise any suitable number of stacks, and each stack may comprise any suitable number of alternating sacrificial layers and isolation layers.

[0065] Figure 2F A semiconductor structure 200f including a protective structure 205 is shown. The protective structure 205 may include polyoxide and may be formed on the bottom of the gate line via 217 and the channel via 213 to protect the substrate 254. The protective structure 205 may also be formed on the sidewalls of the semiconductor layer 203 exposed by the gate line via 217 and the channel via 213 to protect the semiconductor layer 203.

[0066] like Figure 2G As shown, a semiconductor structure 200g is formed by filling, for example, gate line vias 217 and channel vias 213 with a filling material (e.g., polysilicon).

[0067] like Figure 2HAs shown, the semiconductor structure 200h is formed by depositing a sacrificial film 206 on top of the semiconductor structure 200g to cover the gate line via 217 and the channel via 213. The sacrificial film 206 may include a dielectric material, such as silicon nitride.

[0068] Figure 2I A semiconductor structure 200i is shown, which includes an opening 207 formed in a sacrificial film 206 and on top of a channel hole 213 to expose the filling material in the channel hole 213.

[0069] Figure 2J A semiconductor structure 200j formed by removing the filling material in the channel via 213 is shown.

[0070] like Figure 2K As shown, a semiconductor structure 200k is formed by depositing a high-k layer 212a, a storage film 212b, a channel layer 212c, and a core-filler layer 212d into each channel via 213. The storage film 212b may include a barrier layer, a charge trapping layer, and a tunneling layer. In some embodiments, the channel layer 212c may include silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon; the tunneling layer may include silicon oxide, silicon nitride, or any combination thereof; the barrier layer may include silicon oxide, silicon nitride, a high-k dielectric, or any combination thereof; and the charge trapping layer may include silicon nitride, silicon oxynitride, silicon, or any combination thereof.

[0071] like Figure 2L As shown, a semiconductor structure 200l is formed including channel plugs 212e. Each channel plug 212e includes polysilicon and is disposed above the core filler layer 212d. The channel plug 212e may contact the channel layer 212c.

[0072] like Figure 2M As shown, the semiconductor structure 200m is formed by removing excess material (e.g., a portion of each channel plug 212E, a portion of the dielectric material on top of the stack 204, and a portion of the filling material in the gate line via 217) from the top of the semiconductor structure 200l using a planarization process (such as chemical mechanical polishing (CMP)). The remaining structure in each channel via 213 of the semiconductor structure 200m can be referred to as the corresponding channel structure 212, which includes a high-k layer 212a, a storage film 212b, a channel layer 212c, a core filler layer 212d, and a channel plug 212e.

[0073] like Figure 2N As shown, the semiconductor structure 200n is formed by depositing a dielectric layer 208 (e.g., silicon oxide) on top of the semiconductor structure 200m to cover the filling material in the channel structure 212 and the gate line via 217.

[0074] Figure 2OA semiconductor structure 200o is shown, which includes a gate line trench 210 extending in the X direction on top of a gate line via 217. The gate line trench 210 can be formed by an etching process and can extend in the Z direction through a dielectric layer 208 to expose the fill material in the gate line via 217. Although Figure 2O The example shown has the same Y-direction dimension as the gate line trench 210 and the gate line via 217 (e.g., the maximum dimension), but this example is not intended to be limiting. In some other embodiments, the Y-direction dimension of the gate line trench 210 may be smaller or larger than the Y-direction dimension of the gate line via 217.

[0075] like Figure 2P As shown, a semiconductor structure 200p is formed by removing the filling material in the gate line hole 217.

[0076] Figure 2Q A semiconductor structure 200q including a gate line space 215 is shown. The gate line space 215 can be formed by extending the gate line trench 210 and gate line via 217 using an etching process. The etching process can remove the dielectric material (e.g., a portion of the dielectric layer 208 and stack 204) exposed by the gate line trench 210 and gate line via 217. The extended gate line vias 217 can be connected to each other in the X direction. In some embodiments, a portion of the semiconductor layer 203 is exposed by the gate line space 215 because the etching process may not remove the semiconductor material in the semiconductor layer 203.

[0077] Figure 2R A semiconductor structure 200r including an extended gate line space 215 is shown. The gate line space 215 can be extended by removing (e.g., by another etching process) a portion of the semiconductor layer 203 in the semiconductor structure 200r. The gate line space 215 in the semiconductor structure 200r includes a top portion 215a, a body portion 215b, and a bottom portion 215c. The top portion 215a is formed by an extended gate line trench 210. The body portion 215b is formed by extending beyond a portion of each gate line via 217 in the substrate 254. The bottom portion 215c is formed by a portion of each gate line via 217 in the substrate 254. In some embodiments, reference is made to... Figure 2QThe described etching process is an isotropic wet etching process, and a rounded corner 219 is created adjacent to the top surface of the dielectric layer 208. Therefore, the top portion 215a includes a first portion 215a-1 and a second portion 215a-2 arranged along the Z direction. The first portion 215a-1 is located along the Y direction between two curved side surfaces of the rounded corner 219. The second portion 215a-2 is located along the Y direction between two flat surfaces below the rounded corner 219. Cross-sections 244 and 246 of the first portion 215a-1 are perpendicular to the Z direction. Cross-section 244 is further away from the substrate 254 along the Z direction than cross-section 246. The dimension (e.g., maximum dimension) of cross-section 244 along the Y direction is greater than the dimension (e.g., maximum dimension) of cross-section 246 along the Y direction.

[0078] The cross-section 248 of the second part 215a-2 is perpendicular to the Z direction. The cross-section 249 of the main body part 215b is perpendicular to the Z direction. The gate line trench 210 and gate line via 217 in the semiconductor structure 200o can be defined by a reference. Figure 2Q The etching rate of the described etching process is determined by a similar rate expansion. Therefore, the difference between the dimension of section 248 along the Y direction (e.g., the maximum dimension) (referred to as the first expanded dimension) and the dimension of section 249 along the Y direction (e.g., the maximum dimension) (referred to as the second expanded dimension) can be determined by the dimension of the gate line trench 210 in the semiconductor structure 200o along the Y direction (referred to as the first unexpanded dimension) and the dimension of the gate line via 217 in the semiconductor structure 200o along the Y direction (referred to as the second unexpanded dimension). For example, if the first unexpanded dimension is similar to or equal to the second unexpanded dimension (e.g., as...), Figure 2O As shown), the first extended size can be similar to or equal to the second extended size (e.g., as shown). Figure 2R (As shown). In another example, if the first unexpanded size is greater than the second unexpanded size, then the first expanded size can be greater than the second expanded size. In another example, if the first unexpanded size is less than the second unexpanded size, then the first expanded size can be less than the second expanded size.

[0079] Figure 2S A semiconductor structure 200s including a conductive layer 204A is shown. The sacrificial layer 204C in the stack 204 is replaced by the conductive layer 204A. The sacrificial layer 204C can be etched away, for example, by filling the gate line space 215 with etchant. The conductive layer 204A can then be formed between the isolation layers 204B and replace the sacrificial layer 204C to form a new stack 204.

[0080] Figure 2TA semiconductor structure 200t including a gate line structure 216 is shown. The gate line structure 216 may include an outer layer 234 formed by depositing a dielectric material (e.g., silicon oxide) on the inner surface of a gate line space 215, and an inner layer 236 formed by depositing a semiconductor material (e.g., polysilicon) into the space surrounded by the outer layer 234 in the gate line space 215. In some embodiments, the gate line structure 216 may be a solid semiconductor structure without a dielectric material and may be formed by depositing a semiconductor material (e.g., polysilicon) into the gate line space 215. For example, the gate line structure 216 may be similar to a reference design. Figure 3N The gate line structure 316 is described. The gate line structure 216 in the top portion 215a of the gate line space 215 can be referred to as the top portion 238 of the gate line structure 216. The gate line structure 216 in the body portion 215b of the gate line space 215 can be referred to as the body portion 240 of the gate line structure 216. The top portion 238 is further away from the bottom end of the channel structure 212 along the Z direction than the channel plug 212e.

[0081] Figure 2U A semiconductor structure 200u including a semiconductor layer 228 is shown. The substrate 254 of the semiconductor structure 200u is removed. Additionally, a portion of each channel structure 212 in the substrate 254 may be removed. For example, as... Figure 2U As shown, a portion of the storage film 212b of the channel structure 212, which includes the ONO dielectric (silicon oxide-silicon nitride-silicon oxide), can be removed. Therefore, the core filler layer 212d of the channel structure 212 can be exposed. A semiconductor layer 228 can be formed by depositing a suitable semiconductor material (e.g., polysilicon). The semiconductor layer 228 is connected to the gate line structure 216 and the channel structure 212.

[0082] The stacked body 204, channel structure 212, gate line structure 216, and semiconductor layer 228 of the semiconductor structure 200u can be compared with a reference. Figure 1A-1E The corresponding components of the described semiconductor device 100 are similar or identical. It should be understood that, although... Figure 2U Not shown, but the semiconductor device 100 can be formed from the semiconductor structure 200u using additional manufacturing processes, such as forming an interconnect layer 126 on top of the semiconductor structure 200u and bonding the semiconductor structure 200u to the semiconductor structure 102. It should also be understood that... Figure 1F The semiconductor device 100-1 can be used with reference Figure 2A-2U The manufacturing process is described as a suitable variation to form it.

[0083] Figure 3A-3N It shows the manufacturing of semiconductor devices (such as...) Figure 1A-1FAnother example process of the semiconductor device 100 or semiconductor device 100-1 shown. Figure 3A-3N References are shown Figure 2A-2U Some variations of the described manufacturing process. For example, a dielectric layer can be formed as a protective structure (e.g., as shown in the image). Figure 3A (As shown), which differs from the reference. Figure 2F The polyoxide described. In another example, it is possible to form a polyoxide having the characteristics of... Figure 2T The gate line structures shown are of different structures (e.g., such as...) Figure 3N (As shown). Figure 3A-3N Cross-sectional views of example semiconductor structures at various stages of the manufacturing process are shown (e.g., along the...). Figure 1F (The cutting line at the same position as the cutting line AA').

[0084] like Figure 3A As shown, by Figure 2E A dielectric layer 301 is deposited on the inner surface of each channel via 213 and each gate via 217 of the semiconductor structure 200e to form the semiconductor structure 300a. The dielectric layer 301 may also cover the top of the semiconductor structure 200e.

[0085] like Figure 3B As shown, the semiconductor structure 300b is formed by filling the gate line via 217 and the channel via 213 with a filling material (e.g., polysilicon).

[0086] like Figure 3C As shown, semiconductor structure 300c is formed by depositing a sacrificial film 306 on top of semiconductor structure 300b to cover gate line via 217 and channel via 213. The sacrificial film 306 may include a dielectric material, such as silicon nitride.

[0087] Figure 3D A semiconductor structure 300d is shown, which includes an opening 307 formed in a sacrificial film 306 and on top of a channel hole 213 to expose the filling material in the channel hole 213.

[0088] Figure 3E The semiconductor structure 300e formed by removing the filling material in the channel via 213 is shown.

[0089] like Figure 3FAs shown, a semiconductor structure 300f is formed by depositing a high-k layer 312a, a storage film 312b, a channel layer 312c, and a core-filler layer 312d into each channel via 213. The storage film 312b may include a barrier layer, a charge trapping layer, and a tunneling layer. In some embodiments, the channel layer 312c may include silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon; the tunneling layer may include silicon oxide, silicon nitride, or any combination thereof; the barrier layer may include silicon oxide, silicon nitride, a high-k dielectric, or any combination thereof; and the charge trapping layer may include silicon nitride, silicon oxynitride, silicon, or any combination thereof.

[0090] like Figure 3G As shown, a semiconductor structure 300g is formed including channel plugs 312e. Each channel plug 312e includes polysilicon and is disposed above the core filler layer 312d. The channel plug 312e may contact the channel layer 312c.

[0091] like Figure 3H As shown, the semiconductor structure 300h is formed by removing excess material (e.g., a portion of each channel plug 312e, a portion of the dielectric material on top of the stack 204, and a portion of the filling material in the gate line via 217) from the top of the semiconductor structure 300g using a planarization process (e.g., CMP). The remaining structure in each channel via 213 of the semiconductor structure 300h can be referred to as the corresponding channel structure 312, which includes a high-k layer 312a, a storage film 312b, a channel layer 312c, a core filler layer 312d, and a channel plug 312e.

[0092] like Figure 3I As shown, the semiconductor structure 300i is formed by depositing a dielectric layer 308 (e.g., silicon oxide) on top of the semiconductor structure 300h to cover the filling material in the channel structure 312 and the gate line via 217.

[0093] Figure 3J A semiconductor structure 300j is shown, which includes a gate line trench 310 extending in the X direction on top of a gate line via 217. The gate line trench 310 can be formed by an etching process and can extend in the Z direction through a dielectric layer 308 to expose the fill material in the gate line via 217. The dimension of the gate line trench 310 in the Y direction can be the same as, smaller than, or larger than the dimension of the gate line via 217 in the Y direction (e.g., the maximum dimension). Similar to reference... Figure 2R The dimensions of the gate line trench 310 can affect the dimensions of the top portion 315a of the gate line space 315, as described below. Figure 3M As shown.

[0094] like Figure 3KAs shown, the semiconductor structure 300k is formed by removing the filling material in the gate line hole 217.

[0095] Figure 3L A semiconductor structure 300l including a gate line space 315 is shown. The gate line space 315 can be formed by extending the gate line trench 310 and gate line via 217 using an etching process. The etching process can remove the dielectric material (e.g., a portion of the dielectric layer 308 and stack 204) exposed by the gate line trench 310 and gate line via 217. The extended gate line vias 217 can be connected to each other in the X direction. In some embodiments, a portion of the semiconductor layer 203 is exposed by the gate line space 315 because the etching process may not remove the semiconductor material in the semiconductor layer 203.

[0096] Figure 3M A semiconductor structure 300m including an extended gate line space 315 is shown. The gate line space 315 can be extended by removing (e.g., by another etching process) a portion of the semiconductor layer 203 in the semiconductor structure 300m. The gate line space 315 in the semiconductor structure 300m includes a top portion 315a, a body portion 315b, and a bottom portion 315c. The top portion 315a is formed by an extended gate line trench 310. The body portion 315b is formed by extending a portion of each gate line via 217 in the substrate 254. The bottom portion 215c is formed by a portion of each gate line via 217 in the substrate 254. The gate line space 315 in the semiconductor structure 300m can be connected to... Figure 2R The gate line space 215 is similar to or the same as that of the gate line space 215.

[0097] Figure 3N A semiconductor structure 300n including a stack 304 and a gate line structure 316 is shown. The stack 304 can be formed from the stack 204 by replacing the sacrificial layer 204C with a conductive layer 304A. The sacrificial layer 204C can be etched away, for example, by filling the gate line space 315 with an etchant. The conductive layer 304A can then be formed between the isolation layers 204B and replace the sacrificial layer 204C to form a new stack 304. A protective structure 305 (e.g., polyoxide) can be formed on the bottom of the gate line space 315. The gate line structure 316 can be formed by depositing a semiconductor material (e.g., polysilicon) into the gate line space 315. In some embodiments, the gate line structure 316 can have a... Figure 3N The structures shown are different. For example, gate line structure 316 may include an outer layer made of a dielectric material and an inner surface made of a semiconductor material (e.g., as shown in the reference). Figure 2T The above).

[0098] The stacked body 304, channel structure 312, and gate line structure 316 of the semiconductor structure 300n can be compared with a reference. Figure 1A-1E The corresponding components of the described semiconductor device 100 are similar or identical. (Similar to reference...) Figure 2U The semiconductor device 100 or 100-1 described herein may utilize additional manufacturing processes and / or references. Figure 3A-3N The variation of the manufacturing process described is formed by a semiconductor structure 300n.

[0099] Figure 4 A flowchart of example process 400 is shown. Process 400 can be performed to form a semiconductor device (e.g., Figure 1A-1F The semiconductor device shown is 100 or 100-1. It can be based on... Figure 2A-2U and Figure 3A-3N Describe process 400. Process 400 may include forming Figure 2A-2U This refers to one or more steps in the manufacturing process of the semiconductor structures in 3A-3N. It should be understood that the operations shown in process 400 are not exhaustive, and other operations may be performed before, after, or between any of the shown operations. Furthermore, some operations may be performed simultaneously or in conjunction with... Figure 4 The different execution sequences are shown.

[0100] In operation 402, a semiconductor structure is formed (e.g., Figure 2G The semiconductor structure 200g. The semiconductor structure includes a stack (e.g., stack 204) of sacrificial layers (e.g., sacrificial layer 204C) and isolation layers (e.g., isolation layer 204B) alternating with each other along a first direction (e.g., the Z direction).

[0101] In operation 404, a channel structure extending through the stack body along a first direction is formed (e.g., Figure 2M The channel structure 212). The channel structure includes at least a first channel structure having a top end and a bottom end along a first direction. The first channel structure includes a channel plug at the top end (e.g., channel plug 212e).

[0102] In operation 406, a gate line structure is formed (e.g., Figure 2T The gate line structure 216 includes a top portion (e.g., top portion 238) and a body portion (e.g., body portion 240) arranged along a first direction. The top portion of the gate line structure is further away from the bottom end of the first channel structure than the channel plug along the first direction.

[0103] In some embodiments, process 400 further includes depositing a dielectric layer on top of the stack (e.g., Figure 2NA dielectric layer 208 is used to cover the channel structure and gate line vias (e.g., gate line vias 217). The gate line vias are spaced apart from each other along a second direction perpendicular to the first direction (e.g., the X direction) and are filled with filler material.

[0104] In some embodiments, process 400 further includes forming trenches in the dielectric layer (e.g., Figure 2O The gate line trench 210 is used to expose the filling material in the gate line hole.

[0105] In some embodiments, process 400 further includes removing filler material from the gate line via (e.g., as referenced). Figure 2P The above).

[0106] In some embodiments, process 400 further includes forming a gate line space by extending the trench and gate line via (e.g., Figure 2R Gate line space 215 (e.g., as referenced) Figure 2Q and Figure 2R (As described). Connect the extended gate line via.

[0107] In some implementations, the gate line space includes a top portion formed by an extended trench (e.g., Figure 2R The top portion 215a) and the body portion formed by the extended gate line aperture (e.g., Figure 2R The main body portion 215b). The first section (e.g., section 244) and the second section (e.g., section 246) of the top portion are perpendicular to the first direction. The first section of the top portion is further away from the main body portion along the first direction than the second section. The dimension of the first section along a third direction (e.g., the Y direction) perpendicular to the first and second directions is greater than the dimension of the second section along the third direction.

[0108] In some implementations, the third section of the top portion (e.g., Figure 2R Section 248 is adjacent to the main body and perpendicular to the first direction. The dimension of the third section along the third direction is smaller than the dimension of the main body along the third direction (e.g., the dimension of section 249).

[0109] In some embodiments, process 400 further includes forming gate line vias and channel vias extending through the stacked body in a first direction (e.g., as referenced). Figure 2E The gate vias include gate vias in the array region of the semiconductor structure and gate vias in the connection region of the semiconductor structure. Channel structures are formed in the channel vias (e.g., as described in reference). Figure 2K , Figure 2L and Figure 2M The above).

[0110] In some embodiments, process 400 further includes forming a gate line space by extending trenches and gate line vias (e.g., as referenced). Figure 2Q and Figure 2R Prior to the above, a channel structure is formed in the channel hole (e.g., as referenced). Figure 2K , Figure 2L and Figure 2M The above). By using a high-K layer (e.g., Figure 2K A high-K layer 212a), a barrier layer (e.g., a barrier layer of the storage membrane 212b), a charge trapping layer (e.g., a charge trapping layer of the storage membrane 212b), a tunneling layer (e.g., a tunneling layer of the storage membrane 212b), a channel layer (e.g., channel layer 212c), and a core filler layer (e.g., core filler layer 212d) are deposited into each channel hole to form a channel structure.

[0111] In some implementations, forming the semiconductor structure includes multiple stacks of deposited sacrificial and insulating layers (e.g., Figure 2E The stack of layers 2041, 204-2 and 204-3, and etched by a corresponding etching process (e.g., as referenced). Figures 2A-2E The stack (e.g., stack 204) forms gate line vias and channel vias in each of the plurality of stacks.

[0112] In some embodiments, process 400 further includes removing the sacrificial layer in the stack by filling the gate line space with etchant and forming a conductive layer (e.g., conductive layer 204A) between the isolation layers in the stack (e.g., as referenced). Figure 2S The above).

[0113] In some embodiments, forming the gate line structure includes forming an outer layer of the gate line structure by depositing a dielectric material on the inner surface of the gate line space (e.g., Figure 2T The outer layer 234); and the inner layer (e.g., formed by depositing semiconductor material into the gate line space to form the gate line structure). Figure 2T Inner layer 236).

[0114] Figure 5 A block diagram of an example system 500 is shown. System 500 may have one or more semiconductor devices (e.g., memory devices) according to one or more embodiments of this disclosure. System 500 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 5As shown, system 500 may include a host device 508 and a memory system 502 having one or more memory devices 504 and a memory controller 506. The host device 508 may include a processor of an electronic device, such as a central processing unit (CPU) or a system-on-a-chip (SoC), such as an application processor (AP). The host device 508 may be configured to send data to or receive data from one or more memory devices 504.

[0115] Memory device 504 can be any memory device disclosed in this disclosure, such as Figure 1A-1F The memory device shown is an example of a NAND flash memory. A memory controller 506 (also referred to as controller circuitry) is coupled to the memory device 504 and the host device 508. Consistent with embodiments of this disclosure, the memory device 504 may include a plurality of conductive interconnects through a cover layer, the plurality of conductive interconnects contacting conductive pads in a conductive pad layer, and the memory controller 506 may be coupled to the memory device 504 through at least one of the plurality of conductive interconnects. The memory controller 506 is configured to control the memory device 504. For example, the memory controller 506 may be configured to operate a plurality of channel structures via word lines. The memory controller 506 may manage data stored in the memory device 504 and communicate with the host device 508.

[0116] In some embodiments, the memory controller 506 is designed / configured to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 506 is designed / configured to operate in high duty cycle environments, such as SSDs or embedded multimedia cards (eMMCs) (which serve as data storage devices in mobile devices such as smartphones, tablets, laptops, etc.) and enterprise storage arrays. The memory controller 506 may be configured to control the operation of the memory device 504, such as read, erase, and program (or write) operations. The memory controller 506 may also be configured to manage various functions regarding data stored or to be stored in the memory device 504, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 506 is also configured to process error correction codes (ECC) regarding data read from or written to the memory device 504. The memory controller 506 may also perform any other suitable function, such as formatting the memory device 504.

[0117] The memory controller 506 can communicate with external devices (e.g., host device 508) according to a specific communication protocol. For example, the memory controller 506 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, Fast PCI (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, Firewire protocol, etc.

[0118] The memory controller 506 and one or more memory devices 504 can be integrated into various types of storage devices, for example, included in the same package, such as a Universal Flash Storage (UFS) package or an eMMC package. That is, the memory system 502 can be implemented and packaged into different types of end electronic products. In one example, the memory controller 506 and a single memory device 504 can be integrated into a memory card 502. The memory card 502 can include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, Memory Sticks, Multimedia Cards (MMC, RS-MMC, MMCMicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc.

[0119] The subjects and embodiments of action and operation described in this disclosure can be implemented in digital electronic circuits, in tangibly embodied computer software or firmware, or in computer hardware, including the structures disclosed in this disclosure and their structural equivalents, or combinations thereof. Embodiments of the subjects described in this disclosure can be implemented as one or more computer programs, for example, one or more modules of computer program instructions encoded on a computer program carrier for execution by or control of the operation of a data processing device. The carrier can be a tangible, non-transitory computer storage medium. Alternatively or additionally, the carrier can be an artificially generated propagation signal, such as a machine-generated electrical, optical, or electromagnetic signal, generated to encode information for transmission to a suitable receiver device for execution by the data processing device. The computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination thereof, or a portion thereof. The computer storage medium is not a propagation signal.

[0120] It should be noted that references to "an embodiment," "an embodiment," "an example embodiment," "some embodiments," "some implementations," etc., in this disclosure indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. In addition, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other implementations is within the knowledge of those skilled in the art.

[0121] Generally, terms can be understood at least partly from their usage in context. For example, the term "one or more," as used herein, depends at least partly on the context and can be used to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a," "an," or "the" can also be understood, at least partly on the context, to express either a singular or plural usage. Furthermore, the term "based on" can be understood to not necessarily convey an exclusive set of factors, but rather to allow for the presence of other factors that are not necessarily explicitly described, which also depends at least partly on the context.

[0122] It should be readily understood that the terms "on," "above," and "over" in this disclosure should be interpreted in the broadest possible sense, such that "on" means not only "directly on" something, but also includes "on" something with an intermediate feature or layer in between. Furthermore, "above" or "over" means not only "on" something, but also "above" or "over" something without an intermediate feature or layer in between (i.e., directly on).

[0123] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “down,” “above,” and “above” may be used herein to describe the relationship between one element or feature and another (or more) shown in the figures. In addition to the orientations shown in the figures, the spatial relative terms are intended to cover different orientations of the apparatus during use or process steps. The apparatus may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0124] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. A substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where a semiconductor device is formed; therefore, unless otherwise stated, the semiconductor device is formed on the top side of the substrate. The bottom surface is opposite to the top surface, so the bottom side of the substrate is opposite to the top side. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0125] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, while the top side is relatively far from the substrate. A layer may extend over the entire lower or upper layer structure, or may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of lateral planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive and contact layers (where contacts, interconnects, and / or vertical interconnect accesses (VIAs) are formed) and one or more dielectric layers.

[0126] As used herein, the term "nominal / nominally" refers to the expected or target value of a characteristic or parameter of a component or process step set during the design phase of a product or process, and the range of values ​​higher and / or lower than the expected value. As used herein, the range of values ​​may be due to slight variations in manufacturing processes or tolerances. As used herein, the term "about" indicates the value of a given quantity that may vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term "about" may indicate the value of a given quantity that varies, for example, within 10-30% of that value (e.g., ±10%, ±20%, or ±30% of the value).

[0127] In this disclosure, the terms “horizontal / horizontally / laterally” refer to a lateral surface that is nominally parallel to the substrate, and the terms “vertical” or “perpendicularly” refer to a lateral surface that is nominally perpendicular to the substrate.

[0128] As used herein, the term “3D memory” refers to a three-dimensional (3D) semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as “memory strings”, such as NAND strings) on a laterally oriented substrate, such that the memory strings extend in the vertical direction relative to the substrate.

[0129] This disclosure provides numerous different implementations or examples for achieving various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not limiting. For instance, forming a first feature above or on a second feature in the following description may include implementations in which the first and second features can be in direct contact, and may also include implementations in which an additional feature can be formed between the first and second features such that the first and second features are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples throughout this disclosure. Such repetition is for simplicity and clarity and does not, in itself, indicate a relationship between the various implementations and / or configurations discussed.

[0130] The foregoing description of a particular embodiment can be readily modified and / or adapted to various applications. Therefore, based on the teachings and guidance presented herein, such adaptations and modifications are intended to fall within the meaning and scope of equivalent variations of the disclosed embodiments.

[0131] While this disclosure contains numerous details of specific implementations, these should not be construed as limiting the scope of the claims as defined by the claims themselves, but rather as descriptions of features that may be specific to particular embodiments of the invention. Certain features described in this disclosure within the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in certain combinations and even initially claimed in this way, one or more features from the claimed combination may be removed from the combination in some cases, and the claims may be directed to sub-combinations or variations thereof.

[0132] Similarly, although operations are illustrated in the accompanying drawings and described in a specific order in the claims, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order, or to perform all of the shown operations to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the above embodiments should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0133] Specific embodiments of the subject matter have been described. Other embodiments are also within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve the desired result. As an example, the processes shown in the figures do not necessarily require the specific order or sequential order shown to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous.

[0134] The scope and extent of this disclosure should not be limited by any of the exemplary embodiments described above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A semiconductor device, comprising: A semiconductor structure comprising a stack of conductive layers and insulating layers alternating with each other along a first direction; A channel structure extending through the stack along a first direction, wherein the channel structure includes at least a first channel structure having a top end and a bottom end along the first direction, and the first channel structure includes a channel plug at the top end; and A gate line structure extending through the stack along a first direction, wherein the gate line structure includes a top portion and a body portion arranged along the first direction, and the top portion of the gate line structure is further away from the bottom end of the first channel structure than the channel plug along the first direction.

2. The semiconductor device according to claim 1, wherein, The side surface of the top portion includes a curved surface and a flat surface, and the flat surface is located between the curved surface and the main body portion along the first direction. The side surface of the main body includes a series of curved surfaces arranged along a second direction perpendicular to the first direction.

3. The semiconductor device according to claim 2, wherein, The top portion includes a first portion and a second portion arranged along the first direction, the second portion being connected to the main body portion, and the first portion being further away from the main body portion along the first direction than the second portion. Wherein, the dimension of the first part along a third direction perpendicular to the first direction and the second direction is greater than or equal to the dimension of the second part along the third direction.

4. The semiconductor device according to claim 3, wherein, The second portion of the top portion has a smaller dimension along the third direction than the main portion has a smaller dimension along the third direction.

5. The semiconductor device according to any one of claims 1 to 4, wherein, The top portion of the gate line structure extends along the first direction beyond the length of the channel plug in the range of 20 nanometers (nm) to 300 nm.

6. The semiconductor device according to any one of claims 1 to 5, wherein, The gate line structure includes an outer layer and an inner layer surrounded by the outer layer, the outer layer comprising a dielectric material and the inner layer comprising a semiconductor material.

7. The semiconductor device according to any one of claims 1 to 6, wherein, The semiconductor structure includes a semiconductor layer connected to the body portion of the gate line structure and the bottom end of the first channel structure.

8. The semiconductor device according to claim 7, wherein, The semiconductor structure is a first semiconductor structure, and the semiconductor device further includes a second semiconductor structure, the second semiconductor structure including peripheral circuitry configured to control the channel structure, and the first semiconductor structure is connected to the second semiconductor structure along the first direction.

9. The semiconductor device according to any one of claims 1 to 7, further comprising a substrate and peripheral circuitry configured to control the channel structure, the peripheral circuitry being located between the stack and the substrate along the first direction, and the peripheral circuitry being connected to the body portion of the gate line structure and the bottom end of the first channel structure.

10. A method comprising: A semiconductor structure is formed, the semiconductor structure comprising a stack of sacrificial layers and isolation layers alternating with each other along a first direction; A channel structure is formed extending through the stack along the first direction, wherein the channel structure includes at least a first channel structure having a top end and a bottom end along the first direction, and the first channel structure includes a channel plug at the top end; and A gate line structure is formed, wherein the gate line structure includes a top portion and a body portion arranged along the first direction, and the top portion of the gate line structure is further away from the bottom end of the first channel structure along the first direction than the channel plug.

11. The method of claim 10, further comprising: A dielectric layer is deposited on top of the stack to cover the channel structure and gate line vias, the gate line vias being spaced apart from each other along a second direction perpendicular to the first direction and filled with a filler material; Trenches are formed in the dielectric layer to expose the filling material in the gate line vias; Remove the filler material from the gate line via; as well as A gate line space is formed by expanding the trench and the gate line via, wherein the expanded gate line via is connected.

12. The method according to claim 11, wherein, The gate line space includes a top portion formed by an extended trench and a body portion formed by an extended gate line via. A first cross section and a second cross section of the top portion are perpendicular to the first direction. The first cross section of the top portion is further away from the body portion along the first direction than the second cross section. The dimension of the first cross section along a third direction perpendicular to both the first and second directions is greater than the dimension of the second cross section along the third direction.

13. The method according to claim 12, wherein, The third section of the top portion is adjacent to the main body portion and perpendicular to the first direction, and the dimension of the third section along the third direction is smaller than the dimension of the main body portion along the third direction.

14. The method according to any one of claims 11 to 13, further comprising: The gate line vias and channel vias are formed extending through the stack along the first direction, wherein the gate line vias include gate line vias in the array region of the semiconductor structure and gate line vias in the connection region of the semiconductor structure, and the channel structure is formed in the channel vias.

15. The method according to claim 14, wherein, Forming the semiconductor structure includes: Multiple stacks of deposited sacrificial and isolation layers, wherein the stack comprises the multiple stacks; and The gate vias and the channel vias are formed in each of the plurality of stacks by means of appropriate etching processes.

16. The method according to any one of claims 11 to 15, further comprising: The sacrificial layer in the stack is removed by filling the gate line space with etchant; as well as A conductive layer is formed between the isolation layers in the stack.

17. The method according to claim 16, wherein, Forming the gate line structure includes: The outer layer of the gate line structure is formed by depositing a dielectric material on the inner surface of the gate line space; and The inner layer of the gate line structure is formed by depositing semiconductor material into the gate line space.

18. A memory system comprising: Memory devices; as well as A memory controller, coupled to and configured to control the memory device. The memory device includes: A semiconductor structure comprising a stack of conductive layers and insulating layers alternating with each other along a first direction; A channel structure extending through the stack along the first direction, wherein the channel structure includes at least a first channel structure having a top end and a bottom end, and the first channel structure includes a channel plug in the top end; and A gate line structure extending through the stack along a first direction, wherein the gate line structure includes a top portion and a body portion arranged along the first direction, and the top portion is further away from the bottom end of the first channel structure than the channel plug along the first direction.

19. The memory system according to claim 18, wherein, The side surface of the top portion includes a curved surface and a flat surface, the flat surface being located between the curved surface and the main body portion along the first direction, and the side surface of the main body portion includes a series of curved surfaces arranged along a second direction perpendicular to the first direction.

20. The memory system according to claim 18 or claim 19, wherein, The top portion of the gate line structure extends along the first direction beyond the length of the channel plug in the range of 20 nanometers (nm) to 300 nm.

Images