Multi-core radar target detection method and device based on ft6678

Abstract

The application discloses a multi-core radar target detection method and equipment based on FT6678. The method comprises the following steps: dividing a radar range-Doppler two-dimensional matrix into a first region to be processed by core 1 and a second region to be processed by core 2, and there is an overlapping region between the first region and the second region; core 0 adjusts the first region and the second region in real time according to the task queue depth of core 1 and core 2; for the first region adjusted by core 1 and the second region adjusted by core 2, the following steps are executed in parallel: obtaining a plurality of candidate targets through a nine-square sliding window CFAR detection, and generating a candidate target list, the candidate target list comprising distance / Doppler information and peak signal-to-noise ratio of each candidate target; and determining effective targets in the plurality of candidate targets. According to the embodiment of the application, the data allocation ratio of core 1 and core 2 is adjusted in real time, and a block overlapping region is introduced, so that the cross-core joint detection of boundary targets is ensured, and high-precision and low-delay radar target detection can be realized.

Description

Technical Field

[0001] This application belongs to the field of target detection technology, and in particular relates to a multi-core radar target detection method and device based on FT6678. Background Technology

[0002] Currently, radar multi-core detection schemes suffer from the following core defects in distributed processing. First, fixed block allocation leads to load imbalance: Traditional multi-core task allocation methods are static and fixed, distributing radar data to multiple cores in a fixed proportion (e.g., 50%-50%), failing to dynamically adjust the load according to the detection scenario. However, in real-world scenarios, target distribution is non-uniform (e.g., dense clutter areas are concentrated in a certain half-region), resulting in significant differences in computational load between cores and low resource utilization. Second, target misses at block boundaries: When a target is located precisely at the boundary between core 1 and core 2, the local detection window of a single core cannot completely cover the target's energy distribution, leading to a decrease in detection probability. Summary of the Invention

[0003] This application provides a multi-core radar target detection method and device based on FT6678.

[0004] In a first aspect, embodiments of this application provide a multi-core radar target detection method based on FT6678, applied to an FT6678 heterogeneous multi-core processor, wherein the FT6678 heterogeneous multi-core processor includes core 0, core 1 and core 2; The method includes: The radar range-Doppler two-dimensional matrix is ​​divided into a first region to be processed by kernel 1 and a second region to be processed by kernel 2, with overlapping areas between the first region and the second region. Core 0 adjusts the first and second regions in real time based on the task queue depths of Core 1 and Core 2; For the first region after adjustment of core 1 and the second region after adjustment of core 2, the following steps are performed in parallel: several candidate targets are obtained by CFAR detection through a nine-square sliding window, and a candidate target list is generated, which includes the distance / Doppler information and peak signal-to-noise ratio of each candidate target; Identify the effective target from among several candidate targets.

[0005] Secondly, this application provides a multi-core radar target detection device based on FT6678, which is applied to the FT6678 heterogeneous multi-core processor, the FT6678 heterogeneous multi-core processor including core 0, core 1 and core 2; The device includes: The partitioning module is used to divide the radar range-Doppler two-dimensional matrix into a first region to be processed by kernel 1 and a second region to be processed by kernel 2, wherein there is an overlapping region between the first region and the second region; The adjustment module is used by core 0 to adjust the first and second regions in real time based on the task queue depths of core 1 and core 2. The detection module is used to perform the following steps in parallel for the first region after adjustment of core 1 and the second region after adjustment of core 2: obtain several candidate targets through CFAR detection using a nine-square sliding window, and generate a candidate target list, wherein the candidate target list includes the distance / Doppler information and peak signal-to-noise ratio of each candidate target; The determination module is used to identify the valid target among several candidate targets.

[0006] Thirdly, embodiments of this application provide an electronic device, which includes: a processor and a memory storing computer program instructions; when the processor executes the computer program instructions, it implements the steps of the multi-core radar target detection method based on FT6678 as described in any embodiment of the first aspect.

[0007] Fourthly, embodiments of this application provide a computer-readable storage medium storing computer program instructions, which, when executed by a processor, implement the steps of the multi-core radar target detection method based on FT6678 as described in any embodiment of the first aspect.

[0008] Fifthly, embodiments of this application provide a computer program product, which is stored in a storage medium and executed by at least one processor to implement the steps of the multi-core radar target detection method based on FT6678 provided in the first aspect of embodiments of this application.

[0009] The multi-core radar target detection method and device based on FT6678 in this application embodiment adjusts the data allocation ratio between core 1 and core 2 in real time by core 0 and introduces block overlapping areas to ensure cross-core joint detection of boundary targets. False alarms are eliminated through spatial consistency analysis of inter-core results, thereby achieving high-precision and low-latency radar target detection. Attached Figure Description

[0010] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a flowchart illustrating a multi-core radar target detection method based on FT6678 provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of a multi-core radar target detection device based on FT6678 provided in an embodiment of this application; Figure 3 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0012] Figure label: The FT6678-based multi-core radar target detection device 200 comprises a partitioning module 201, an adjustment module 202, a detection module 203, and a determination module 204. Electronic device 300, processor 301, memory 302, communication interface 303, bus 310. Detailed Implementation

[0013] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0014] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0015] Currently, radar multi-core detection schemes suffer from the following core defects in distributed processing. First, fixed block allocation leads to load imbalance: Traditional multi-core task allocation methods are static and fixed, distributing radar data to multiple cores in a fixed proportion (e.g., 50%-50%), failing to dynamically adjust the load based on the detection scenario. However, in real-world scenarios, target distribution is non-uniform (e.g., dense clutter areas are concentrated in a certain half-region), resulting in significant differences in computational load between cores and low resource utilization. Second, target misses at block boundaries: When a target is located precisely at the boundary between core 1 and core 2, the local detection window of a single core cannot completely cover the target's energy distribution, leading to a decrease in detection probability. Third, multi-core result conflicts and redundancy: When two cores independently detect the same physical target, duplicate markings may occur. Traditional selection rules (e.g., simply choosing the result with the highest signal-to-noise ratio) lack joint verification of target spatial consistency. Fourth, insufficient false alarm suppression in complex scenarios: Existing multi-core schemes rely solely on a single CFAR detection layer, making it difficult to verify target authenticity through local information under strong clutter interference.

[0016] The CFAR detection principle refers to statistically analyzing the background noise power of radar echo data by region through a sliding window and dynamically setting the detection threshold (such as OS-CFAR, CA-CFAR). However, its window design is simple and it is difficult to deal with the problem of multiple targets blocking the view.

[0017] Multi-core DSP architecture refers to heterogeneous multi-core processors represented by FT6678, which support shared memory and hardware acceleration units between cores. However, traditional solutions often adopt a master-slave mode (such as centralized scheduling of core 0), resulting in high communication overhead between cores.

[0018] Multi-target detection criteria refer to local density decision criteria such as 3 / 5 and 4 / 6, which are used to suppress false alarms, but are not deeply integrated with multi-core dynamic task allocation.

[0019] Radar data block processing refers to dividing the radar range-Doppler two-dimensional plane into several sub-regions and assigning them to different processor cores for parallel computation. Typical block methods include uniform block (such as horizontal / vertical equal division) and block based on prior information (such as detailed block division of key monitoring areas).

[0020] Multi-core result fusion refers to methods including simple logical merging (such as logical OR / AND) and weighted merging (based on confidence), but it lacks in-depth analysis of the correlation of the target space.

[0021] Furthermore, in related technologies, a dual-core parallel processing method is used, with core 1 and core 2 processing odd-numbered and even-numbered frame data respectively, and core 0 merging results in chronological order. Its drawbacks include: the block segmentation strategy is independent of target motion, making it prone to trajectory loss when high-speed targets move across frames; the lack of an overlapping detection region results in a high false negative rate of up to 15% for boundary targets; and the merging rule only retains the initial detection result, failing to consider multi-core collaborative verification. Specifically, if a fixed 50%-50% block segmentation is used, when the dense target area is concentrated in a certain half-region, the computational load of the corresponding core surges, leading to load imbalance between cores and increased overall processing latency; if the detection results of any core are directly selected, it is impossible to distinguish between real targets and false alarms, resulting in low target confirmation reliability.

[0022] Furthermore, a dynamic block-segmentation method based on inter-core communication has been proposed, which dynamically adjusts the block ratio of the current frame according to the target distribution of the previous frame. However, it has the following shortcomings: dynamic block-segmentation relies on historical data prediction, resulting in poor real-time performance (latency increases by more than 20%); it does not solve the conflict problem of multi-core detection results, with a duplicate labeling rate exceeding 10%. Specifically, if there is no overlapping area between blocks, targets located at the block boundary may be truncated, leading to a decrease in the detection probability of boundary targets; if only single-layer CFAR detection is relied upon, the false alarm rate is difficult to suppress in strong clutter environments, resulting in poor robustness in complex scenes.

[0023] To address the problems in the related technologies, this application provides a multi-core radar target detection method and device based on FT6678.

[0024] The multi-core radar target detection method based on FT6678 provided in this application will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.

[0025] It should be noted that the embodiments of this application are applied to the FT6678 heterogeneous multi-core processor. Specifically, the FT6678 heterogeneous multi-core processor includes core 0, core 1, and core 2.

[0026] Figure 1 A flowchart illustrating a multi-core radar target detection method based on the FT6678 according to an embodiment of this application is shown. Figure 1 As shown, the multi-core radar target detection method based on FT6678 may specifically include the following steps: S101. Divide the radar range-Doppler two-dimensional matrix into a first region to be processed by kernel 1 and a second region to be processed by kernel 2, wherein there is an overlapping region between the first region and the second region. S102, Core 0 adjusts the first and second regions in real time according to the task queue depths of Core 1 and Core 2; S103. For the first region after adjustment of core 1 and the second region after adjustment of core 2, the following steps are performed in parallel: several candidate targets are obtained by CFAR detection through a nine-square sliding window, and a candidate target list is generated. The candidate target list includes the distance / Doppler information and peak signal-to-noise ratio of each candidate target. S104. Identify the effective target among several candidate targets.

[0027] Therefore, the multi-core radar target detection method and equipment based on FT6678 can achieve high-precision and low-latency radar target detection by adjusting the data allocation ratio between core 1 and core 2 in real time by core 0 and introducing block overlapping areas to ensure cross-core joint detection of boundary targets and eliminating false alarms through spatial consistency analysis of inter-core results.

[0028] The specific implementation methods for each of the above steps are described below.

[0029] In some embodiments, in S101, the input data is radar echo data, i.e., a range-Doppler two-dimensional matrix, whose size is defined as R*V, where R is the number of range elements and V is the number of Doppler elements.

[0030] Optionally, the first region includes 50% of the range cells on the left side of the radar range-Doppler two-dimensional matrix and 5% of the range cells on the right side of the radar range-Doppler two-dimensional matrix; the second region includes 50% of the range cells on the right side of the radar range-Doppler two-dimensional matrix and 5% of the range cells on the left side of the radar range-Doppler two-dimensional matrix. That is, the first region corresponding to the initial block of core 1 is: 50% of the range cells on the left side (0 ≤ r ≤ 0.5 R) + 5% overlapping area on the right side (0.5R ≤ r ≤ 0.55 R). The second region corresponding to the initial block of core 2 is: 50% of the range cells on the right side (0.5R ≤ r ≤ R) + 5% overlapping area on the left side (0.45R ≤ r ≤ 0.5R).

[0031] In other words, the radar range-Doppler plane is divided into two processing zones: Core 1 (50% overlap on the left + 5% overlap on the right) and Core 2 (50% overlap on the right + 5% overlap on the left), with the width of the overlap area configurable. By setting the overlap area, it can be ensured that boundary targets are completely covered by at least one core, thus avoiding missed detections.

[0032] It should be noted that in this embodiment, core 1 and core 2 directly access the original data in their respective allocated regions through shared memory or hardware-accelerated DMA to achieve data mapping without the need for full disk copying.

[0033] Furthermore, in some embodiments, in S102, dynamic load monitoring and adjustment are triggered through core 0. Specifically, the monitoring metrics include: task queue depth, which records the number of data blocks to be processed by cores 1 and 2 (each block is a continuous distance unit group); and processing latency, which is the average time for each core to complete a single block of data in real time.

[0034] In practice, core 0 periodically (e.g., every 10ms) reads the task queue depths of cores 1 and 2 and calculates the load difference rate according to the following formula: Furthermore, if the load difference rate is greater than the first preset threshold, and if core 1 is overloaded, core 0 will move the right boundary of core 1 to the left within a preset range (e.g., reduce the distance unit by 5%), and simultaneously move the left boundary of core 2 to the left, thereby expanding the adjusted second region; if core 2 is overloaded, core 0 will move the left boundary of core 2 to the right within a preset range, and simultaneously move the right boundary of core 1 to the right, thereby expanding the adjusted first region.

[0035] It should be understood that after the block regions corresponding to core 1 and / or core 2 are adjusted, the data in the newly added regions of core 1 and / or core 2 can be directly accessed through shared memory, and the data mapping can be updated without physical relocation.

[0036] Optionally, the first preset threshold can be set to 1 / 3. If the load difference rate is greater than 1 / 3, dynamic adjustment will be triggered. That is, if the task queue depth of core 1 is greater than 1.5 times that of core 2 and continues for more than 3 processing cycles, the initial block area of ​​core 2 will be expanded to the left; if the task queue depth of core 2 is greater than 1.5 times that of core 1, the block area of ​​core 1 will be expanded to the right.

[0037] It should be noted that, regarding the adjustment range limit, each adjustment shall not exceed the preset range, such as, but not limited to, 10% of the total distance unit, in order to avoid instability caused by frequent switching.

[0038] In another embodiment, the overlapping area between the first region and the second region is adjusted according to the following formula: Where W represents the width of the overlapping region, Indicates the target's maximum radial velocity. Indicates the radar frame period. Indicates distance resolution.

[0039] Taking a distance-Doppler 2D matrix with a distance element count R=1024 as an example, if the first region of core 1 is r=0 to r=512, the second region of core 2 is r=512 to r=1024, and the overlapping region is r=486 to r=512, then, in a core 1 overload scenario, if core 0 detects a queue depth of 150 for core 1 and 80 for core 2, and the calculated load difference rate is 46.7% and greater than 1 / 3, the adjustment action can include: shifting the right boundary of core 1's region 50 elements to the left to r=462, shifting the left boundary of core 2 50 elements to the left to r=462, and updating the overlapping region to r=462 to r=512. Thus, core 2 takes over the region from r=462 to r=512, and the load on core 1 decreases.

[0040] In this way, the embodiments of this application adopt a dynamic block and overlapping area coupling design, and propose to use dynamic area allocation to dynamically balance and adjust the computational load of core 1 and core 2 according to the scene, thereby improving resource utilization; in addition, 5% overlap area is reserved on the left and right sides to avoid the risk of missing the detection of targets at the boundary.

[0041] Furthermore, in some embodiments, in S103, both core 1 and core 2 employ hardware accelerators for CFAR detection to achieve parallelization of window sliding and statistical calculation. Additionally, core 1 and core 2 each divide their assigned regions into multiple sub-blocks (e.g., each block contains 128 distance units), which are then processed in parallel via a pipeline.

[0042] In practice, a nine-square sliding window CFAR detection is performed on the allocated area. The window structure consists of a 3×3 guard cell (with the target candidate area at the center) and 16 surrounding reference cells (circularly distributed). After sorting the reference cells, the 75th quantile is used as the background noise estimate, and the signal-to-noise ratio threshold is calculated. ,in, This represents the probability of a false alarm, which is a preset value. Determined by the false alarm probability. If the current cell's signal-to-noise ratio is greater than the signal-to-noise ratio threshold. If it is, then it is marked as a candidate target.

[0043] In practice, the location (distance / Doppler, r, v) and peak signal-to-noise ratio (SNR) of candidate targets are extracted, and a list of candidate targets is generated.

[0044] Furthermore, in some alternative embodiments, the candidate target list is transferred to the buffer of core 0 via inter-core shared memory or hardware-accelerated DMA (such as EDMA3).

[0045] As an optional embodiment, after S103 and before S104, the method further includes: determining whether there is a conflicting target pair for any candidate target corresponding to the adjusted first region and any candidate target corresponding to the adjusted second region.

[0046] In specific implementation, for any candidate target corresponding to the adjusted first region and any candidate target corresponding to the adjusted second region, if the distance difference between the two candidate targets is less than or equal to a second preset threshold and the Doppler difference is less than or equal to a third preset threshold, the two candidate targets are determined to be a conflicting target pair. For example, for the candidate target lists of core 1 and core 2, if the distance difference between the two candidate targets is less than or equal to a second preset threshold and the Doppler difference is less than or equal to a third preset threshold, the two candidate targets are determined to be a conflicting target pair. And Doppler unit difference If they are detected repeatedly, they are considered to be the same target and are marked as "conflicting target pair".

[0047] Furthermore, for non-conflicting targets, the detection results are directly adopted; for conflicting target pairs, the one with the higher SNR is selected as the preliminary result. Specifically, in response to the existence of conflicting target pairs, the candidate target with the lower SNR among the two candidate targets of the conflicting target pair is removed from the candidate target list. That is, for conflicting target pairs, the result with the higher SNR is selected as the preliminary output.

[0048] Furthermore, in some embodiments, in S104, the frame number of the radar echo is recorded, and detection begins from the 4th frame onwards. According to the 4 / 7 criterion, if there is no valid target in the first 4 frames, the 4 / 7 criterion is not met. If there is a valid target in the first 4 frames, the position of the valid target is recorded. Then, according to the judgment criterion, the target is continuously judged for 7 frames from the position of the valid target to determine whether the target is valid.

[0049] The judgment criteria include: and ,in, This represents the difference between the target distance in the current frame and the target distance in the previous frame. Represents distance unit, Represents the first empirical integer. This represents the difference between the target velocity in the current frame and the target velocity in the previous frame. Represents velocity unit, This represents the second empirical integer.

[0050] Furthermore, the number of targets is recorded. If the number of targets is greater than or equal to 4, a valid target is detected. Specifically, the number N of units in the area marked as targets by at least one null terminator is counted. If N ≥ 4, the target is confirmed as a real target; if N < 4, it is determined as a false alarm and is removed.

[0051] In this way, the embodiments of this application improve the detection speed to twice that of related technologies by using multi-core nine-grid CFAR and 4 / 7 criterion cascade detection, while reducing the edge target false detection rate to 1 / 5 of the traditional solution.

[0052] In some optional embodiments, core 0 includes a first buffer (Buffer A) corresponding to core 1 and a second buffer (Buffer B) corresponding to core 2. Then, when core 1 completes target detection, core 0 triggers an interrupt and reads the first buffer; when core 2 completes target detection, core 0 triggers an interrupt and reads the second buffer, and the result of core 2 is written to Buffer B, achieving a wait-free pipeline. In other words, core 0 employs a dual-buffer mechanism; when core 1 / core 2 completes the detection of the current data block, an interrupt is triggered immediately, and core 0 prioritizes processing ready data without waiting for the other core to complete.

[0053] Therefore, the multi-core radar target detection method based on FT6678 in this application embodiment designs a dynamically adjustable block mechanism to adjust the data allocation ratio between core 1 and core 2 according to the real-time computing load; introduces overlapping blocks to ensure cross-core joint detection of boundary targets; incorporates 4 / 7 criterion multi-level verification to eliminate false alarms through spatial consistency analysis of inter-core results; and constructs a hierarchical detection architecture to achieve coarse CFAR detection within the core and fine decision-making through inter-core collaboration. Thus, based on this dynamic block multi-core collaborative detection architecture, combined with the overlapping block allocation strategy and the 4 / 7 criterion multi-level verification mechanism, high-precision, low-latency radar target detection can be achieved.

[0054] Furthermore, specifically addressing the load imbalance problem caused by fixed block partitioning, the introduction of dynamic block adjustment keeps the difference in computational load between cores within 20%, resulting in a multi-core utilization rate of ≥95%. Regarding the issue of missed detection of targets at block boundaries, overlapping region allocation ensures that boundary targets are covered by both cores simultaneously, significantly improving the detection probability of boundary targets. Addressing the issues of multi-core result conflicts and redundancy, and insufficient false alarm suppression in complex scenarios, layered detection (intra-core CFAR + inter-core 4 / 7 criterion) significantly reduces the false alarm rate compared to traditional optimization methods.

[0055] It should be noted that the above description describes some embodiments of this application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0056] Based on the same technical concept, and corresponding to any of the above embodiments, this application also provides a multi-core radar target detection device 200 based on FT6678. It should be noted that this multi-core radar target detection device 200 based on FT6678 is applied to an FT6678 heterogeneous multi-core processor, which includes core 0, core 1, and core 2.

[0057] like Figure 2 As shown, the FT6678-based multi-core radar target detection device 200 may include: The partitioning module 201 is used to divide the radar range-Doppler two-dimensional matrix into a first region to be processed by kernel 1 and a second region to be processed by kernel 2, wherein there is an overlapping region between the first region and the second region. Adjustment module 202 is used for core 0 to adjust the first region and the second region in real time according to the task queue depth of core 1 and core 2; The detection module 203 is used to perform the following steps in parallel for the first region after adjustment of core 1 and the second region after adjustment of core 2: obtain several candidate targets through CFAR detection using a nine-square sliding window, and generate a candidate target list, wherein the candidate target list includes the distance / Doppler information and peak signal-to-noise ratio of each candidate target; The determination module 204 is used to determine the effective target among several candidate targets.

[0058] It should be noted that, for ease of description, the above devices are described in terms of function, divided into various modules. Of course, in implementing this application, the functions of each module can be implemented in one or more software and / or hardware.

[0059] The apparatus of the above embodiments is used to implement the corresponding multi-core radar target detection method based on FT6678 in any of the foregoing embodiments, and has the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0060] Based on the same technical concept, corresponding to any of the above embodiments, this application also provides an electronic device.

[0061] Figure 3 A schematic diagram of a more specific electronic device hardware structure provided in this embodiment is shown.

[0062] The electronic device 300 may include a processor 301 and a memory 302 storing computer program instructions.

[0063] Specifically, the processor 301 may include a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits that can be configured to implement the embodiments of this application.

[0064] Memory 302 may include mass storage for data or instructions. For example, and not limitingly, memory 302 may include a hard disk drive (HDD), floppy disk drive, flash memory, optical disk, magneto-optical disk, magnetic tape, or Universal Serial Bus (USB) drive, or a combination of two or more of these. Where appropriate, memory 302 may include removable or non-removable (or fixed) media. Where appropriate, memory 302 may be internal or external to the integrated gateway disaster recovery device. In a particular embodiment, memory 302 is non-volatile solid-state memory.

[0065] In certain embodiments, the memory may include read-only memory (ROM), random access memory (RAM), disk storage media devices, optical storage media devices, flash memory devices, and electrical, optical, or other physical / tangible memory storage devices. Thus, generally, memory includes one or more tangible (non-transitory) computer-readable storage media (e.g., memory devices) encoded with software including computer-executable instructions, and when the software is executed (e.g., by one or more processors), it is operable to perform the operations described with reference to the method according to one aspect of this application.

[0066] The processor 301 reads and executes computer program instructions stored in the memory 302 to implement any of the FT6678-based multi-core radar target detection methods in the above embodiments.

[0067] In some examples, the electronic device 300 may also include a communication interface 303 and a bus 310. For example, Figure 3 As shown, the processor 301, memory 302, and communication interface 303 are connected through bus 310 and complete communication with each other.

[0068] The communication interface 303 is mainly used to realize communication between various modules, devices, units and / or equipment in the embodiments of this application.

[0069] Bus 310 includes hardware, software, or both, that couples components of an online data traffic metering device together. For example, and not as a limitation, bus 310 may include an Accelerated Graphics Port (AGP) or other graphics bus, an Enhanced Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), HyperTransport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an Infinite Bandwidth Interconnect, a Low Pin Count (LPC) bus, a memory bus, a Microchannel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local (VLB) bus, or other suitable buses, or combinations of two or more of these. Where appropriate, bus 310 may include one or more buses. Although specific buses are described and illustrated in embodiments of this application, any suitable bus or interconnect is contemplated herein.

[0070] For example, the electronic device 300 can be a mobile phone, tablet computer, laptop computer, handheld computer, in-vehicle electronic device, ultra-mobile personal computer (UMPC), netbook, or personal digital assistant (PDA), etc.

[0071] Based on the same technical concept, corresponding to any of the methods in the above embodiments, this application also provides a non-transitory computer-readable storage medium. This computer-readable storage medium stores computer program instructions; when executed by a processor, these computer program instructions implement any of the FT6678-based multi-core radar target detection methods in the above embodiments. Examples of computer-readable storage media include non-transitory computer-readable storage media such as portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, etc.

[0072] Based on the same technical concept, corresponding to any of the above embodiments, this application also provides a computer program product, which includes computer program instructions. In some embodiments, the computer program instructions can be executed by one or more processors of a computer to cause the computer and / or the processor to execute the FT6678-based multi-core radar target detection method. Corresponding to the execution entity for each step in each embodiment of the FT6678-based multi-core radar target detection method, the processor executing the corresponding step can belong to the corresponding execution entity.

[0073] It should be clarified that this application is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of this application is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of this application.

[0074] The functional blocks shown in the above-described structural diagram can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this application are programs or code segments used to perform the required tasks. Programs or code segments can be stored on a machine-readable medium or transmitted over a transmission medium or communication link via data signals carried on a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio frequency (RF) links, etc. Code segments can be downloaded via computer networks such as the Internet, intranets, etc.

[0075] It should also be noted that the exemplary embodiments mentioned in this application describe methods or systems based on a series of steps or apparatus. However, this application is not limited to the order of the above steps; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0076] The aspects of this application have been described above with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It should be understood that each block in the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that these instructions, executable via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field-programmable logic circuit. It is also understood that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can also be implemented by dedicated hardware performing the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

[0077] The above description is merely a specific implementation of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.

Claims

1. A multi-core radar target detection method based on FT6678, characterized in that, It is applied to the FT6678 heterogeneous multi-core processor, which includes core 0, core 1 and core 2; The method includes: The radar range-Doppler two-dimensional matrix is ​​divided into a first region to be processed by kernel 1 and a second region to be processed by kernel 2, with overlapping areas between the first region and the second region. Core 0 adjusts the first and second regions in real time based on the task queue depths of Core 1 and Core 2; For the first region after adjustment of core 1 and the second region after adjustment of core 2, the following steps are performed in parallel: several candidate targets are obtained by CFAR detection through a nine-square sliding window, and a candidate target list is generated, which includes the distance / Doppler information and peak signal-to-noise ratio of each candidate target; Identify the effective target from among several candidate targets; The first region includes 50% of the range cells on the left side of the radar range-Doppler two-dimensional matrix and 5% of the range cells on the right side of the radar range-Doppler two-dimensional matrix; The second region includes the 50% range cells on the right side of the radar range-Doppler two-dimensional matrix and the 5% range cells on the left side of the radar range-Doppler two-dimensional matrix; The core 0 adjusts the first and second regions in real time based on the task queue depths of cores 1 and 2, including: Core 0 periodically reads the task queue depths of Core 1 and Core 2 and calculates the load difference rate according to the following formula: If the load difference rate is greater than the first preset threshold, and if core 1 is overloaded, core 0 will move the right boundary of core 1 to the left within a preset range, and simultaneously move the left boundary of core 2 to the left, thereby expanding the adjusted second region; if core 2 is overloaded, core 0 will move the left boundary of core 2 to the right within a preset range, and simultaneously move the right boundary of core 1 to the right, thereby expanding the adjusted first region. The core 0 adjusts the first and second regions in real time based on the task queue depths of core 1 and core 2, and also includes: The overlapping area between the first and second regions is adjusted according to the following formula: Where W represents the width of the overlapping region, Indicates the target's maximum radial velocity. Indicates the radar frame period. Indicates distance resolution.

2. The method according to claim 1, characterized in that, After obtaining several candidate targets through CFAR detection using a nine-square sliding window and generating a candidate target list, the method further includes the following step before determining the valid targets among the candidate targets: For any candidate target corresponding to the adjusted first region and any candidate target corresponding to the adjusted second region, determine whether there are conflicting target pairs; In response to the existence of a conflicting target pair, the candidate target with the lower signal-to-noise ratio among the two candidate targets of the conflicting target pair is removed from the candidate target list.

3. The method according to claim 2, characterized in that, The determination of whether there are conflicting target pairs for any candidate target corresponding to the adjusted first region and any candidate target corresponding to the adjusted second region includes: For any candidate target corresponding to the adjusted first region and any candidate target corresponding to the adjusted second region, if the distance difference between the two candidate targets is less than or equal to a second preset threshold and the Doppler difference is less than or equal to a third preset threshold, the two candidate targets are determined to be a conflicting target pair.

4. The method according to claim 1, characterized in that, The method further includes transferring the candidate target list to the buffer of core 0 via inter-core shared memory or hardware-accelerated DMA.

5. The method according to claim 4, characterized in that, Core 0 includes the first buffer corresponding to Core 1 and the second buffer corresponding to Core 2; The method further includes: When core 1 completes target detection, core 0 triggers an interrupt and reads the first buffer; when core 2 completes target detection, core 0 triggers an interrupt and reads the second buffer.

6. The method according to claim 1, characterized in that, The determination of the effective target among several candidate targets includes: Record the frame number of the radar echo, and start detection from the 4th frame onwards. According to the 4 / 7 rule, if there is no valid target in the first 4 frames, the 4 / 7 rule is not met. If there is a valid target in the first 4 frames, record the position of the valid target. Then, according to the judgment criterion, continuously judge whether the target is valid for 7 frames starting from the position of the valid target. The judgment criteria include: and ,in, This represents the difference between the target distance in the current frame and the target distance in the previous frame. Represents distance unit, Represents the first empirical integer. This represents the difference between the target velocity in the current frame and the target velocity in the previous frame. Represents velocity unit, Represents the second empirical integer; Record the number of targets. If the number of targets is greater than or equal to 4, then a valid target is found.

7. An electronic device, characterized in that, The device includes: a processor and a memory storing computer program instructions; when the processor invokes the computer program instructions, it implements the multi-core radar target detection method based on FT6678 as described in any one of claims 1-6.

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