Vectorization predicate execution instruction sequence-oriented duplicating propagation optimization method

Abstract

The invention discloses a duplicating propagation optimization method oriented to a vectorized predicate execution instruction sequence, and belongs to the field of compilation optimization. Aiming at the problems that an existing copying propagation method is difficult to adapt to strong coupling characteristics of vector variables and predicate registers, identification of copying instructions with predicate domains is insufficient, and cross-basic-block analysis is not adaptive to predicate control flows, the instructions are divided according to whether the predicate domains are contained or not, and only non-predicate instructions are optimized; constructing a control flow graph with predicates and a vector variable-register mapping and DU / UD chain; identifying a local and global rewriting relationship by combining predicate field verification; and a safety propagation rule is designed by adapting to hardware characteristics, and full-process automatic optimization is realized. According to the method, redundant memory access and register operation are reduced, code execution efficiency is improved, manual optimization dependence is reduced, the method is adaptive to architectures based on reduced instruction set computing (RISC), single instruction multiple data (SIMD), VLIW and the like, and the method is particularly suitable for high-performance computing and other scenes based on the RISC principle.

Description

Technical Field

[0001] This invention relates to the field of compiler optimization technology, specifically to a rewrite propagation optimization method for linear assembly code in vectorized predicate execution scenarios. This method distinguishes between "predicate execution instructions" and "non-predicate execution instructions" in linear assembly code. It skips the rewrite propagation process for predicate execution instructions that cannot be safely optimized due to non-unique data flow analysis, and only optimizes the rewrite propagation of non-predicate execution instructions. This improves the execution efficiency and optimization safety of vectorized predicate execution linear assembly code, and is applicable to scenarios with stringent requirements for the efficiency and semantic correctness of vectorized code, such as embedded systems and high-performance computing based on RISC principles. Background Technology

[0002] With the widespread use of devices equipped with embedded software (such as industrial control equipment and automotive chips), the quality of embedded software has become crucial to the national economy and the safety of personal life and property. Software testing is a common way to improve software quality, but traditional methods are insufficient for thoroughly testing embedded software because test cases cannot cover all possible execution scenarios.

[0003] In compiler optimization, write propagation is a key technique. Its core idea is to identify write relationships between variables in a program (i.e., assignment operations of the form x=y) and replace subsequent references to variable x with references to variable y, thereby reducing redundant variable accesses, register operations, or memory interactions and improving code execution efficiency. Write propagation is widely used in high-level language compilers. It accurately identifies write relationships through data flow analysis (such as definition-use chains (DU chains) and use-definition chains (UD chains), thus achieving effective propagation optimization.

[0004] Linear assembly, as an intermediate representation between high-level languages ​​and machine code, combines the low-level hardware relevance of assembly languages ​​with certain structured features. It is widely used in embedded systems and high-performance computing—especially in vectorized predicate execution scenarios based on Reduced Instruction Set Computing (RISC) architectures. Linear assembly requires conditional vector operations through "vector instructions + predicate registers," making it a core means of improving hardware computing power utilization. Compared to ordinary linear assembly, linear assembly code related to vectorized predicate execution has three significant characteristics: First, vector variables are strongly coupled with physical registers (including vector registers and predicate registers), and instruction semantics are deeply bound to hardware vector units and predicate control units; second, there are a large number of hardware-specific overwrite instructions with predicate fields, which are the core carriers of overwrite relationships; and third, control flow and data flow are highly integrated, requiring cross-block overwrite analysis to simultaneously adapt vector data flow and predicate control flow, significantly increasing complexity.

[0005] However, existing copy propagation methods are mainly designed for high-level languages ​​or general-purpose linear assembly code, making it difficult to adapt to the characteristics of vectorized predicate execution scenarios, and have the following significant shortcomings:

[0006] Insufficient recognition of hardware-specific rewrite instructions: Existing methods do not have a dedicated recognition mechanism for vector rewrite instructions with predicate fields. For example, the paper "Optimization of Assembly Language Programs for Embedded Devices Based on ARM Architecture" (Zhong Bing et al.) focuses on instruction scheduling and register allocation in the ARM architecture, but fails to recognize rewrite instructions with predicate fields, resulting in the omission of rewrite relationships for such instructions and limiting the optimization effect;

[0007] Poor adaptability of cross-block global rewrite analysis: Existing methods do not incorporate the control flow characteristics of vectorized predicate execution to optimize data flow analysis. For example, the linear assembler designed in the paper "Design of an Independent Software Stack for Phytium Maichuang DSP" (Shi Yang et al.) achieves automatic register allocation, but does not consider the impact of the predicate field on the effectiveness of rewrite—when propagating across basic blocks, if the rewrite instruction and the predicate field of the reference point are inconsistent, the rewrite relationship is actually invalid, but existing methods will still mispropagate, leading to semantic errors;

[0008] High dependence on manual optimization: The optimization of vectorized predicate execution code is highly dependent on expert experience. The paper "Deep Learning Programming Framework for Maichuang + MatrixZone Heterogeneous Systems" (Kang Yuhan et al.) points out that the identification and propagation of copy relationships of vectorized assembly code in heterogeneous systems requires manual intervention. Especially in scenarios with large-scale code or complex hardware architectures (such as vector operations controlled by multiple predicate registers), the efficiency is low and error-prone, optimization consistency is difficult to guarantee, and development costs are significantly increased.

[0009] Therefore, it is necessary to design a rewrite propagation optimization method that is adapted to vectorized predicate execution scenarios in order to improve code performance and reduce manual costs. Summary of the Invention

[0010] This invention aims to solve the problem that existing copy propagation methods are difficult to adapt to linear assembly code in vectorized predicate execution scenarios. Specifically, it addresses issues such as poor adaptability caused by strong coupling between vector variables and predicate registers in vectorized predicate execution, insufficient identification of vector copying with predicate fields, failure to consider predicate field consistency in cross-basic block global copy analysis, and high cost and error-proneness of manual optimization. Ultimately, it achieves automated and efficient optimization of linear assembly code using vectorized predicate execution.

[0011] To address the aforementioned technical problems, this invention provides a method for optimizing the rewrite propagation of vectorized predicate execution instruction sequences, specifically comprising the following steps:

[0012] Step 1: Linear Assembly Code Parsing and Intermediate Representation Construction

[0013] The vectorized input predicates are subjected to structured parsing of the relevant linear assembly code to generate an intermediate representation adapted to the characteristics of the hardware vector unit and the predicate control unit, specifically including:

[0014] Scan the linear assembly code and divide the instructions into two categories based on whether they contain a predicate field:

[0015] Predicate execution instructions: Vector / scalar instructions containing predicate fields are only marked as "predicate instructions" and their internal overwrite semantics are not extracted (overwrite propagation processing is skipped subsequently).

[0016] Non-predicate execution instructions: Vector / scalar instructions without a predicate field. Extract key information such as operands, vector register mapping relationships, and instruction mnemonics, with a focus on identifying the semantics of non-predicate overwrite instructions.

[0017] Control Flow Graph (CFG) Construction: Based on branch instructions (such as B, BL) and jump instructions, basic blocks (continuous, branchless instruction sequences) are divided to generate a "Control Flow Graph (CFG)" - nodes represent basic blocks, edges only label ordinary control dependencies (such as "BB1→BB2"), without any predicate condition labels, no need to adapt to predicate control flow, laying the foundation for cross-basic block rewriting analysis of non-predicate instructions.

[0018] Non-predicate variable relationship modeling: Establish a "vector variable-physical register" mapping table to record the binding relationship between vector variables and physical vector registers in non-predicate instructions; construct the definition-use chain (DU chain) and use-definition chain (UD chain) of non-predicate variables by traversing the non-predicate instruction sequence.

[0019] DU chain: records the mapping from non-predicate variable definition points (including non-predicate overwrite instructions) to all non-predicate reference points; UD chain: records the mapping from non-predicate variable reference points to all possible non-predicate definition points; variables in predicate execution instructions are not included in DU chain / UD chain analysis.

[0020] Step 2: Identification of Overwrite Relationships of Non-Predicate Execution Instructions

[0021] Based on the intermediate representation constructed in step 1, the overwriting relationship between variables is accurately identified only for non-predicate execution instructions, including local and global overwriting, while completely excluding predicate execution instructions:

[0022] Local write-over identification: Traverse the non-predicate instruction sequence within a single basic block to identify non-predicate write-over instructions of the form x=y; confirm the legality of the write-over relationship through "instruction mnemonic matching + operand semantic analysis (source / destination operands are both registers or immediate values)", for example, SMOV RA, RB can determine the write-over relationship RA=RB (non-predicate, globally valid).

[0023] Global write-over-recognition: Combining the control flow graph (CFG) and UD / DU chains, the write-over-relationship of non-predicate instructions is analyzed across basic blocks. For each non-predicate variable reference point, all possible non-predicate definition points are traced through the UD chain to filter out scenarios where the definition point is a non-predicate write-over-recognition instruction; the propagation path between the write-over-recognition instruction and the reference point is further verified: there is no redefinition of variables / registers (e.g., using defCount == 1 to determine write uniqueness), and if the condition is met, it is determined to be a globally valid write-over-recognition relationship.

[0024] Step 3: Rewrite the design and execution of propagation rules

[0025] Based on the identified non-predicate overwriting relationships and combined with the rules of overwriting propagation theory, the propagation execution logic is formulated to suit the characteristics of non-predicate instructions: explicitly skipping the overwriting propagation processing of all predicate execution instructions, and performing propagation while ensuring the semantic correctness of non-predicate instructions.

[0026] The scope of transmission has been determined:

[0027] Local copying: The propagation scope is limited to all non-predicate references within the current basic block;

[0028] Global overwrite: Based on the dominance relationships of the control flow graph (CFG) and the lifetime of the vector register, determine all non-predicate reference points that can be safely propagated by the overwrite instruction (predicate instructions do not participate in the propagation).

[0029] Hardware feature adaptation:

[0030] Register constraint adaptation: Verify that the use of the vector registers after replacement conforms to hardware constraints. For example, the 32-bit vector registers adapted to the embedded DSP cannot be used in combination with the 64-bit vector registers to avoid register conflicts.

[0031] Non-predicate instruction optimization: For non-predicate overwrite instructions such as SMOV and SMOVIL, prioritize propagating their source operands to the reference point to reduce redundant register move operations.

[0032] Step 4: Optimize code generation

[0033] After the copy propagation is completed, the legality of the modified intermediate representation is checked. The check only applies to non-predicate instructions.

[0034] 1. Register usage validity: Vector register type matches, register does not exceed bounds;

[0035] 2. Semantic consistency of instructions: The data dependencies of non-predicate instructions are not broken;

[0036] 3. Rewrite propagation integrity: All valid non-finite verb references are replaced;

[0037] After verification, optimized vectorized predicate execution linear assembly code is generated—all predicate execution instructions are retained, and the order of non-predicate instructions is regularized.

[0038] Compared with the prior art, the beneficial effects of this invention are as follows:

[0039] 1. By accurately identifying vector rewriting instructions with predicate fields and propagating their rewriting relationships, redundant vector register operations and memory accesses are reduced. In embedded DSP scenarios, this can effectively reduce the instruction execution overhead of vectorized predicate execution code, and the optimization effect is better than the rewriting propagation optimization scheme of general linear assembly code.

[0040] 2. Enhanced automated optimization capabilities: Achieve full automation of copy propagation in vectorized predicate execution scenarios, eliminating reliance on manual optimization. In large-scale vectorized linear assembly code scenarios, it can significantly shorten the optimization cycle while avoiding misjudgments caused by manual optimization, resulting in a significant improvement in optimization consistency;

[0041] 3. High adaptability and compatibility: In response to the characteristics of "strong coupling between vector register and predicate register" and "many instructions with predicate overwriting" in vectorized predicate execution, the execution logic is adapted to the overwriting propagation theory rules, which solves the adaptability problem of general overwriting propagation methods. It shows excellent compatibility on architectures based on the Reduced Instruction Set Computing (RISC) principle, especially for embedded DSPs.

[0042] 4. High optimization accuracy: Based on DU chain and UD chain analysis and predicate domain consistency verification, it ensures the validity of the rewrite relationship within the propagation range and avoids semantic errors caused by conditional branches, register redefinition, and predicate domain contradictions. Attached Figure Description

[0043] Figure 1 This is the overall architecture diagram of the present invention, showing the entire process of "linear assembly code parsing - rewrite relation identification - rewrite propagation execution - optimized code generation", which is marked with dedicated modules for vectorized predicate execution such as "predicate domain analysis unit" and "vector variable relation modeling unit".

[0044] Figure 2 This is a schematic diagram of a control flow graph with predicate control flow used in an embodiment of the present invention. Nodes represent basic blocks (BB1~BB3) used for the analysis of global write relationships across basic blocks. Detailed Implementation

[0045] The present invention will now be further described in conjunction with the accompanying drawings and specific embodiments.

[0046] Example 1: Overall Process Implementation (Based on Embedded DSP Architecture)

[0047] This embodiment uses the vectorized predicate execution of linear assembly code based on an embedded DSP architecture as an example to illustrate the specific implementation process of the present invention.

[0048] Step 1: Linear Assembly Code Parsing and Intermediate Representation Construction

[0049] First, complete the instruction classification, control flow graph (CFG) construction, and non-predicate variable relationship modeling. The core is to distinguish between "predicate execution instructions" and "non-predicate execution instructions", and do not handle the rewriting semantics of predicate instructions.

[0050] Instruction parsing and classification:

[0051] The input linear assembly code is scanned and divided into two categories based on whether it contains a predicate field (e.g., [!Rcd1_], [Rcd2_]). Predicate execution instructions include vector or scalar instructions with a predicate field, such as [!Rcd1_] SMOVRA, RB, [Rcd2_] SADD RA, RB, RC. These instructions are simply marked as "predicate instructions," and their internal copy semantics are not extracted; subsequent copy propagation processing is skipped. Non-predicate execution instructions are vector or scalar instructions without a predicate field, such as SMOVRA, RB, SMOV RB, RC, SADD RB, RC, RD. For these instructions, key information such as operands, vector register mapping relationships, and instruction mnemonics needs to be extracted. The semantics of non-predicate copy instructions are particularly important; for example, SMOV RA, RB can be clearly identified as a non-predicate copy instruction, with the corresponding copy relationship RA=RB.

[0052] Control Flow Graph (CFG) Construction:

[0053] Basic blocks are defined based on branch instructions (such as B and BL) and jump instructions in the code. A basic block is defined as a continuous, branchless sequence of instructions. A control flow graph (CFG) is generated based on these basic blocks. Nodes in the graph represent basic blocks, and edges only indicate ordinary control dependencies, such as BB1→BB2 and BB1→BB3. No predicate condition annotations are included, so there is no need to adapt to predicate control flow. This lays the foundation for subsequent cross-basic block rewriting analysis of non-predicate instructions.

[0054] Modeling nonpredicate variable relationships:

[0055] A "vector variable-physical register" mapping table is constructed to record the binding relationship between vector variables and physical vector registers in non-predicate instructions. For example, variable RS is bound to register R4, variable RA is bound to register R5, and variable RB is bound to register R6. Simultaneously, by traversing the non-predicate instruction sequence, a definition-use chain (DU chain) and a use-definition chain (UD chain) for non-predicate variables are constructed. The DU chain records the mapping from the definition point of a non-predicate variable (including non-predicate overwrite instructions) to all non-predicate reference points. For example, the DU chain of SMOV RA, RB (defining RA) will be associated with subsequent non-predicate instructions that reference RA. The UD chain records the mapping from the reference point of a non-predicate variable to all possible non-predicate definition points. For example, if a non-predicate instruction references RA, the UD chain can trace back to the definition point of RA, SMOV RA, RB. It is important to note that variables in predicate execution instructions are not included in the analysis scope of the DU chain and UD chain.

[0056] Step 2: Identification of Overwrite Relationships of Non-Predicate Execution Instructions

[0057] Based on the intermediate representation constructed in step 1, the overwrite relationship identification is performed only for non-predicate execution instructions, which is divided into local overwrite identification and global overwrite identification, eliminating the interference of predicate execution instructions throughout the process.

[0058] Partial copy recognition:

[0059] Within a single basic block, the non-predicate instruction sequence is traversed to identify non-predicate overwrite instructions of the form x=y. The identification criteria are "instruction mnemonic matching (such as SMOV, SMOVIL) + operand semantic analysis (both source and destination operands are registers or immediate values)". Taking BB1 as an example, traversing the non-predicate instructions, SMOV RA, RB can be identified as non-predicate overwrite instructions. Considering that there is no redefinition of RA and RB within this basic block, the overwrite relationship RA=RB is determined to be valid.

[0060] Global copy recognition:

[0061] Combining the control flow graph (CFG) and UD and DU chains, the overwrite relationship of non-predicate instructions is analyzed across basic blocks. Taking a non-predicate instruction in BB2 that may reference RA (such as SMOV RC, RA) as an example, all possible non-predicate definition points are traced through the UD chain, and scenarios where the definition point is a non-predicate overwrite instruction (i.e., SMOV RA, RB in BB1) are selected. The propagation path between the overwrite instruction and the reference point is further verified. In the path from BB1 to BB2, there is no reassignment of RA and RB. By judging by defCount == 1 (indicating overwrite uniqueness), it is determined that RA = RB is a globally valid overwrite relationship.

[0062] Step 3: Rewrite the dissemination execution

[0063] Based on the identified non-predicate overwrite relationship, and in accordance with the rules of overwrite propagation theory, the propagation logic is adapted to the characteristics of non-predicate instructions: explicitly skip the overwrite propagation processing of all predicate execution instructions, and perform the propagation operation on the premise of ensuring the semantic correctness of the non-predicate instructions.

[0064] The scope of transmission has been determined:

[0065] The propagation scope is determined based on the type of overwrite relation. Local overwrites are limited to all non-predicate references within the current basic block, excluding variable references in predicate instructions. Global overwrites, however, require determining all non-predicate references that the overwrite instruction can safely propagate to based on the dominance of the control flow graph (CFG) and the lifetime of vector registers. For example, propagation may only extend to basic blocks where there are no register conflicts with the overwrite instruction. It's important to note that non-predicate references within the basic block containing the predicate instruction are processed normally, but the predicate instruction itself does not participate in the propagation. For example, with the overwrite relation RA=RB, its propagation scope includes non-predicate references within BB1 (which, upon inspection, has no relevant references) and non-predicate references within BB2 (such as SMOV RC,RA). Predicate instructions such as [VRcd1_] VMOV VRA, VRB and [!Rcd2_] SADD RB, RA, RC are completely skipped during propagation.

[0066] Hardware feature adaptation:

[0067] To address the hardware-related characteristics of non-predicate instructions, the propagation rules were adjusted. First, register constraint adaptation was performed to verify whether the use of the vector register after replacement complied with hardware constraints. For example, it was confirmed that VRB is a 32-bit vector register that matches the operand width of the VMOV instruction, thus avoiding register conflicts. Second, non-predicate instruction optimization was carried out. For non-predicate overwrite instructions such as SMOV and VMOV, the source operands were propagated to the reference point first to reduce redundant register move operations.

[0068] Step 4: Optimize code generation

[0069] After the copy propagation is completed, the modified intermediate representation is validated for legality. The validation only applies to non-predicate instructions, including register usage legality (vector register type matching, registers not out of bounds), instruction semantic consistency (data dependencies of non-predicate instructions are not broken), and copy propagation integrity (all valid non-predicate references are replaced). Once the validation passes, optimized vectorized predicate execution linear assembly code is generated. All predicate execution instructions remain unchanged, while the order of non-predicate instructions is normalized to adapt to hardware execution characteristics such as vector pipeline scheduling.

[0070] Example 2: Implementation of key modules (based on code snippets)

[0071] This embodiment, based on core code snippets, illustrates the implementation details of key modules for rewrite propagation in a vectorized predicate execution scenario.

[0072] Module 1: DU Chain and UD Chain Analysis (including predicate domain annotation)

[0073] By traversing the DU and UD linked lists, the definition and reference points of vector variables are extracted, and DU and UD chains containing predicate domain information are constructed, providing a data foundation for copy relationship recognition.

[0074] start

[0075] / / Output DU chain (definition → reference)

[0076] Print "DU chain: definition point → reference point mapping"

[0077] Traverse all definition points:

[0078] Retrieve the currently defined register name and instruction number

[0079] Prints "DEF: register name (instruction number) → USE:"

[0080] Iterate through all references to this definition point:

[0081] Prints "Referencing register name (referencing instruction number),"

[0082] line break

[0083] / / Output the UD chain (reference → definition)

[0084] Print "UD chain: reference point → definition point mapping (X chains in total)"

[0085] Traverse all reference points:

[0086] Retrieve the currently referenced register name and instruction number

[0087] Prints "USE: register name (instruction number) → "

[0088] Iterate through all definition points corresponding to this reference point:

[0089] Prints "Define register name (define instruction number)"

[0090] line break

[0091] Finish

[0092] Module 2: Recognition of Overwrite Instructions with Predicates

[0093] By employing a dual approach of "instruction mnemonic + predicate domain validity" to identify hardware-specific rewrite instructions (such as [VRcd1_] VMOV, [Rcd2_] SMOV) in vectorized predicate execution scenarios, the accuracy of rewrite relationship identification is ensured.

[0094] start

[0095] Traverse all reference points:

[0096] Retrieve the instruction corresponding to the reference and the variable name to be replaced.

[0097] Iterate through all definition points in the UD chain of this reference point:

[0098] If the number of defined points is 1 (no redefinition), and the definition instruction is SMOV / VMOV:

[0099] Iterate through the operands of the defined instruction, skipping the target operand:

[0100] Retrieve the source operand name and trigger operand replacement (pass instruction, name to be replaced, source operand name).

[0101] Finish

[0102] Module 3: Operand Substitution with Predicates

[0103] By traversing the expression tree nodes of the instructions, the substitution of overridden variables is achieved while predicate domain information is preserved, ensuring the semantic consistency of vectorized predicate execution.

[0104] Function operand substitution (target instruction, old operand, new operand):

[0105] start

[0106] Iterating through the operand components of the target instruction:

[0107] If the operand is the target operand, skip.

[0108] Traversing the expression tree nodes of operands:

[0109] If a node is an operand and its value equals the old operand:

[0110] The node value has been changed to the new operand, and the replacement has been marked as successful.

[0111] If the replacement is successful:

[0112] Iterate through the source variable list of the instruction and change the old operand to the new operand.

[0113] Return replacement results

[0114] Finish

[0115] This invention effectively addresses the shortcomings of existing copy propagation methods in adapting to the characteristics of linear assembly language, such as the lack of identification of hardware-specific copy instructions and the difficulty of global copy analysis across basic blocks. It optimizes the code execution process by reducing redundant memory accesses and register operations (and can optimize instruction execution flow in embedded devices, DSPs, and other scenarios). Simultaneously, its automated optimization capabilities eliminate reliance on manual optimization, significantly shortening the optimization cycle of large-scale code, achieving extremely high optimization accuracy, and substantially reducing development costs.

[0116] This invention is applicable to scenarios with stringent code efficiency requirements, such as embedded systems and high-performance computing. Through specific implementation methods, it is demonstrated that this invention can accurately identify overwrite relationships and efficiently execute propagation optimization for linear assembly code in vectorized predicate execution scenarios, significantly improving code execution efficiency while ensuring semantic correctness. It fully meets the optimization needs of high-performance computing and embedded DSP scenarios based on the Reduced Instruction Set Computing (RISC) principle.

Claims

1. A method for optimizing the rewrite propagation of vectorized predicate execution instruction sequences, characterized in that, Includes the following steps: Step S1: Parse the linear assembly code related to vectorized predicate execution, and construct the variable-register mapping relationship and the control flow graph with predicate control flow; wherein, constructing the control flow graph with predicate control flow specifically involves: dividing the linear assembly code into basic blocks, analyzing the control dependencies between instructions, and generating a control flow graph with basic blocks as nodes and control dependencies with predicate condition annotations as edges; Step S2: Based on the static single assignment (SSA) form or dependency graph analysis, identify the overwriting relationships between variables, including local overwriting within a basic block and global overwriting across basic blocks; The local copy recognition: by traversing the instructions within the basic block, the direct assignment relationship of variables with predicate fields in adjacent instructions is identified, and the legality of the copy relationship is judged in combination with the validity of the predicate fields; The global copy recognition: Through data flow analysis with predicate constraints, it tracks the transmission of variable values ​​across basic blocks, identifies indirect copy relationships between variables, and verifies the consistency of the predicate domain on the propagation path; Step S3: Based on the rewrite propagation theory rules in the field of compiler optimization, and combined with the characteristics of vectorized predicate execution scenarios, construct safe substitution conditions. Under the premise of ensuring the semantic correctness of instructions, propagate the assignment result of the rewritten variable to all its reference points to generate optimized linear assembly code. The construction of the secure replacement conditions involves combining the vector register lifetime, predicate domain validity, and instruction data dependencies to clarify the applicable boundaries and execution logic of existing copy propagation rules in this scenario. Step S3 also includes: normalizing the propagated code, adjusting the instruction order to adapt to the hardware execution characteristics, while maintaining the logical consistency of the predicate control flow; The method improves the execution efficiency of linear assembly code by reducing memory accesses and register operations.

2. The method for rewriting and propagating linear assembly code for vectorized predicate execution according to claim 1, characterized in that, Step S1, "parse linear assembly code," specifically includes: The linear assembly code is scanned, and instructions are divided into predicate execution instructions and non-predicate execution instructions based on whether they contain a predicate field. Predicate execution instructions are vector / scalar instructions with a predicate field. The instruction type is marked as "predicate instruction", and their internal overwrite semantics are not extracted (overwrite propagation processing is skipped subsequently). Non-predicate execution instructions are vector / scalar instructions without a predicate field. Key information such as the operands, vector register mapping relationship, and instruction mnemonic are extracted, with a focus on identifying the semantics of non-predicate overwrite instructions.

3. The method for optimizing the rewrite propagation of linear assembly code for vectorized predicate execution according to claim 1, characterized in that, Step S1, "Constructing the variable-register mapping relationship," specifically involves: Establish a "vector variable-physical register" mapping table to record the binding relationship between vector variables and physical vector registers in non-predicate instructions; at the same time, construct the definition-use chain (DU chain) and use-definition chain (UD chain) of non-predicate variables by traversing the non-predicate instruction sequence. DU chain: records the mapping from non-predicate variable definition points (including non-predicate overwrite instructions) to all non-predicate reference points; UD chain: records the mapping from non-predicate variable reference points to all possible non-predicate definition points; Variables in predicate execution instructions are not included in the DU chain / UD chain analysis.

4. The method for optimizing the rewrite propagation of linear assembly code for vectorized predicate execution according to claim 1, characterized in that, Step S2, "partial copy recognition," also includes: The validity of the overwrite relationship is confirmed by "instruction mnemonic matching + operand semantic analysis"; for example, the non-predicate instruction SMOVRA,RB can determine the overwrite relationship RA=RB (globally valid).

5. The method for optimizing the rewrite propagation of linear assembly code for vectorized predicate execution according to claim 1, characterized in that, Step S2, "global copy recognition," also includes: By combining the control flow graph (CFG) and the UD chain / DU chain, for each non-predicate variable reference point, all possible non-predicate definition points are traced through the UD chain to filter out scenarios where the definition point is a non-predicate overwrite instruction; the propagation path is further verified: no variable / register redefinition (e.g., judging overwrite uniqueness by defCount == 1), if the condition is met, it is determined to be a globally valid overwrite relationship.

6. The method for optimizing the rewrite propagation of linear assembly code for vectorized predicate execution according to claim 1, characterized in that, Step S3, "propagating the result of the overwrite variable assignment," specifically includes: Local copy propagation: The propagation scope is limited to all non-predicate reference points within the current basic block; Global write propagation: Based on the dominance relationships of the control flow graph (CFG) and the lifetime of the vector register, determine all non-predicate reference points that can be safely propagated for write instructions (predicate instructions do not participate in the propagation).

7. The method for optimizing the rewrite propagation of linear assembly code for vectorized predicate execution according to claim 6, characterized in that, During the process of "propagating the result of variable assignment", hardware characteristics are adapted based on the execution requirements of the replication propagation theory rules: Register constraint adaptation: Verify that the use of the vector registers after replacement conforms to hardware constraints. For example, the 32-bit vector registers adapted to the embedded DSP cannot be used in combination with the 64-bit vector registers to avoid register conflicts. Non-predicate instruction optimization: For non-predicate overwrite instructions such as SMOV and SMOVIL, prioritize propagating their source operands to the reference point to reduce redundant register move operations.

8. The method for optimizing the rewrite propagation of linear assembly code for vectorized predicate execution according to claim 1, characterized in that, Step S3, before "generating optimized linear assembly code," also includes a validity check, which only applies to non-predicate instructions: Register usage validity: Vector register type matches, register not out of bounds; Instruction semantic consistency: Data dependencies of non-predicate instructions are not broken; Rewrite propagation integrity: All valid non-predicate references are replaced; After successful verification, all predicate execution instructions are retained, and optimized linear assembly code is output.

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