Integrated compiling method and system for PSCAD simulation and device operation

Abstract

The invention discloses an integrated compiling method and system for PSCAD simulation and device operation. The method comprises the steps that S1, a compiling unit, a compiling mode and a target platform are read; s2, when the compiling mode is a simulation mode, judging a compiling unit, if the compiling unit is an operation logic of the device, turning to S3, and if the compiling unit is a POU and an operation block, turning to S5; when the compiling mode is a device operation mode, turning to S7; s3, if the number of the tasks is not less than 1, turning to S4; s4, creating an execution record, a corresponding function and a condition jump logic, and turning to S6; s5, creating a corresponding function and condition jump logic for each POU or operation block; s6, counting the functions into a list list, and turning to S7; and S7, analyzing the optimization function, compiling the three-address representation and translating the three-address representation into an instruction. According to the method, the behavior difference between simulation and a real machine can be systematically reduced, and a reliable verification basis is provided for complex system development.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of power system simulation, and relates to an integrated compiling method and system for PSCAD simulation and device operation. BACKGROUND

[0002] Power system simulation can simulate different operation scenarios through mathematical models and algorithms to provide cost-benefit analysis and scheme comparison for system design. PSCAD is widely used in the field of power system simulation as a core tool in the field of power system simulation. For simulation, it is more important to keep the design of each variable of the simulation consistent with the actual hardware operation.

[0003] The general technology at present is to first convert the logic built by the user into a representation of c / c++ and other languages, and then use other compilers (gcc, etc.) to generate target files for simulation. Since the platform and target file format are inconsistent between simulation and device operation, the compiler used for device operation is difficult to support simulation at the same time. SUMMARY

[0004] To solve the problems in the prior art, the application provides an integrated compiling method and system for PSCAD simulation and device operation, and proposes an integrated compiling scheme. The integrated compiling scheme can not only generate target files for device operation, but also generate target files for simulation. Since the integrated compiling uses the same logic file, the user does not need to repeat the development cost of building simulation logic, and the consistency of the logic behavior during operation and simulation is significantly improved. The behavior difference between simulation and actual machine is systematically reduced, the external consistency between simulation and actual operation is achieved to the greatest extent, the simulation conclusion is closer to the hardware execution, and a reliable verification basis is provided for complex system development.

[0005] The application adopts the following technical scheme.

[0006] The application provides an integrated compiling method for PSCAD simulation and device operation, which comprises the following steps: S1, read the selected compiling unit, compiling mode and target platform of the user, wherein the compiling unit is divided into the running logic of the whole device, POU and separate operation block, and the compiling mode is divided into simulation mode and device operation mode; S2, when the user-selected compiling mode is the simulation mode, judge the user-selected compiling unit, if it is the running logic of the whole device, go to S3, if it is the POU and separate operation block, go to S5; when the user-selected compiling mode is the device operation mode, collect all POUs into a function list list, and go to S7; S3, determine the number of tasks in the running logic of the judging device, if the number of tasks is not less than 1, go to S4, otherwise, report an error and end the process; S4, read the period of all tasks, calculate the greatest common divisor a of the period of all tasks and the multiple n of the period and a, create an execution record c for each task; create a corresponding function for each task and a conditional jump logic based on the c and n, and then create a unified calling interface function, go to S6; S5, create a corresponding function and a conditional jump logic based on the simulation variable Tc and the simulation time T for each POU or individual operation block; S6, count all functions into the list list, go to S7; S7, perform syntax, semantic analysis and optimization on the functions in the list list, compile the internal logic of each function into a platform-independent three-address representation and translate it into execution instructions for the target platform to organize the target file, perform PSCAD simulation or device running.

[0007] Preferably, in S1, the default target platform in the simulation mode is x86; the target platform in the device running mode includes x86, arm, risc-v.

[0008] Preferably, in S4, an initialization init function, a step step function and a termination term function are created for each task, and an End label and a conditional jump logic based on the execution record c and the multiple n are created for the step step function.

[0009] Preferably, the conditional jump logic based on the c and n is: Calculate the remainder of the execution record c divided by the multiple n, assign the remainder to the variable f, and add 1 to the execution record c; If the variable f is not 0, jump to the End label, skip the user logic in this call, otherwise execute the user logic in this call.

[0010] Preferably, in S5, an initialization init function, a step step function and a termination term function are created for each POU or individual operation block, a user-adjustable simulation variable Tc is created, and an End label and a conditional jump logic based on the simulation variable Tc and the simulation time T are created for each POU or individual operation block.

[0011] Preferably, the conditional jump logic based on the simulation variable Tc and the simulation time T is: Calculate the remainder of the simulation time T divided by the simulation variable Tc, and assign the remainder to the variable f; If the variable f is not 0, jump to the End label, skip the user logic in the corresponding POU or individual operation block, otherwise execute the user logic in the corresponding POU or individual operation block.

[0012] Preferably, in S7, the three-address representation is (opcode dst, src1, src2), wherein opcode, dst, src1, and src2 are operation code, destination operand, source operand 1, and source operand 2, respectively.

[0013] Preferably, in S7, when the user-selected compilation mode is the simulation mode, the execution instructions and the related symbolic information are organized into a dll format target file to load the simulation using PSCAD; when the user-selected compilation mode is the device running mode, the execution instructions and the related symbolic information are organized into an.o format target file to be loaded and run on the device.

[0014] The second aspect of the present application provides an integrated compilation system for PSCAD simulation and device running, comprising: The reading module is configured to read a user-selected compilation unit, a compilation mode, and a target platform for compilation, wherein the compilation unit is divided into running logic of the entire device and POU and individual operation blocks, and the compilation mode is divided into a simulation mode and a device running mode. The judgment module is configured to, when the user-selected compilation mode is the simulation mode, judge the user-selected compilation unit, and if the user-selected compilation unit is the running logic of the entire device, transfer to the device module, and if the user-selected compilation unit is the POU and individual operation blocks, transfer to the POU / operation block module; and when the user-selected compilation mode is the device running mode, collect all POUs into a function list list and transfer to the compilation module. The device module is configured to judge the number of tasks in the running logic of the device, and if the number of tasks is not less than 1, read the priority and period of all tasks, calculate the greatest common divisor a of the periods of all tasks and the multiple n of the task period and a, create an execution record c for each task, create a corresponding function for each task, and create a unified calling interface function based on the c and the conditional jump logic of n; otherwise, an error is reported and the process is ended. The POU / operation block module is configured to create a corresponding function and conditional jump logic for each POU or individual operation block, count all functions into the list list, and transfer to the compilation module. The compilation module is configured to perform syntax, semantic analysis, and optimization on all functions in the list list, compile all logics in each function into a three-address representation independent of the platform, translate the three-address representation into execution instructions of the target platform selected by the user, and organize a target file to perform PSCAD simulation or device running.

[0015] The third aspect of the present application provides a terminal, comprising a processor and a storage medium; the storage medium is used for storing instructions; the processor is used for operating according to the instructions to execute the steps of the method.

[0016] The fourth aspect of the present application provides a computer readable storage medium, having stored thereon a computer program which, when executed by a processor, implements the steps of the method.

[0017] Compared with the prior art, the present application has at least the following beneficial effects: The present application proposes an integrated compilation method and system which can not only generate target files required for simulation, but also generate target files for actual operation. Only Tc for POU and individual operation block simulation in different periods of simulation tasks and for user simulation convenience is added, and the processing procedures of other parts are consistent. This consistent system not only uses the same IEC language representation of user configuration logic on the input, but also uses the same syntax semantic analysis, optimization, address layout, register allocation, and instruction generation and other key processes of compilation, can systematically reduce the behavior difference between simulation and actual machine, and maximizes the external consistency between simulation and actual operation to make the simulation conclusion more close to the hardware execution, and provides a reliable verification basis for complex system development.

[0018] The three-address representation of the present application is independent of the target platform, and can be very conveniently translated into instructions of different target platforms without further major changes. Whether the user selects the simulation mode or the operation mode, and regardless of the target platform, this part is integrated and reused in the compilation system of the present application. Not only that, but also this part is the largest in size, the most complex in function, and the most important in role in the compilation system. The unified representation of this part is the most complex and important part in the compilation system of the present application, and the behavior is consistent when the user selects different modes and different target platforms. The significance of simulation is to simulate reality, and the simulation conclusion is more convincing under the condition of consistent behavior. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 is a flowchart of an integrated compilation method for PSCAD simulation and device operation. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical scheme and advantages of the present application clearer, the technical scheme of the present application will be described clearly and completely below in combination with the drawings in the embodiments of the present application. The embodiments described in the present application are only a part of the embodiments of the present application, but not all the embodiments. Based on the spirit of the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the present application.

[0021] Embodiment 1 of the present application provides an integrated compiling method for PSCAD simulation and device operation, as shown in the figure, the method specifically comprises the following steps: Figure 1 S1, reading the compiling unit, compiling mode and target platform selected by the user; S1.1, reading the compiling unit selected by the user, wherein the compiling unit is divided into the running logic of the whole device, POU and the single operation block; Further preferably, the compiling system reads the logic selected by the user for compiling, and the present application supports the user to select the logic (multiple tasks) of a device, POU and the single operation block as the compiling unit, so as to achieve the simulation target of different granularity; S1.2, reading the compiling mode and target platform selected by the user; the compiling mode is divided into simulation mode and device operation mode. The default target platform in the simulation mode is x86; in the device operation mode, the supported target platforms are more: x86, arm, risc-v, etc.

[0022] The user selects the compiling mode in the simulation mode and the operation mode. It is assumed that the user needs to recompile to generate a new target file after switching the compiling mode.

[0023] S2, when reading that the compiling mode selected by the user is the simulation mode, judging the compiling unit selected by the user, if it is the running logic of the whole device, turning to S3, if it is POU and the single operation block, turning to S5; when reading that the compiling mode selected by the user is the device operation mode, collecting all POUs to the function list list, and turning to S7; That is, when the user selects the simulation mode, the compiling system judges the current selected compiling unit: when the compiling unit is the running logic of the whole device, turning to S3; when the compiling unit is POU and the single operation block, turning to S5; S3, judging the number of tasks in the running logic of the device, if the number of tasks is not less than 1, turning to S4, otherwise, reporting an error and ending the process; Further preferably, usually the running logic has not less than one task, and the task is taken as the scheduling unit when running. When the compiling unit is the running logic of the whole device, the number of tasks of the current user project is checked first, and when there is no task, an error is reported and the process is ended. When there are not less than one task, turning to S4; S4, reading the priority and period of all tasks, calculating the greatest common divisor a of the periods of all tasks and the multiple n of the task period and a, creating the execution record c for each task; creating the corresponding function and the corresponding conditional jump logic based on the execution record c and the multiple n for each task, and then creating the unified calling interface function, and turning to S6; ​S4.1, read the priority, period, etc. of all tasks. Assuming the periods of tasks are t1, t2, t3,..., calculate the greatest common divisor a = gcd (t1, t2, t3,...) of all task periods and the multiples n1, n2, n3,... of a, create an execution record c for each task, the initial value of c is 0, when generating the target file of the simulation call, the task with high priority is called first; S4.2, create an initialization init function, a step function and a termination term function for each task, and create an End label and a conditional jump logic based on the execution record c and the multiple n for the step function, go to S6; The conditional jump logic based on the execution record c and the multiple n is: calculate the remainder of the execution record c divided by the multiple n, assign the remainder to a variable a, and add 1 to the execution record c; if the variable a is not 0, jump to the End label, skip the user logic in this call, otherwise execute the user logic in this call.

[0024] Specifically, three functions are created for each task, assuming the name of the task is tname, then the functions are created: interface_tname_init, interface_tname_step and interface_tname_term.

[0025] Analyze the user logic, extract global variables, and move the declaration and initialization functions of the global variables, data, etc. of the memory accessed by the user to interface_tname_init, and move the memory release to interface_tname_term.

[0026] The present application is not limited to automatically generating c / cpp, but can also directly generate the intermediate representation of the compiler, and then generate execution instructions and symbolic information from the intermediate representation. The present application preferably uses the direct generation of intermediate representation, which avoids the time cost of parsing and converting between various source languages.

[0027] The user logic is slightly more complex, an End label is created at the end of the user logic, and a conditional operation is created in front of the user logic, the user logic is converted to: f = c mod n; c++; if(0!= f) then jump End; user logic; End; The meaning is that the simulation step step during simulation should be set as the maximum common divisor a mentioned in S4, the execution of the task is executed when a is n times, otherwise the execution is skipped.

[0028] Suppose a is 1ms and the period of the task is 10ms, then n = 10, when c is 0, 10, 20, etc. 10 times, the user logic is executed, otherwise it is skipped.

[0029] In this way, all tasks are processed, and a unified calling interface function is created, that is, a unified fun_main_init function, a step fun_main_step function and an end fun_main_term function are created, and the tasks are called in the order of priority in the functions, and then S6 is turned to; For S4, the use mode of PSCAD generally requires an interface file in fortran language when loading dll, and the init, step and end functions are called in the file, which is a problem of PSCAD use mode, and the detailed process is not described in the application.

[0030] S5, create initialization init function, step function and end term function for each POU or separate operation block, create user-callable simulation variable Tc, and create End label and conditional jump logic based on simulation variable Tc and simulation time T for each POU or separate operation block; The conditional jump logic based on the simulation variable Tc and the simulation time T is: calculate the remainder of the simulation time T divided by the simulation variable Tc, and assign the remainder to the variable a; if the variable a is not 0, jump to the End label, skip the user logic in the corresponding POU or separate operation block, otherwise execute the user logic in the corresponding POU or separate operation block.

[0031] Specifically, when compiling units for POU and separate operation block, suppose the name is fun1, then interface_fun1_init and interface_fun1_term, interface_fun1_step are generated in the manner of S4.

[0032] Create variable Tc, Tc supports users to change the value of Tc during simulation to make simulation more convenient.

[0033] Approximate S4 processing is performed on the user logic: f = T mod Tc; if(0!= f) then jump End; user logic; End; Process all units to be compiled; S6, count all functions in the list, go to S7; S7, perform syntax, semantic analysis and optimization on all functions in the list, compile the logic inside each function into a platform-independent three-address representation and translate it into execution instructions for the target platform and organize the target file.

[0034] S7.1, perform syntax, semantic analysis, optimization, etc. on all functions in the list to generate a basic three-address representation (opcode, dst, src1, src2) of the approximate assembly, where opcode, dst, src1, src2 are opcode, target operand, source operand 1, source operand 2, respectively.

[0035] Assuming c = a + b, the three-address representation is: loadr0, a; (load is the opcode, r0 is the target operand, a is the source operand 1, and the following is the same) loadr1, b; addr0, r0, r1; storec, r0; S7.2, translate the three-address representation of the approximate assembly generated by S7.1 into execution instructions for the target platform selected by the user, with information such as the target platform and other information selected by the user.

[0036] When the user selects the simulation mode, the target instructions and symbol information are organized into dll format and loaded into PSCAD for simulation.

[0037] When the user selects the execution mode, the target instructions and symbol information are organized into.o format and downloaded to the device for loading and running.

[0038] The precondition for the system to be used is that the user has completed the creation of types and data and the construction of control logic according to his own needs.

[0039] The three-address representation of the present application has the advantage of being independent of the target platform, and can be very conveniently translated into instructions of different target platforms without further major changes. Regardless of the user's choice of the compilation mode, whether it is the simulation mode or the running mode, and regardless of the target platform, this part is integrated and reused in the compilation system of the present application. Not only that, but this part is the largest, the most complex and the most important part of the compilation system. The unified representation of this part makes the behavior consistent when the user selects different modes and different target platforms. The significance of simulation is to simulate reality, and the simulation conclusion is more convincing under the condition of consistent behavior.

[0040] Embodiment 2 of the present application provides an integrated compilation system for PSCAD simulation and device running, comprising: A reading module is configured to read the user-selected compilation unit, wherein the compilation unit is divided into the running logic of the entire device, POU and a single operation block; the user-selected compilation mode and the target platform of the compilation are read, wherein the compilation mode is divided into the simulation mode and the device running mode; A judgment module is configured to, when the user-selected compilation mode is the simulation mode, judge the user-selected compilation unit, if it is the running logic of the entire device, turn to the device module, if it is the POU and the single operation block, turn to the POU / operation block module; when the user-selected compilation mode is the device running mode, collect all the POUs into a function list list, and turn to the compilation module; The device module is configured to judge the number of tasks in the running logic of the device, if the number of tasks is not less than 1, read the priority and the period of all the tasks, calculate the greatest common divisor a of all the task periods and the multiple n of the task period and a, create an execution record c for each task, create a corresponding function and a corresponding conditional jump logic based on the execution record c and the multiple n for each task, and create a unified calling interface function; otherwise, an error is reported and the process is ended; The POU / operation block module is configured to create a corresponding function and a corresponding conditional jump logic for each POU or single operation block; all the functions are counted into the list list, and the compilation module is turned to; The compilation module is configured to perform syntax, semantic analysis and optimization on all the functions in the list list, compile all the logics in each function into a three-address representation independent of the platform, translate the three-address representation into the execution instructions of the target platform selected by the user, and organize a target file.

[0041] Embodiment 3 of the present application provides a terminal, comprising a processor and a storage medium; the storage medium is configured to store instructions; the processor is configured to operate according to the instructions to perform the steps of the method.

[0042] Embodiment 4 of the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method.

[0043] This invention can be applied to DC control and protection devices.

[0044] Compared with the prior art, the beneficial effects of the present invention include at least the following: This invention proposes an integrated compilation method and system that can generate not only the target files required for simulation but also the target files for actual runtime. The only difference lies in the Tc (Transmission Control) during different simulation cycles and when adding simulations of POUs and individual computation blocks for user convenience; all other processing steps remain consistent. This consistent system uses the same IEC language for user configuration logic input, and all key compilation processes—including syntax and semantic analysis, optimization, address layout, register allocation, and instruction generation—are identical. This systematically reduces the behavioral differences between simulation and actual operation, maximizing the external consistency between simulation and actual execution. This makes simulation conclusions more closely resemble hardware execution, providing a reliable verification foundation for complex system development.

[0045] The three-address representation of this invention is platform-independent and can be easily translated into instructions for different target platforms without significant modifications. Regardless of whether the user selects simulation or runtime compilation mode, or the target platform, this part is integrated and reused within the compilation system of this invention. Furthermore, this part is the largest, most complex, and most crucial component of the compilation system. This unified representation ensures that the most complex and critical part of the compilation system behaves consistently regardless of the user's chosen mode or target platform. The significance of simulation lies in mimicking reality; under this condition of consistent behavior, simulation conclusions are more convincing.

[0046] This disclosure can be a system, method, and / or computer program product. A computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for causing a processor to implement various aspects of this disclosure.

[0047] Computer readable storage media can be tangible storage media which can retain and store instructions for use by an instruction execution device. Computer readable storage media can be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of computer readable storage media include the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.

[0048] Computer readable program instructions described herein can be downloaded to respective computing / processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and / or a wireless network. The network can comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers. A network adapter card or network interface in each computing / processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing / processing device.

[0049] Computer readable program instructions for carrying out operations of the present disclosure can be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like, and conventional procedural programming languages such as the "C" programming language or similar programming languages. The computer readable program instructions can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate array (FPGA), or programmable logic array (PLA) can execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present disclosure.

[0050] Finally, it should be noted that the above-mentioned embodiments are merely used to illustrate the technical solutions of the present application, rather than limiting the present application. Although the present application has been described in detail with reference to the above-mentioned embodiments, those skilled in the art should understand that the specific embodiments of the present application can be modified or replaced equivalently without departing from the spirit and scope of the present application, and any modification or equivalent replacement without departing from the spirit and scope of the present application should be covered in the protection scope of the claims of the present application.

Claims

1. An integrated compilation method for PSCAD simulation and device operation, characterized in that, include: S1 reads the compilation unit, compilation mode and target platform selected by the user. The compilation unit is divided into the entire device's operating logic and POU and individual operation blocks. The compilation mode is divided into simulation mode and device operation mode. S2. When the user selects the simulation mode as the compilation mode, determine the compilation unit selected by the user. If it is the entire device's operating logic, go to S3. If it is a POU and a separate operation block, go to S5. When the user selects the device operation mode, collect all POUs into the function list and go to S7. S3, determine the number of tasks in the device's operating logic. If the number of tasks is not less than 1, proceed to S4; otherwise, report an error and end the process. S4, read the cycle of all tasks, calculate the greatest common divisor a of all task cycles and the multiple n of the task cycle and a, create an execution record c for each task; create a corresponding function for each task and a conditional jump logic based on c and n, then create a unified calling interface function, and go to S6; S5, create corresponding functions and conditional jump logic based on simulation variable Tc and simulation time T for each POU or individual operation block; S6, add all functions to a list, then go to S7; S7 performs syntax and semantic analysis and optimization on the functions in the list, compiles the internal logic of each function into a platform-independent three-address representation and translates it into the execution instructions of the target platform to organize the target file for PSCAD simulation or device operation.

2. The integrated compilation method for PSCAD simulation and device operation according to claim 1, characterized in that: In S1, the default target platform in the simulation mode is x86; the target platform in the device operation mode includes x86, arm, and RISC-V.

3. The integrated compilation method for PSCAD simulation and device operation according to claim 1, characterized in that: In S4, an initialization init function, a step function, and an end term function are created for each task. An End label and conditional jump logic based on the execution record c and the multiple n are created for the step function.

4. The integrated compilation method for PSCAD simulation and device operation according to claim 3, characterized in that: The conditional jump logic based on c and n is as follows: Calculate the remainder when the execution record c is divided by the multiple n, assign the remainder to the variable f, and increment the execution record c by one; If the variable f is not 0, jump to the End label and skip the user logic in this call; otherwise, execute the user logic in this call.

5. The integrated compilation method for PSCAD simulation and device operation according to claim 1, characterized in that: In S5, an initialization function (init), a step function (step), and an end function (term) are created for each POU or individual computation block. A user-adjustable simulation variable (Tc) is created, and an End label and conditional jump logic based on the simulation variable (Tc) and simulation time (T) are created for each POU or individual computation block.

6. The integrated compilation method for PSCAD simulation and device operation according to claim 5, characterized in that: The conditional jump logic based on simulation variable Tc and simulation time T is as follows: Calculate the remainder when the simulation time T is divided by the simulation variable Tc, and assign the remainder to the variable f; If variable f is not 0, jump to the End label and skip the user logic in the corresponding POU or a separate operation block; otherwise, execute the user logic in the corresponding POU or a separate operation block.

7. The integrated compilation method for PSCAD simulation and device operation according to claim 1, characterized in that: In S7, the three addresses are represented as (opcodedst, src1, src2), where opcode, dst, src1, and src2 are the opcode, the destination operand, the source operand 1, and the source operand 2, respectively.

8. The integrated compilation method for PSCAD simulation and device operation according to claim 1, characterized in that: In S7, when the user selects simulation mode as the compilation mode, the execution instructions and related symbol information are organized into a dll format object file for loading simulation using PSCAD; When the user selects device execution mode as the compilation mode, the execution instructions and related symbol information are organized into .o format object files, which are then loaded into the device for execution.

9. An integrated compilation system for PSCAD simulation and device operation, comprising the method described in any one of claims 1-8, characterized in that, The system includes: The reading module is used to read the compilation unit, compilation mode, and target platform selected by the user. The compilation unit is divided into the entire device's operating logic, POU, and individual computation blocks; the compilation mode is divided into simulation mode and device operation mode. The judgment module is used to determine the compilation unit selected by the user when the user selects the compilation mode as simulation mode. If it is the running logic of the entire device, it will switch to the device module. If it is a POU and a separate operation block, it will switch to the POU / operation block module. When the user selects the compilation mode as device running mode, it will collect all POUs into the function list and switch to the compilation module. The device module is used to determine the number of tasks in the device's operating logic. If the number of tasks is not less than 1, it reads the priority and cycle of all tasks, calculates the greatest common divisor 'a' of all task cycles and the multiple 'n' of the task cycle and 'a', creates an execution record 'c' for each task, creates a corresponding function for each task, and creates a unified calling interface function based on the conditional jump logic of 'c' and 'n'. Otherwise, it reports an error and terminates the process. The POU / operation block module is used to create corresponding functions and conditional jump logic for each POU or individual operation block; all functions are counted in a list and then transferred to the compilation module. The compilation module is used to perform syntax and semantic analysis and optimization on all functions in the list, compile all the logic inside each function into a platform-independent three-address representation, translate the three-address representation into the execution instructions of the target platform selected by the user and organize the object file for PSCAD simulation or device operation.

10. A terminal, comprising a processor and a storage medium; characterized in that: The storage medium is used to store instructions; The processor is configured to operate according to the instructions to perform the steps of the method according to any one of claims 1-8.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the program implements the steps of the method according to any one of claims 1-8.

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